JP2882206B2 - Mosaic effect generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mosaic effect generating circuit capable of obtaining a mosaic effect which is one of special effects of a television signal.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional mosaic effect generating circuit.

A conventional mosaic effect generating circuit for a television signal of this type includes an A / D (analog / digital) converter 22 for sampling and quantizing an analog video signal input from an input terminal 1 and an A / D converter. A memory 23 for storing one frame of the video signal supplied from the device 22, a counter 25 for generating a horizontal write address and a vertical write address for storing the input image in the memory 23 in the order of input. 26, a read address generator constituted by adders 28, 31 and multipliers 27, 29, 30, 32 to output a horizontal read address and a vertical read address to the memory 23, and a digital signal read from the memory 23. Into an analog signal and output terminal 33
D / A (digital / analog) output externally via
And a converter 24.

In the read address generator, a multiplier 27 multiplies the horizontal write address output from the counter 25 by a coefficient 1 / N (N is an arbitrary integer). The adder 28 performs a rounding process on the output of the multiplier 27. The multiplier 29 outputs the integer N to the output of the adder 28.
And outputs the result to the memory 23 as a horizontal read address. Similarly, the multiplier 30 multiplies the vertical write address output from the counter 26 by a coefficient 1 / M (where M is an arbitrary integer). The adder 31 performs a rounding process on the output of the multiplier 30. Then, the multiplier 32 multiplies the output of the adder 31 by the integer M, and outputs the result to the memory 23 as a vertical read address.

In the mosaic effect generating circuit configured as described above, the output of the multiplier 29 is supplied as the horizontal read address of the memory 23, and the output of the multiplier 32 is supplied as the vertical read address. The mosaic effect is generated in accordance with the digit loss determined by.

[0006]

However, the above-described conventional mosaic effect generating circuit has the following problems. That is, the adders 28 and 31 and the multiplier 2
In the read address generator constituted by 7, 29, 30, and 32, an address outside the effective range is generated at the end of the image when the mosaic effect is applied due to the relationship between the integers N and M and the number of effective pixels. Therefore, there is a disadvantage that the black level in the blanking period protrudes within the effective range.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a mosaic effect generating circuit capable of preventing a black level in a blanking period from protruding to an image edge.

[0008]

A mosaic effect generating circuit according to the present invention comprises an A / D converter for sampling and quantizing an analog video signal, and a video signal output from the A / D converter for one frame. A first and a second counter for respectively generating a horizontal write address and a vertical write address given to the memory; a coefficient 1 / N (where N is an arbitrary number) ), A first adder for performing a rounding process on the output of the first multiplier, and an output of the first adder multiplied by the integer N. A second multiplier, a first comparator and a first switch for limiting an effective range of an output of the second multiplier and outputting the horizontal read address to the memory, and the vertical write address To the coefficient 1 / M (however,
M is any integer) and a third multiplier
A second adder that performs a rounding process on the output of the multiplier, a fourth multiplier that multiplies the output of the second adder by the integer M, and an output of the fourth multiplier A second comparator and a second switch for limiting the effective range and outputting the vertical read address to the memory, and a D / A for converting a signal output from the memory into an analog video signal
And a converter.

[0009]

According to the present invention, the first comparator and the first comparator which limit the effective range of the output of the second multiplier and output a signal within the effective range to the memory as a horizontal read address.
And a second comparator and a second switch for limiting the effective range of the output of the fourth multiplier and outputting a signal within the effective range to the memory as a vertical read address. . That is, when the output of the second multiplier exceeds the effective range of the horizontal read address, the first comparator and the first switch output, for example, the maximum value of the effective range of the horizontal read address, 4 when the output of the multiplier 4 exceeds the valid range of the vertical read address.
Output the maximum value of the effective range of the vertical read address, for example. That is, in the present invention, the first comparator and the first switch act as a limiter of the horizontal read address, and prevent the horizontal read address from exceeding the maximum value of the effective range. Similarly, the second comparator and the second switch act as a vertical read address limiter to prevent the vertical read address from exceeding the maximum of its effective range. This makes it possible to prevent the black level from protruding beyond the image edge when the mosaic processing is performed.

[0010]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a mosaic effect generating circuit according to an embodiment of the present invention.

The A / D converter 2 samples and quantizes the analog video signal input from the input terminal 1. Memory 3
Stores the video signal supplied from the A / D converter 2 for one frame based on the horizontal write address and the vertical write address supplied from the counters 5 and 6, respectively. Then, the video signals stored in the memory 3 are added to the adders 8, 13,
The data is read by the horizontal read address and the vertical read address given from the read address generator constituted by the multipliers 7, 9, 12, and 14, the comparators 10 and 15, and the switches 11 and 16, and the D / A converter 4 Is output to This D /
The A converter 4 converts the digital signal read from the memory 3 into an analog signal and outputs the analog signal to the outside via the output terminal 17.

In the read address generator, a multiplier 7 multiplies the horizontal write address output from the counter 5 by a coefficient 1 / N (where N is an arbitrary integer). Adder 8
Performs a rounding process on the output of the multiplier 7. The multiplier 9 multiplies the output of the adder 8 by the integer N. The output signal P of the multiplier 9 is supplied to the comparator 10 and the switch 11
Given to. Comparator 10 compares signal P with signal Q indicating the maximum value HMAX of the effective range of the horizontal read address, and outputs the result to switch 11 as control signal S. In response to the control signal S, the switch 11 outputs one of the signal L directly supplied from the multiplier 9 and the signal H which is the maximum value HMAX of the effective range of the horizontal read address to the memory 3 as a horizontal read address. Output. That is, when P is smaller than Q (P ≦ Q), the switch 11 outputs the output of the multiplier 9 to the memory 3 as a horizontal read address as it is. On the other hand, when P is larger than Q (P>
In Q), the switch 11 outputs the signal H which is the maximum value HMAX of the effective range of the horizontal read address to the memory 3 as the horizontal read address.

Similarly, the multiplier 12 adds the coefficient 1 / M (where M
Is any integer). The adder 13 is the multiplier 1
2 is subjected to a rounding process. The multiplier 14 multiplies the output of the adder 13 by the integer M. The output signal P of the multiplier 14 is given to the comparator 15 and the switch 16. Comparator 15 compares signal P with signal Q indicating the maximum value VMAX of the effective range of the vertical read address, and outputs the result to switch 16 as control signal S. Switch 1
6 outputs to the memory 3 either the signal L directly supplied from the multiplier 14 or the signal H which is the maximum value VMAX of the effective range of the vertical read address as the vertical read address by the control signal S. . That is, when P is smaller than Q (P ≦ Q), the switch 16
4 is used as a vertical read address in memory 3
Output to On the other hand, when P is larger than Q (P> Q)
The switch 16 outputs the signal H, which is the maximum value VMAX of the effective range of the vertical read address, to the memory 3 as the vertical read address.

In this embodiment, a mosaic effect can be obtained according to the cancellation of the digits determined by the integers N and M, as in the prior art. If the output of the multiplier 9 exceeds the maximum value of the effective range of the horizontal read address, the maximum value of the effective range of the horizontal read address is output to the memory 3 as the horizontal read address. Is larger than the maximum value of the effective range of the vertical read address, the maximum value of the effective range of the vertical read address is output to the memory 3 as the vertical read address. This can prevent the black level in the blanking period from protruding to the image edge.

[0016]

As described above, in the mosaic effect generating circuit according to the present invention, the first comparator and the first switch, and the second comparator and the second switch use the horizontal read address and the vertical switch. Since an address exceeding the maximum value of the effective range of the read address is prevented from being given to the memory, the black level in the blanking period can be prevented from protruding to the image edge.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a mosaic effect generating circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional mosaic effect generating circuit.

[Explanation of symbols]

 2, 22; A / D converters 3, 23; memory 4, 24; D / A converters 5, 6, 25, 26; counters 7, 9, 12, 14, 27, 29, 30, 32; Units 8, 13, 28, 31; adders 10, 15; comparators 11, 16;

Claims (1)

(57) [Claims] 1. An A / D converter for sampling and quantizing an analog video signal, a memory for storing one frame of a video signal output from the A / D converter, and a horizontal writing provided to the memory. A first and a second counter for respectively generating an address and a vertical write address; a first multiplier for multiplying the horizontal write address by a coefficient 1 / N (where N is an arbitrary integer); A first adder for performing a rounding process on the output of the first multiplier, a second multiplier for multiplying the output of the first adder by the integer N, A first comparator and a first switch for limiting an effective range for an output and outputting the horizontal read address to the memory; and a coefficient 1 / M (where
M is any integer) and a third multiplier
A second adder that performs a rounding process on the output of the multiplier, a fourth multiplier that multiplies the output of the second adder by the integer M, and an output of the fourth multiplier A second comparator and a second switch for limiting the effective range and outputting the vertical read address to the memory, and a D / A for converting a signal output from the memory into an analog video signal
A mosaic effect generating circuit, comprising: a converter.