JP2875606B2 - Testing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a test apparatus, it is an object of the present invention to provide a test apparatus capable of stopping a micro-sequencer during operation without using a breakpoint setting pointer, a comparator and the like. For the purpose, a stack circuit to which a PUSH signal instructing to save the return address when branching to the subroutine is supplied and a POP signal to instruct to restore the return address when returning from the subroutine, a TES signal indicating the test state, and A stop instruction circuit to which the POP signal is supplied, the stop instruction circuit outputs a STOP signal based on the TES signal and the POP signal, in a test state and when returning from the subroutine,
It is configured to stop the operation of the device.

[Industrial applications]

 The present invention relates to a test device.

In a VLSI that uses a microsequencer for controlling an internal sequencer such as a high-performance microprocessor, when testing the internal operation, it is necessary to stop the sequencer during the operation. For this reason, a break function is used, but the configuration of the conventional break function is complicated. Therefore, it is desired to stop the sequencer during operation with a simple configuration.

[Conventional technology]

In recent years, VLSIs such as microprocessors have been actively enhanced in function and integration (software is embedded in the CPU), and with this, logic testing of designed circuits has become more complicated. In addition, there are problems that the development period is lengthened and the test cost is increased. The problem is that the logic depth of the VLSI becomes deeper, and it is difficult to set the internal state only by operating the external signal lines using normal functions.
This is because it is difficult to extract internal information to the outside.

Therefore, in recent VLSI, in order to solve the above problems, a circuit dedicated to testing is mounted in advance inside the VLSI,
This increases the efficiency of the test. In particular, in a high-performance VLSI such as a microprocessor or a dedicated processor, a micro-sequencer is used for internal control, and it is necessary to easily analyze a bug in a microprogram.

As a conventional test method, there is the following method for detecting a failure of a micro ROM in a manufacturing process. That is, there are a dump circuit for sequentially reading firmware such as a micro ROM and a PLA to the outside, and a break function for stopping the sequencer at a designated position and reading the internal state during operation from the outside.

The break function is a function of providing a register for setting an address (breakpoint) for stopping the micro sequencer, and stopping the micro sequencer when the set address of the register matches the address of the program counter of the micro sequencer. is there.

[Problems to be solved by the invention]

The above-mentioned break function has a problem that a register for setting a breakpoint (this is used only at the time of a test and is not used on the user side) and a comparator for comparing the set address of the register with the address of the program counter are required. . The width (bit length) of the breakpoint register is determined by the number of steps of the microprogram written in the micro ROM. In recent microprocessor microprograms, the number of steps often exceeds 1000 steps, and the register width is 10 It will be more than a bit. For this reason, the area of the VLSI increases, resulting in an increase in cost.

An object of the present invention is to provide a test apparatus that can stop a micro sequencer during operation during a test without using a breakpoint setting pointer, a comparator, and the like.

[Means for solving the problem]

According to the present invention, a POSH signal (PUSH) for instructing saving of a return address is supplied at the time of branching to a subroutine, and PO for instructing return of a return address when returning from a subroutine.
A stack circuit (5) to which a P signal (POP) is supplied, and a stop instruction circuit (9) to which a TES signal (TES) indicating the test state and the POP signal (POP) are supplied; The circuit (9) is configured to output a STOP signal (STOP) based on the TES signal (TES) and the POP signal (POP) in a test state and return from the subroutine to stop the operation of the device. It is characterized by having.

[Action]

When analyzing the internal operation of the processor controlled by the microsequencer, it is possible to analyze a defective portion by stopping the operation in a unit of a processing routine having a microprogram and testing the state. Here, a high-performance processor has a subroutine branch function so that a structured program can be performed from the viewpoint of reducing the number of steps of a microprogram and developing efficiency. In this case, the end of the processing routine can be known by detecting the return instruction from this subroutine.

Therefore, in the present invention, the operation of the micro sequencer is stopped using the return instruction from the subroutine, and the operation of the sequencer can be performed in the unit of the processing routine without requiring a breakpoint setting pointer, a comparator, and the like. Has stopped.

That is, in the present invention, the stop instruction circuit (9)
Outputs a STOP signal (STOP) when the test state is recognized by the TES signal (TES), and when the return from the subroutine is recognized by the POP signal (POP), the operation of the device is stopped. I do.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the embodiments, the present invention is applied to a drawing processing apparatus.

FIG. 2 shows a block circuit of the drawing processing apparatus.

In FIG. 2, reference numeral 100 denotes a drawing processor. The drawing processor 100 is connected to a host CPU 102, a system memory 104, and a display memory 106, and the display memory 106 is connected to a display 108. Here, the drawing processor 100 is a host bus interface unit that receives drawing commands and parameters from the host CPU 102.
The system includes a drawing operation unit 112 that analyzes a command and generates a drawing address such as a straight line or a circle, and a graphic bus interface unit 114 that performs a drawing process of a display memory (graphic memory) 106.

As shown in FIG. 3, the drawing operation unit 112 includes a micro sequencer unit 116, an ALU 118, a multiplier 120, a shifter 12
It is composed of an arithmetic unit such as 2 and a work register 124, and executes a process written in a micro ROM in the micro sequencer unit 116 based on a command given from the outside.

Next, FIG. 1 shows a block circuit of the micro sequencer section 116, and FIG. 1 shows a micro sequencer section to which a test apparatus according to an embodiment of the present invention is applied.

In FIG. 1, reference numeral 1 denotes a command decoder for generating a start address of a microinstruction by an externally applied command, 2 denotes a selector for selecting a read address of the next microinstruction, and 3 denotes a branch address. A PLA unit 4 is an incrementer for incrementing an address, 5 is a stack circuit for subroutine operation, and 6 is a micro circuit storing a micro instruction.
A ROM 7 is a microinstruction output latch (microinstruction register).

The micro sequencer controls the address to the micro ROM 6 having the micro instruction. The address contains
There are four addresses: an increment address, a branch destination address, a subroutine return address, and a command start address. One of the four addresses is selected by the selector 2. The PLA unit 3 receives signals serving as a plurality of branch conditions from each unit of the processor, and controls the selector 2 by outputting.

Microinstructions are stored in the micro ROM 6 for each command such as a line, a circle, and a fill, and common processing (drawing address calculation, DDA processing, graphic bus IF
) Are stored together as a subroutine. In practice, most of the commands are configured as a group of subroutines, and the test determines whether the state of each register or flag in the image processor is correct at the end of each subroutine. This makes it possible to efficiently perform a test inside the image processor (the present invention utilizes this point). When a branch instruction JPS to a subroutine is executed by a micro instruction, The control signal of the PLA unit 3 is supplied from the microinstruction register, and the PUSH signal (PUSH) is asserted to return to the stack circuit 5 and save the address to the stack circuit. On the other hand, when the return instruction RTS from the subroutine branch is executed by the micro instruction, the stack circuit 5
POP signal (POP) is asserted to return the address from the stack.

Next, reference numeral 9 denotes a stop instruction circuit. When the PAUSE signal (PAUSE) is asserted, the stop instruction circuit 9 outputs a STOP signal (STOP) to put the entire microsequencer into a temporarily stopped state. Restart the operation.

Further, the stop instruction circuit 9 is supplied with a TES signal (TES) indicating the test state and the POP signal (POP). The stop instruction circuit 9 is in the test state (when the TES signal is asserted) and When returning from the subroutine, the STOP signal (ST
OP) is output to stop the operation of the micro sequencer. In other words, after the execution of the subroutine, when the time point when the higher-level program (main program) returns is detected, a STOP signal (STOP) is output.

The PAUSE signal (PAUSE) and the TES signal (TES) are supplied from the host bus I / F unit 1108 (see FIG. 2) by external setting.

Next, FIGS. 4 and 5 show the configuration and operation of the stop instruction circuit of FIG. 1, respectively.

In FIG. 4, the stop instruction circuit 9 includes an OR circuit 22 and an AND circuit 24.

4 and 5, during normal operation (non-test state), the TES signal (TES) is negated, so that even if the POP signal (POP) changes, The output is at "0" level. Therefore, the PAUSE signal (PAUS
E) changes the STOP signal (STOP).

On the other hand, during the test, the TES signal (TES) is asserted. When the return from the subroutine causes the assertion of the POP signal (POP), the output of the AND circuit 24 is at the "1" level, so that the STOP signal (STOP) is asserted, thereby stopping the operation of the sequencer. You.

〔The invention's effect〕

As described above, according to the present invention, the micro sequencer can be stopped for each subroutine in the middle of the operation at the time of the test only by providing the stop instruction circuit. Therefore, it is not necessary to provide a breakpoint setting pointer, a comparator, and the like, so that the required area is reduced, the test time is shortened (since the setting to the breakpoint setting pointer is unnecessary), and the test cost is further reduced. It is planned.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a micro-sequencer unit to which a test device according to an embodiment of the present invention is applied, FIG. 2 is a block circuit diagram of a drawing processing device, FIG. FIG. 4 is a diagram illustrating the configuration of a stop instruction circuit, and FIG. 5 is a diagram illustrating the operation of the stop instruction circuit. 5: Stack circuit 9: Stop instruction circuit 116: Micro sequencer block PUSH: PUSH signal POP: POP signal TES: TES signal STOP: STOP signal

Claims (1)

(57) [Claims] A PUSH signal (PUSH) for instructing saving of a return address when branching to a subroutine is supplied, and a PO for instructing return address restoration when returning from a subroutine.
A stack circuit (5) to which a P signal (POP) is supplied, a TES signal (TES) indicating a test state, and the POP signal (POP)
And a stop instruction circuit (9) supplied with a STOP signal. The stop instruction circuit (9) is in a test state based on the TES signal (TES) and the POP signal (POP) and returns to the STOP state when returning from the subroutine. A test apparatus configured to output a signal (STOP) and stop operation of the apparatus.