JP2869369B2 - Data read circuit in semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a data read circuit in a semiconductor memory device, and more particularly to a high speed data read circuit.

[0002]

2. Description of the Related Art Conventionally, register files, RAM, RO
2. Description of the Related Art A dynamic circuit is used as a method for configuring a large-scale circuit requiring high-speed operation such as M and PLA.

[0003] In the field of logic LSIs such as microprocessors, microcontrollers, digital signal processors, etc., large-scale built-in RAMs have conventionally been used. For example, a microprocessor has an on-chip cache, a communication LSI has a RAM for storing program and data, a digital image processing LSI and a compression / decompression LSI.
In this case, it is used as a RAM for buffering data. In a RAM for these applications, a read circuit using a latch-type sense circuit has been used as a method for realizing a stable read operation and low power consumption.

Hereinafter, as a data read circuit in a conventional semiconductor memory device, a register file read circuit (dynamic circuit) and a RAM read circuit using a latch type sense circuit will be described.

FIG. 9 shows a configuration of a conventionally used register file reading circuit.

In FIG. 9, reference numeral 901 denotes a memory cell in a register file, which is an N-channel type MOSFET.
901a and 901b and a latch circuit 901c. Reference numeral 911 denotes a large number of the memory cells 901 (1 in FIG.
902 is a connected bit line, 902 is a precharge circuit composed of a P-channel MOSFET for precharging the bit line 911 to a predetermined potential, 903
Is an inverter circuit serving as a sense circuit.

In the conventional circuit configured as described above, the precharge circuit 902 is turned on by the precharge enable line 912, and the potential of the data line 911 is precharged to the power supply potential (hereinafter abbreviated as "H"). Thereafter, when the word line 913 of the memory cell is set to “H”, when the content of the memory cell 901 is “H”, for example, the data line 911 is set.
Is discharged through the memory cell 901 to a low potential (hereinafter abbreviated as “L”). When the content of the memory cell 901 is "L", the data line 911 remains "H" because there is no current path for discharging from the data line 911. The content of the memory cell 901 is output by logically inverting the potential of the data line 911 by the inverter circuit 903 and outputting the inverted signal to the sense output line 914.

FIG. 10 shows a Japanese Patent Application No. 4-217768 filed by the present applicant (US application No. 08/10).
6,551). In this circuit, in addition to the circuit shown in FIG.
P-channel MOS that supplies a current by detecting a potential change of
An FET 951 and a current mirror circuit 960 that receives a current supplied from the MOSFET 951 and discharges the data line 961 are provided. The current mirror circuit 960 includes two N-channel MOSFETs 952, 9
53.

In the read circuit of FIG. 10, when reading, the charge of the data line 961 is discharged through the memory cell 901 and the potential of the data line 961 changes to decrease. The current mirror circuit 960 discharges the charge of the data line 961. Therefore, compared to the case where the discharge of the data line is performed only through the memory cell 901 as in the conventional example of FIG. 9, the discharge of the charge of the data line 961 can be promoted, and the reading speed can be increased. Can be.

FIG. 14 shows a main configuration of a conventional read circuit of a RAM using a latch type sense circuit.

In FIG. 14, reference numerals 1401 and 1402 denote memory cell arrays each corresponding to one column of a RAM. 1403
Denotes a memory cell of a RAM, 1432 and 1433 denote bit lines for reading / writing data of a memory cell 1403, and 1404 denotes a precharge enable line (PR).
C) The bit lines 1432 and 14
A precharge circuit for precharging and equalizing 33.

FIG. 14 shows bit lines 1432 and 1433.
Although not shown in the figure, a large number of memory cells are connected in a row direction. Although not shown, a large number of memory cells are connected to the word line (WL) 1430 in the column direction. 1405 is a column address input line (ADR)
Memory cell array 14 for one column according to the potential of 1434
A selector circuit 1406 for selecting either one of the bit lines 01 and 1402 has a column address input line (ADR) 1
434 is a buffer circuit, and 1435 and 1436 are data lines connected to the bit line selected by the selector circuit 1405. The data line 1435 is a read line for one bit of data.

1407 is a latch type sense circuit,
P-channel MOSFET 1 forming two inverters
408, 1409 and N-channel MOSFET 141
0, 1411 and N-channel MOSF for current control
ET1412, and a sense enable line (SE
N) The operation is controlled by the potential setting of 1437.

Reference numeral 1413 denotes a buffer circuit for writing, which is a write enable line (WEN) 1439.
Is "H", the data input to the input line 1438 is written to the memory cell 1403 via the data line and the bit line.

[0015] As shown in FIG.
05 and one bit line pair is selected.
(1) To reduce the area and (2) To reduce the power consumption.
That is, a memory cell can be designed with a small area by miniaturization of a process, but peripheral circuits such as a read circuit are not as small as a reduction rate of the memory cell in order to increase the speed. Therefore, arranging the read circuit and the write circuit one by one in the memory cell array of one column causes size mismatch. Therefore, a selector circuit for selecting one bit line pair from a plurality of bit line pairs is provided. Further, reducing the number of sense circuits 1407 is effective for reducing power consumption.

Next, the read operation of the RAM shown in FIG. 14 will be described with reference to the operation timing chart shown in FIG. 15, the potential waveforms corresponding to the signal line numbers of the read circuit shown in FIG. 14 are denoted by the same reference numerals as those of the signal lines.

Incidentally, the column address input line 1434 is set to “H”, and the bit lines 1432 and 1433 of the memory cell array 1401 in one column are set by the selector circuit 1405.
It is assumed that is selected. Also, the memory cell 140
It is assumed that a logical value “1” is stored in 3.

At time t1, the potential of word line 1430 is changed to "
H ”, the bit line 1433 is connected to the memory cell 1403
, And the bit line 1432 outputs “H”.

At time t2, both bit lines 1432, 1433
When the potential difference ΔVbl between them reaches a predetermined potential, the potential of the sense enable line 1437 becomes “H”. The sense circuit 1407 operates as a latch. Data line 143
5 and 1436 are connected to the bit lines 1432 and 1433 through the selector circuit 1405.
A potential change similar to that of 432 and 1433 is shown.
That is, the sense circuit 1407 includes the bit lines 1432 and 1432
33 and the data lines 1435 and 1436 are in equilibrium when the potentials are equal, but the potential difference ΔVbl
When this occurs, it operates to amplify this potential difference,
The potentials of the “H” bit line 1432 and the data line 1435 are raised to the power supply voltage VDD, and the “L” bit line 143
3 and the potential of the data line 1436 are reduced to the ground potential VSS.

When the potential of the data line 1436 becomes lower than the logical threshold at time t3, the read data is determined.

The potentials of the word line 1430, the precharge enable line 1431, and the sense enable line 1437 are
The clocks operate at almost the same clock timing. Therefore, when the word line 1430 becomes “L”, the precharge enable line 1431 and the sense enable line 1437
Also, the bit lines 1432 and 1433 and the data lines 1435 and 1436 are cut off from the sense circuit 1407, and the bit lines 1432 and 1433
And the data lines 1435 and 1436 are connected to the precharge circuit 1
Precharged and equalized by 404.

As described above, in the readout circuit using the latch type sense circuit, when a potential difference occurs in the input line pair, the latch circuit shifts from a balanced state to a non-equilibrium state and amplifies the input potential difference. And built-in RAM of a logic LSI where a large-scale logic circuit block exists
Is widely used as a readout circuit. Further, since the through current flowing through the sense circuit at the time of the read operation is small, it has a feature of low current consumption.

[0023]

However, the prior art shown in FIG. 9 has a problem that the load 920 of the bit line 911 is extremely large and the read time is long. In particular, since the memory cell is configured using a MOSFET having a small gate width for the purpose of reducing the area, the drain capacitance of the memory cell increases, and when a large number of memory cells are connected to the data lines, Since the load 920 on the line 911 is significantly increased, it takes a long time to discharge the electric charge on the data line 911, and the read time becomes long.

Further, in the technique proposed by the present applicant shown in FIG. 10, the electric charge of the data line is discharged also through the current mirror circuit 960, so that the reading speed can be increased as compared with the prior art of FIG. However, the current mirror circuit 96
Since the magnitude of the discharge current of the MOSFET 953 constituting 0 is also limited, when the load 920 of the data line 961 is increased, the effect of shortening the read time is reduced. In particular, in applications such as microprocessors, the data line length is increased due to the enlargement of the circuit, and the wiring resistance of the data line is also increased. As a result, the load capacity of the data line is increased and the read time is increased. .

Further, in the prior art shown in FIG.
There are the following problems: That is, when the size of the RAM increases, the loads on the bit lines 1432 and 1433 (the wiring load capacitance of the bit lines, the wiring resistance, and the drain capacitance of the memory cell) as described above.
Becomes larger. At the time of reading data in which one pair of bit lines is selected and connected to the data line, the latch type sense circuit 1407 discharges both the load capacitance of the data line and the large load capacitance of the bit line. Therefore, the read time becomes longer, and the sense circuit 140
7 requires a large amount of current consumption to amplify one data line to the power supply voltage VDD.

The present invention solves the above problems,
An object of the present invention is to provide a read circuit which can detect a potential change in a bit line in a short time even if a load capacitance of a bit line is large and can read data at high speed.

[0027]

In order to achieve the above object, according to the present invention, when data is read, that is, when electric charges from a bit line or a data line are discharged through a current mirror circuit or a latch type sense circuit. By arranging a transistor in the discharge path and making it equal to a state in which a part of the discharge path is cut off by the transistor, only a small capacity is discharged, the discharge speed is increased, and data reading is speeded up. In the present invention, by operating the interposed transistor in the saturation region in this way, the impedance before and after the interposed position is made close to infinity, and the space between the interposed positions is made equal to the open state.

That is, the data read circuit in the semiconductor memory device according to the present invention is precharged to a predetermined potential during a precharge period and has a first data line to which a plurality of memory cells are connected. A data read circuit in a semiconductor memory device comprising a circuit, wherein the second data line is precharged to a predetermined potential during the precharge period, and the first data line is connected to the first data line. Current supply means for detecting a potential change of
A current input terminal for inputting a supply current of the current supply means,
And a current output terminal connected to the second data line, wherein a current is supplied from the current output terminal to ground using the supply current of the current supply means input to the current input terminal as a reference current. A current mirror circuit for discharging the electric charge of the second data line; a control transistor for connecting the first data line and the second data line; and a control transistor for supplying a current to the current mirror circuit. Open control means for setting the potential of the control electrode of the transistor to an intermediate potential at which the control transistor operates in a saturation region, and equalizing the open state between the first data line and the second data line; It is characterized by having.

According to a second aspect of the present invention, in the data read circuit of the semiconductor memory device according to the first aspect, the input side is connected to the second data line, and the potential of the second data line is logically inverted. An inverter circuit having an output line to which a potential is output, and a supply current amount control which is connected to the output line of the inverter circuit and limits the amount of current supplied from the current supply means after the end of the change in the potential of the output line. Means.

According to a third aspect of the present invention, in the data read circuit of the semiconductor memory device according to the second aspect, the supply current amount control means is arranged between the current supply means and a current input terminal of the current mirror circuit. And an output line of an inverter circuit is connected to a gate of the P-channel MOSFET.

According to a fourth aspect of the present invention, in the data read circuit in the semiconductor memory device according to the second aspect, the supply current amount control means includes a P-channel MOSFET disposed between the current mirror circuit and the ground. Consisting of
An output line of an inverter circuit is connected to a gate of the P-channel MOSFET.

According to a fifth aspect of the present invention, in the data read circuit in the semiconductor memory device according to the first aspect, the data read circuit is connected to a second data line, and after the potential change of the second data line is completed, the current is reduced. A supply current amount control means for limiting the amount of current supplied from the supply means to a small amount is provided.

According to a sixth aspect of the present invention, in the data read circuit of the semiconductor memory device according to the fifth aspect, the supply current amount control means is arranged between the current supply means and the current input terminal of the current mirror circuit. And a gate of the N-channel MOSFET is connected to a second data line.

According to a seventh aspect of the present invention, in the data reading circuit of the semiconductor memory device according to the fifth aspect, the supply current amount control means includes an N-channel MOSFET disposed between the current mirror circuit and the ground. Consisting of
A second data line is connected to a gate of the N-channel MOSFET.

According to an eighth aspect of the present invention, in the data reading circuit of the semiconductor memory device according to the first aspect, the potential of the current input terminal of the current mirror circuit is forcibly set when the second data line is precharged. A disconnecting means for setting the ground potential and disconnecting the second data line and the current output terminal of the current mirror circuit is provided.

According to a ninth aspect of the present invention, there is provided the first aspect,
In the data reading circuit of the semiconductor memory device described in 2, 3, 4, 5, 6, 7, or 8, the current mirror circuit is disposed between a current input terminal and a ground line, and a control electrode is connected to the current input terminal. And a second transistor disposed between the current output terminal and the ground line and having a control electrode connected to the current input terminal.

According to a tenth aspect of the present invention, in the data reading circuit of the semiconductor memory device according to the ninth aspect, both the first and second transistors are formed of N-channel MOSFETs.

[0038] The invention according to claim 11 is the invention according to claim 1,
In the data reading circuit of the semiconductor memory device described in 2, 3, 4, 5, 6, 7, 8, 9, or 10, the current supply means is constituted by a P-channel MOSFET;
The P-channel MOSFET has a gate connected to the first data line, a source connected to the power supply line, and a current flowing from the drain as a supply current of the current supply means.

According to a twelfth aspect of the present invention, in the semiconductor memory device, the data read circuit comprises a bit line pair comprising two bit lines to which memory cells are connected, and a bit line pair comprising two data lines. And a latch type sense circuit connected to the data line pair and reading data stored in the memory cell from the bit line pair to the data line pair. In a data read circuit in a semiconductor memory device in which data can be written from a data line pair to the memory cell via the bit line pair, two control circuits arranged between the bit line pair and the data line pair A transistor, and potential control means connected to a control electrode of each of the control transistors and controlling a potential of the control electrode. The control means sets the potential of the control electrode of each control transistor to an intermediate potential that is lower than the power supply voltage and higher than the ground potential when reading data in which the latch-type sense circuit operates, so that each control transistor is in a saturation region. On the other hand, at the time of writing the data, the potential of the control electrode is set so that each control transistor operates in a linear region.

The invention according to claim 13 is the invention according to claim 12.
In the data read circuit of the semiconductor memory device described above, the latch type sense circuit includes first and second inverter circuits each having an input terminal and an output terminal, and an input terminal of the first inverter circuit and a second inverter circuit. A first input line connected to the output terminal of the inverter circuit, and a second input line connected to the output terminal of the first inverter circuit and the input terminal of the second inverter circuit, The input line pair including the first and second input lines is connected to the data line pair.

According to a fourteenth aspect, in the twelfth aspect,
In the data read circuit in the semiconductor memory device described above, a selector circuit is provided corresponding to the plurality of bit line pairs and includes a transistor disposed between the corresponding plurality of bit line pairs and the data line pair. A CMOS type transfer gate forming each selector circuit by selecting one bit line pair from the corresponding plurality of bit line pairs by the operation of the selector circuit to read and write data. A control transistor is constituted by

The invention according to claim 15 is the invention according to claim 14.
In the data read circuit in the semiconductor memory device described above, the selector circuit is provided with the same number as the number of bit lines constituting a plurality of corresponding bit line pairs, and includes a CMOS type transfer gate connected to the corresponding bit line. , Each of the CMOS type transfer gates is
A channel MOSFET and an N-channel MOSFET are provided, and the sources and drains of both MOSFETs are connected.

The invention according to claim 16 is the invention according to claim 15.
In the data read circuit of the semiconductor memory device described above, the potential control means performs a read operation to select a predetermined pair of bit lines during a read operation by selecting a C bit constituting a selector circuit.
Of the MOS transfer gates, two P-channel MOs forming two CMOS transfer gates connected to the predetermined pair of bit lines to be selected.
The gate potential of each of the SFET and the two N-channel MOSFETs is set to an intermediate potential lower than the power supply potential and higher than the ground potential, and these four MOSFETs are operated in the saturation region. In a write operation for selecting a line, the potential of each gate of two P-channel MOSFETs forming two CMOS transfer gates connected to a predetermined pair of bit lines to be selected is set to the ground potential. And two N-channel MOSFETs forming the CMOS transfer gate.
The potential of each gate is set to the power supply potential, and these four MOSFETs are operated in a linear region.

According to a seventeenth aspect of the present invention, there is provided the method according to the fifteenth aspect.
In the data read circuit of the semiconductor memory device described above, the potential control means performs a read operation to select a predetermined pair of bit lines during a read operation by selecting a C bit constituting a selector circuit.
Of the MOS transfer gates, two P-channel MOs forming two CMOS transfer gates connected to the predetermined pair of bit lines to be selected.
The potential of each gate of the SFET is set to an intermediate potential lower than the power supply potential and higher than the ground potential, and the two P-channel MOSFETs are operated in a saturation region.
The potential of each gate of the two N-channel MOSFETs constituting the OS type transfer gate is set to the ground potential to turn off the two N-channel MOSFETs, while selecting a predetermined pair of bit lines. In operation, two CMOS transfer gates 2 connected to a predetermined pair of bit lines to be selected are formed.
The potential of each gate of the two P-channel MOSFETs is set to the ground potential, and the potential of each gate of the two N-channel MOSFETs constituting the CMOS transfer gate is set to the power supply potential. MOSF
The ET operates in a linear region.

The invention according to claim 18 is the invention according to claim 16.
In the data reading circuit in the semiconductor memory device described above, two P-channel MOSFETs forming both CMOS transfer gates of the two CMOS transfer gates connected to the bit line pair
Are commonly connected to a selector signal line, the gates of two N-channel MOSFETs constituting both CMOS transfer gates are commonly connected to another selector signal line, and the potential control means When a data read operation via the bit line pair is performed immediately after a data write operation via the line pair, an equalizing means for equalizing the selector signal line and the other selector signal line is provided.

According to the above-described structure, in reading out data from the memory cell, the transistor operates in the saturation region when data is read from the memory cell, so that the first data line and the second data line are connected to each other. Becomes closer to infinity and becomes equal to the open state. as a result,
The current mirror circuit discharges only the electric charge of the second data line having a small capacity. Therefore, even if the number of memory cells connected to the first data line is large and the load capacity of the first data line is increased, the speed of discharging the second data line, that is, the speed of reading data, is increased.

In particular, according to the present invention, after the data is read, that is, after the potential of the output line or the second data line of the inverter circuit is determined, the current supply is controlled by the operation of the supply current amount control means. Since the current supply path from the means to the current mirror circuit can be cut off, unnecessary DC current flowing in the current mirror circuit is reduced.

Further, in the invention according to claim 8, when the second data line is precharged, the potential of the current input line (reference current input line) of the current mirror circuit is set to the ground potential. As a result, since the current mirror circuit is cut off from the second data line, the potential stabilization of the second data line and the shortening of the precharge time are realized.

According to the twelfth to seventeenth aspects, when data of a memory cell is read from a bit line pair to a data line pair by a latch type sense circuit, the transistor operates in a saturation region under the control of the control means. hand,
The impedance between the bit line and the data line approaches infinity and becomes equal to the open state. As a result, the latch type sense circuit discharges only the data line charges. Therefore, even if the number of memory cells connected to the bit line is large and the load capacity of the bit line is increased, the data line is discharged for a short time. And the speed of data reading is increased. On the other hand, when data is written from the data line to the memory cell via the bit line, the transistor operates in a linear region, so that the data is transmitted to the memory cell with low impedance and a high writing speed is secured.

[0050]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a circuit diagram showing a main configuration of a read circuit according to a first embodiment of the present invention.
4 shows a circuit for reading a register file.

In FIG. 1, reference numeral 101 denotes a memory cell in a register file, which is an N-channel type MOSFET 1
01a, 101b and a latch circuit 101c. 11
0 denotes a first data line (bit line) to which a large number of the memory cells 101 are connected (only one is shown in the figure), 111 denotes a second data line, and 102 denotes the first data line. P-channel type MOSF for precharging 110
A precharge circuit 103 made of ET; a P-channel MOSF 103 for precharging the second data line 111;
These two precharge circuits 102 and 103 precharge the potentials of the first and second data lines 110 and 111 to “H” by controlling the precharge enable line 112, respectively. Charge.

Reference numeral 104 denotes a P-channel MOSFET (current supply means) whose gate is connected to the first data line 110.
And its source is connected to the power supply line. This P
When the potential Vb of the first data line reaches a value represented by the following equation 1, the channel MOSFET 104 allows a current to flow from its drain to detect a change in the potential of the first data line 110.

VDD−Vtp ≧ Vb (Equation 1) Here, VDD is a power supply potential, and Vtp is a P-channel MOS.
This is the threshold voltage of the FET 104.

Reference numeral 130 denotes a current mirror circuit. The current mirror circuit 130 includes two N-channel MOs.
It comprises SFETs 105 and 106 and has a current input terminal IN and a current output terminal OUT. The current input terminal IN
Is connected to the drain of a P-channel MOSFET (electrode supply means) 104, and the current output terminal OUT is connected to the second data line 111. The one N-channel MOSF
ET (first transistor) 105 has a drain connected to the current input terminal IN, a source grounded,
The gate (control electrode) is connected to the current input terminal IN. The other N-channel MOSFET (second transistor) 106 has a drain connected to the second data line 111, a source grounded, and a gate (control electrode) connected to the current input terminal IN. .

Reference numeral 107 denotes a control transistor which is a characteristic configuration of the present invention, and is composed of a P-channel MOSFET. The MOSFET 107 has a source connected to the first data line 110 and a drain connected to the second data line 11.
1 and their gates (control electrodes) are supplied with an intermediate potential via an intermediate potential supply line 109. This intermediate potential is generated by the intermediate potential generation circuit (opening control means) 300 shown in FIG. 3, and in the present embodiment, is a potential of about 2.0 V as described later.

Next, the intermediate potential generation circuit 300 will be described. In FIG. 3A, 301 is a P-channel MOSFET for pull-up, and 302 and 304 are P-channel MOSFETs connected in series for pull-down. P-channel MOSFET 302 has a configuration in which its gate and drain are connected. 303 is the input line 31
This is an inverter circuit for logically inverting the potential setting signal input to 0. The potential of the potential setting signal 310 is “H”
Output line (the intermediate potential supply line shown in FIG. 1) 109
Becomes “H” when the P-channel MOSFET 301 is turned on. When the potential of the potential setting signal 310 is “L”, the potential of the intermediate potential supply line 109 becomes the ground line potential Vs.
The potential becomes 2 · Vtp higher than s by the threshold voltage Vtp of the P-channel MOSFETs 302 and 304.

The intermediate potential generating circuit 300 shown in FIG.
, A power supply voltage of 3.3 V, a P-channel MOSFET
Assuming that the threshold voltage Vtn of T302 and T304 is about 0.7 V, the threshold voltage Vtp increases to about 1 V due to the substrate bias effect.
The intermediate potential supplied to 9 becomes 2.0V.

In this embodiment, an inverter circuit 108 is provided for driving an output load, and the input side of the inverter circuit 108 is connected to the second data line 111. Is output to the sense output line (output line) 114.

Next, the operation of the read circuit of this embodiment will be described with reference to the operation timing chart shown in FIG. In FIG. 2, the same reference numerals as those of the signal lines are given to the potential waveforms corresponding to the signal line numbers of the read circuit shown in FIG. For comparison, FIG. 2A is a timing chart for comparison with the conventional read circuit shown in FIG.
FIG. 2B is a timing chart for comparison with the conventional sense circuit shown in FIG. All the operations in the conventional example are indicated by broken lines.

In general, the condition for turning on the MOSFET is given by Equation 2, and the condition for operating in the saturation region is given by Equation 3.

Vgs ≧ Vt (Equation 2) Vds ≧ Vgs−Vt (Equation 3) Here, Vgs is the gate-source potential, Vds is the drain-source potential, and Vt is the threshold voltage of the MOSFET. is there. Therefore, the MOSFET is turned off when Equation 2 is not satisfied, and operates in the linear region when Equation 2 is satisfied and Equation 3 is not satisfied. When both the equations 2 and 3 are satisfied, the MOSFET operates in the saturation region, that is, operates as a current source, so that current can flow in and out, but the impedance is equal to infinity. Become.

The operation will be described based on the above operating conditions. Now, it is assumed that data of a logical value “1” is stored in the memory cell 101. Also, the potential of the intermediate potential supply line 109 is Vgp, the potential of the first data line 110 is Vb, the potential of the second data line 111 is Vd,
07 is assumed to be Vtp. First data line 1
Since the potential Vb of 10 and the potential Vd of the second data line 111 change as data is read, the timing at which one or both of the above formulas 2 and 3 are satisfied according to these potential changes. Change.

One memory cell 101 storing "H"
A case in which data is read out by discharging from the memory will be described. Before data reading, both the potential Vb of the first data line 110 and the potential Vd of the second data line 111 are precharged to the power supply voltage VDD. At the initial stage of data reading, the word line 113 changes to “H”,
Discharge is started from the memory cell 101, and the potential of the first data line 100 decreases due to the discharge. In this situation, the gate-source voltage Vgs and the source-drain voltage Vds of the P-channel MOSFET 107 are as shown in Expressions 4 and 5.

Vgs = Vd−Vgp (Equation 4) Vds = Vd−Vb (Equation 5) By substituting these two equations into the above Equations 2 and 3, the ON condition equation of the P-channel MOSFET 107 becomes Expression 6 and the saturation operation condition expression are Expression 7.

Vgp ≦ Vd−Vtp (Equation 6) Vgp ≧ Vb−Vtp (Equation 7) Here, an actual numerical example will be described. Power supply voltage VD
D is set to 3.3 V, and the threshold voltage Vtp of the P-channel MOSFET 107 is set to 1.0 V in consideration of an increase due to the substrate bias effect. The gate voltage Vgp of the P-channel MOSFET 107 is the voltage generated by the intermediate potential generation circuit 300, that is, 2.0V. Therefore, at the initial stage of data reading, the on-condition expression 6 of Expression 6 is satisfied, but the saturation operation condition expression of Expression 7 is not satisfied.
Operates in the linear region.

Next, the potential Vb of the first data line 110 is
Is reduced to 3.0 V, the saturation operation condition expression of Expression 7 is satisfied, and the P-channel MOSFET 107 starts operating in the saturation region. Therefore, the impedance between the first data line 110 and the second data line 111 approaches infinity.

Thereafter, the potential Vb of the first data line 110 is
2.6V (VDD-Vtp = 3.3-0.
7), the P-channel MOSFET 104 is turned on, and a drain current flows. This P channel MOSFE
Since the drain current of T104 is input to the current mirror circuit 130 as a reference current, the current mirror circuit 1
At 30, the N-channel MO is induced by this reference current.
An output current flows to the drain of the SFET 106. This N
Since the drain of the channel MOSFET 106 is the current output terminal OUT of the current mirror circuit 130 and is connected to the second data line 111, the second data line 11
The charge of 1 is discharged by the output current of the current mirror circuit 130. At this time, the P-channel MOSFET 107
Satisfies both Equations 6 and 7 as described above, and operates in the saturation region. Therefore, the impedance between the first data line 110 and the second data line 111 is close to infinity, and the two data lines are equal to each other in an open state. Here, the load capacitance 12 of the second data line 111 is
1 is a P-channel MOSFET 103 and an N-channel M
This is the total capacitance of each drain capacitance of the OSFET 106 and the input capacitance of the inverter circuit 108, which is a small capacitance value. Therefore, the load 120 of the first data line 110,
That is, even if the total capacitance of the wiring resistance and the wiring capacitance of the first data line 110 and the drain capacitance of the plurality of memory cells 101 connected to the first data line 110 increases, the current mirror circuit 103 N-channel MOS
The FET 106 only needs to discharge the small load capacitance 121, and thus the data reading is performed at high speed.

The second by the current mirror circuit 130
Of the second data line 1 along with the discharge of the data line 111
The potential Vd of the first data line 110 is lower than the potential Vb of the first data line 110. At this time, the P-channel MOSFET
The gate-source voltage Vgs of 107 is expressed by Expression 8, and the source-drain Vds voltage is expressed by Expression 9.

Vgs = Vb−Vgp (Equation 8) Vds = Vb−Vd (Equation 9) By substituting these two equations into the above Equations 2 and 3, the ON condition of the P-channel MOSFET 107 becomes Equation 1
At 0, the saturation operating condition is given by equation 11.

Vgp ≦ Vb−Vtp (Equation 10) Vgp ≧ Vd−Vtp (Equation 11) At this time, the potential Vb of the first data line 110 is 2.6 V
(DDD-Vtp) or less, and therefore does not satisfy Equation 10;
The P-channel MOSFET 107 turns off. Accordingly, the second data line 111 is discharged through the discharge N-channel MOSFET 106 of the current mirror circuit 130 while being separated from the first data line 110.

The read time Tsn of the read circuit according to the present embodiment is, as shown in FIG.
, Time Td2, and time Tivn.
Here, during the time Td1, after the word line 113 becomes “H”, the potential Vb of the first data line 110 is changed to the power supply voltage VD.
This is the time until the potential changes to a potential (VDD−Vtp) lower than the threshold voltage V by the threshold voltage Vtp of the P-channel MOSFET 104, and the time Td 2 exceeds the threshold voltage of the P-channel MOSFET 104. After that, the time until the potential Vd of the second data line 111 exceeds the logical threshold voltage of the inverter circuit 108, the time T
inv is a delay time of the inverter circuit 108, and after the delay time Tinv elapses, the potential of the sense output line 114 is determined.

Therefore, during most of the data read operation, the second data line 111 and the first data line 110
And the impedance between discharge and N
Since the load capacitance driven by the channel MOSFET 106 can be reduced, the data reading time can be shortened.

As described above, in the present embodiment,
At the time of data reading, a potential difference is generated by discharging current from the memory cell 101 at the initial stage, and at the time of the subsequent main reading operation, the P-channel MOSFET 107 is operated and turned off in the saturation region, and the first data line 110 and the first data line 110 are turned off. Since the data read is performed with the two data lines 111 equal to the open state, the read time can be shortened.

On the other hand, in the conventional read circuit shown in FIG. 9, the discharge of the data line 911 is caused by the N-channel MOSFET in the memory cell 901 as shown in FIG.
Since the discharge is performed only at 901a and 901b, the discharge time is delayed as shown by the broken line. Delay time Tdp9 (> Td1
After + Td2), the potential of the data line 911 changes to the logical threshold voltage of the inverter circuit 903. Further, the potential of the sense output line 914 is determined after the delay time Tivp9 of the inverter circuit 903. Since the slope of the input waveform of the inverter circuit 903 is small (slow), even if the inverter circuit 903 has the same configuration as the inverter circuit 108 in FIG. 1, the delay time Tivp9 is longer than the delay time Tivn of the inverter circuit 108. Also increases. Therefore, the read time Tsp9 of the read circuit of FIG.
This is the sum of dp9 and Tivp9, which is later than the read time Tsn in the present embodiment.

Further, in the conventional read circuit shown in FIG. 10, as shown in FIG. 2B, the data line 961 is at the potential VDD lower than the power supply potential VDD by the threshold voltage Vtp.
The time required to change to -Vtp is Td1 as in the embodiment of FIG. After that, the discharge from the data line 961 is applied to the N-channel MOSFET 9 in the memory cell 901.
01a and 901b as well as the N-channel MOSFET 953 in the current mirror circuit 960.
Since the discharge current of 53 has a limit, the discharge time becomes longer as shown by the broken line. Delay time Tdp10 (> Td2)
Later, the potential of the data line 961 changes to the logical threshold voltage of the inverter circuit 954, and thereafter, the inverter circuit 9
After 54 delay times Tivp10, the potential of the sense output line 962 is determined. Since the slope of the input waveform of inverter circuit 954 is small, even if inverter circuit 954 having the same configuration as inverter circuit 108 in FIG. 1 is used, delay time Tivp10 is longer than delay time Tivn of inverter circuit 108. Therefore, the read time Tsp10 of the read circuit of FIG.
This is the sum of dp10 and the delay time Tivp10, which is later than the read time Tsn of the present embodiment.

FIG. 3B shows an intermediate potential generating circuit 3 for lowering the potential of the intermediate potential supply line 109 to the intermediate potential Vtp.
It is a block diagram of 00 '.

In FIG. 3B, reference numeral 305 denotes a P-channel MOSFET for pull-down. When the potential of the potential setting signal 310 is “H”, the potential of the intermediate potential supply line 109 becomes “H”, and the potential of the potential setting signal 310 becomes “H”.
At L ”, the potential of the intermediate potential supply line 109 becomes a voltage Vtp higher than the ground line potential by the threshold voltage Vtp of the P-channel MOSFET. The first data line 110 and the second data line 111 VDD with N-channel MOSFET
When the precharge is performed up to −Vtn, FIG.
By using the circuit described above, the conditions of Expressions 2 and 3 are satisfied, so that the P-channel MOSFET 107 can operate in the saturation region.

When the cell width of the readout circuit is larger than the width of the bit line (corresponding to the first data line) in applications such as a ROM, the bit line is used to ensure area consistency. May be arranged for selecting a column. P channel MOSFE of the present embodiment
T107 can also be used as a column selection MOSFET. A specific example in this case is shown in a fifth embodiment described later.

In the present embodiment, an N-channel MOSFET is used for the configuration of the current mirror circuit. However, a similar circuit can be configured using a P-channel MOSFET.

(Second Embodiment) FIG. 4 shows a main configuration of a read circuit according to a second embodiment of the present invention, and shows a read circuit of a register file. FIG.
The same reference numerals are given to the portions indicating the same configuration as in FIG.

In FIGS. 4A and 4B, 401,
Reference numeral 402 denotes a P-channel MOSFET, which is a P-channel MOSFET 1 according to the potential of the sense output line 114.
This is for limiting or reducing the amount of current supplied from 04 to zero.

In the read circuit shown in FIG. 4A, a P-channel MOSFET (current supply control means) 401
The source is a P-channel MOSFET (current supply means) 10
4, the drain is connected to the current input terminal IN of the current mirror circuit 130, and the gate is connected to the sense output line 114 of the inverter circuit 108.

Therefore, in the read circuit of FIG.
When the second data line 111 is precharged and the sense output line 114 is “L”, the P-channel MOSFET 4
01 is in a conductive state. At the time of subsequent data reading, the current mirror circuit 130 is switched from the P-channel MOSFET 104 in accordance with the potential drop of the first data line 110.
The current mirror circuit 130 discharges the electric charge of the second data line 111, and the electric potential of the second data line 111 decreases with this discharge, and the inverter circuit 108
When the potential of the sense output line 114 is determined to be “H”, P
Since the channel MOSFET 401 is turned off, the P-channel MOSFET 104 and the current mirror circuit 130 are turned off.
Is cut off, and no DC current flows through this readout circuit.

In the read circuit shown in FIG. 4B, a P-channel MOSFET (supply current amount control means) 4
Reference numeral 02 has a source connected to a connection point between the sources of the two N-channel MOSFETs 105 and 106 of the current mirror circuit 130, a drain grounded, and a gate connected to the sense output line 114 of the inverter circuit 108. . Therefore, in this readout circuit, the potential of the sense output line 114 is "" as in the readout circuit of FIG.
Since the DC current can be prevented from flowing needlessly at the time when it is determined to be “H”, the read time can be reduced and the power consumption can be reduced.

(Third Embodiment) FIG. 5 shows a main configuration of a read circuit according to a third embodiment of the present invention, and shows a register file read circuit. In addition, the same code | symbol is attached | subjected to the part which shows the structure similar to FIG.

In FIGS. 5A and 5B, 501,
Reference numeral 502 denotes an N-channel MOSFET for limiting the amount of current supplied from the P-channel MOSFET 104 to a small value or to zero according to the potential of the second data line 111.

In the read circuit shown in FIG. 5A, an N-channel MOSFET (supply current control means) 501
The drain is a P-channel MOSFET (current supply means) 1
The source is connected to the current input terminal 10IN of the current mirror circuit 130, and the gate is connected to the second data line 111.

Therefore, in the read circuit of FIG. 5A, when the second data line 111 is precharged to "H", the N-channel MOSFET 501 is in a conductive state, and therefore, the subsequent data read is performed. At times, a reference current flows from the P-channel MOSFET (current supply means) 104 to the current mirror circuit 130, and the charge of the second data line 111 is discharged.
When the potential of the N-channel MOSFET is determined to be "L", the N-channel MOSFET
Since the (supply current amount control means) 501 is turned off, the DC current path to the current mirror circuit 130 is cut off, and no DC current flows, thereby reducing power consumption.

In the read circuit shown in FIG. 5B, an N-channel MOSFET (supply current amount control means) 5
02 is the drain of the current mirror circuit 130
The sources are connected to the sources of the N-channel MOSFETs 105 and 106, the sources are grounded, and the gates are connected to the second data line 111. Therefore, the read circuit in FIG. 5B can also eliminate the unnecessary flow of the DC current when the potential of the second data line 111 is determined to be “L”, and can reduce the read time and the low power consumption. Can be realized.

(Fourth Embodiment) FIG. 6 shows a main part of a read circuit according to a fourth embodiment of the present invention, and shows a register file read circuit. In addition, the same code | symbol is attached | subjected to the part which shows the structure similar to FIG.

In FIG. 6, reference numeral 600 denotes potential setting means (separating means). The potential setting means 600 includes an N-channel MOSFET 601 and an inverter circuit 602. The inverter circuit 602 logically inverts the precharge signal input to the precharge signal line 112.
The N-channel MOSFET 601 is arranged between the current input terminal IN of the current mirror circuit 130 and a ground line, and receives at its gate the logical inversion signal of the inverter circuit 602 at the time of reception, that is, the second data line 111. During the precharge period of the current mirror circuit 13
The potential of the 0 current input terminal IN is forcibly set to the ground potential.

The reading circuit of the present embodiment solves the following disadvantage. That is, the potential of the current input line IN of the current mirror circuit 130 becomes a potential divided by the resistance components of the P-channel MOSFET 104 and the N-channel MOSFET 105. Therefore, if the width of the gate of the N-channel MOSFET 105 is set small,
The potential of the gate of 106 increases. Further, N channel M
When the gate width of the OSFET 106 is set to be large, a large output current, that is, a large drain current is obtained in the N-channel MOSFET 106, so that the read time can be reduced. However, even when the discharge of the second data line 111 is completed, the potential of the gate of the N-channel MOSFET 106 still exceeds the threshold voltage, and the N-channel MOSFET
The ET 106 keeps on. As a result, the N-channel MO
If the gate width of the SFET 105 is set too small,
Next, when precharging the second data line 111,
The N-channel MOSFET 106 that keeps on is the second
To fix the potential of the data line 111 to “L”, and the precharge circuit 103 and the N-channel MOSF
Since a DC current path is formed between the ET 106 and the ET 106, the time for precharging the potential of the second data line 111 to “H” may be long, or the precharge may not be performed to “H”.

However, in the present embodiment, when the precharge circuit (P-channel MOSFET) 103 is turned on and the second data line 111 is precharged, the N-channel MOSFET 601 is turned on, so that the current mirror is turned on. The potential of the current input terminal IN of the circuit 130, that is, the potential of the gates of the two N-channel MOSFETs 105 and 106 decreases to the ground potential. As a result, the N-channel MOSFET 106 is turned off, and the current output terminal OUT of the current mirror circuit 130 is disconnected from the second data line 111. Therefore, while reducing the read time by setting the gate width of the N-channel MOSFET 105 to be small, at the time of precharging the second data line 111 performed after the read, the second
Of the data line 111 can be stabilized and the precharge time can be shortened.

The potential setting means 6 shown in the present embodiment
The same effect can of course be obtained by applying 00 to the readout circuit shown in FIGS. 4 and 5.

(Fifth Embodiment) FIG. 7 shows a main configuration of a read circuit according to a fifth embodiment of the present invention.
The M read circuit is shown. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In an application such as a ROM, a selector circuit is provided because the width of a read circuit is larger than the width of a memory cell, and one bit line is selected from a plurality of bit lines by the selector circuit. Thus, a method of reading a signal from the selected bit line is adopted. In the present embodiment, the present invention is applied to a read circuit including such a selector circuit.

In FIG. 7, reference numerals 711 and 716 denote bit lines, and reference numeral 700 denotes a ROM memory cell. In the drawing, only the memory cells connected to the bit line 711 are shown. A word line 710 is connected to the memory cell 700,
When the potential of the word line 710 rises, the potential of the corresponding bit line 711 or 716 is lowered to “L” via the memory cell 700 connected to the word line 710. Each of the bit lines 711 and 716 has a load 720 and 721 including a wiring resistance, a wiring capacitance, a drain capacitance of a memory cell, and the like.

The bit lines 711 and 716 are connected to P-channel MOSFETs 703 and 7 as selector circuits, respectively.
08, and is connected to the second data line 111.
The P-channel MOSFETs 703 and 708 are respectively
The gates are connected to column address selection lines 713 and 718, and the potentials of the selection lines 713 and 718 are set to an intermediate potential described later. This P-channel MOSFET 70
3, 708 are the corresponding bit lines 711, 716 and the second
Function as opening control means of the present invention to make the impedance between the data line 111 and the data line 111 close to infinity and equalize the two to an open state.

P-channel MOSFETs 701 and 706
Constitutes a current supply means of the present invention, the gate of which is connected to the corresponding bit line 711, 716, the source of which is connected to the power supply line, and detects when the potential of the corresponding bit line changes, and detects its drain. To supply current.

P-channel MOSFETs 702 and 707
Each have a P-channel MOSFET 70
1, 706, the drain of which is connected to the current input terminal IN of the current mirror circuit 130,
The gate is connected to the other column address selection lines 712, 717.

FIG. 8 shows the column address selection lines 712, 7
13 shows a configuration example of an intermediate potential generation circuit that generates an intermediate potential to be supplied to 13, 717, and 718. In FIG.
Is an input line for the address {an-1 .... a0} and its logically inverted signal {xan-1 .... xa0}, and 801 is the address {an-1 .... a0} from the input line 820. A first decoder circuit comprising a multi-input NAND gate to be inputted, 80
2 is a logical inverted signal of the address {x} from the input line 820
an-1... xa0} are input to the second decoder circuits 803 and 804, each of which is composed of another multi-input NAND gate, and have the same configuration as the intermediate potential generation circuit 300 shown in FIG. It is a first and second intermediate potential generation circuit. The first
Of the first decoder circuit 80
1 to generate an intermediate potential at the time of address selection,
This intermediate potential is output to a column address selection line 713.
The output potential of the first decoder circuit 801 is supplied to a column address selection line 712 via a buffer circuit 805. The second intermediate potential generation circuit 804 receives the output of the second decoder circuit 802 and generates an intermediate potential at the time of address selection. This intermediate potential is output to a column address selection line 718. The output potential of the second decoder circuit 802 is
The signal is supplied to the column address selection line 717 via the buffer circuit 806.

Next, the operation of the read circuit of the ROM of this embodiment will be described. For example, when the bit line 711 is selected, the potential of the column address selection line 712 is “
L ”, the potential of the column address selection line 713 is
Each is set to an intermediate potential so that the OSFET 703 operates in the saturation region. At the same time, the unselected bit lines 71
In order to disable the selector circuit No. 6, the potential of the column address selection line 717 is set to "H" and the potential of the column address selection line 718 is set to "H". Therefore, as the potential of the selected bit line 711 decreases, the P-channel M
The OSFET (electrode supply means) 701 supplies a current, and this current flows to the current input terminal IN of the current mirror circuit 130 via the P-channel MOSFET 702. As a result, the current mirror circuit 130 becomes the second data line 111
When the potential of the sense output line 114 is determined as the charge is discharged, the reading is completed.

In a conventional selector circuit for selecting a column of a ROM, a ground potential is applied to a gate of a MOSFET constituting the column circuit, and the selector circuit operates in a linear region. Therefore, nodes at both ends of the selector circuit are resistors. It becomes equal to the connected state. On the other hand, in the present embodiment, P-channel MOSFETs (selector circuits) 703 and 708
Is operated in a saturation region when an intermediate potential is applied to its gate, so that the selected bit line (first data line) 7
11 or 716 and the second data line 111 are disconnected. As a result, the load capacitance seen from the N-channel MOSFET 106 of the current mirror circuit 130 is equal to the selected bit line (first data line) 711 or 716.
Therefore, reading is performed in a short time and the reading speed is increased.

Further, in the present embodiment, the P channel M
Since the OSFETs 703 and 708 have both the function as the selector circuit and the function as the opening control means of the present invention, the circuit scale can be made smaller and the area can be reduced as compared with a circuit configuration having a separate selector circuit.

Note that, as shown in this embodiment, the configuration shown in FIGS. 4, 5 and 6 is added to the read circuit for selecting one data line from a plurality of data lines. Of course, it may be possible.

(Sixth Embodiment) FIG. 11 shows a main configuration of a read circuit of a RAM according to a sixth embodiment of the present invention.

In FIG. 11, reference numerals 1101 and 1102 denote memory cell arrays for one column of the RAM, 1132 and 1112, respectively.
33 is a bit line arranged in the memory cell array 1101, and 1182 and 1183 are bit lines arranged in the other memory cell array 1102. Hereinafter, the memory cell arrays 1101 and 1102 have the same configuration.
Only one configuration will be described. 1103 is a memory cell connected to a pair of bit lines, 1130 is a word line WL, and a large number (two in the figure) of the memory cells 1103 are connected to the word line WL (1130) in the column direction. .
Although not shown, a large number of memory cells 1103 are connected to each pair of bit lines in the row direction. The pair of bit lines (1132, 1133), (1182, 118)
3) through the bit line pair consisting of 3)
, Or write data to the memory cell 1103. A precharge circuit 1104 precharges and equalizes each bit line to a predetermined potential according to the potential of a precharge enable line (PRC) 1131.

Reference numerals 1135 and 1136 denote data lines, and the bit line pairs are connected to a pair of data lines composed of the two data lines. The data line 1135 is a read line for one bit of data.

Reference numeral 1107 denotes a latch type sense circuit.
The two data lines 1135 and 1136 are connected.
This sense circuit 1107 includes a P-channel MOSFET 1
108 and an N-channel MOSFET 1110 connected in series, a first inverter circuit 1190, another P-channel MOSFET 1109 and an N-channel MOSFET 1110.
And a second inverter circuit 11 connected in series with
91. An input terminal in1 of the first inverter circuit 1190 and an output terminal out2 of the second inverter circuit 1191 are connected by a first input line 1107a,
This input line 1107a is connected to data line 1136. Also, the output terminal o of the first inverter circuit 1190
ut1 and the input terminal in of the second inverter circuit 1191
2 are connected by a second input line 1107b, and the input line 1107b is connected to the data line 1135. The sense circuit 1107 has an N-channel MOSFET 1112 for current control,
1112 is a sense enable line (SEN) 1137
Is "H", the sensing circuit 1107 starts the sensing operation.

Reference numeral 1113 denotes a buffer circuit for writing data to the memory cell 1103. When the write enable line (WEN) 1139 is at "H", the input line 1113
38 data are written to the memory cell 1103 via a pair of data lines 1135 and 1136 and a predetermined pair of bit lines (for example, 1132 and 1133).

Reference numeral 1105 denotes a memory cell array 11 of each column.
A selector circuit (control transistor) for selecting any one of the bit line pairs 01, 1102. The selector circuit 1105 has four CMOS type transfer gates 1170, 1171, 1172, 1173.
33, 1182, 1183, respectively,
A set of P-channel and N-channel MOSFETs (114
1,1142), (1143, 1144), (114
5, 1146) and (1147, 1148), and the two MOSFETs constituting each group have their sources and drains connected to each other.

In the selector circuit 1105, two CMs connected to a pair of bit lines 1132 and 1133
In the OS transfer gates 1170 and 1171, the selector signal line CSL (1160) is connected to the gate (control electrode) of each of the N-channel MOSFETs 1142 and 1144, and the P-channel MOSFETs 1141 and 1143 are connected.
The other selector signal line XCSL to the gate (control electrode) of
(1161) is connected. Further, in the two CMOS transfer gates 1172 and 1173 connected to the other pair of bit lines 1182 and 1183, the gates (control electrodes) of the respective N-channel MOSFETs 1146 and 1148
Is connected to the selector signal line CSR (1162).
Another selector signal line XCSR (1163) is connected to the gates (control electrodes) of the channel MOSFETs 1145 and 1147.

A circuit for setting the potentials of the selector signal lines CSL and CSR and the other selector signal lines XCSL and XCSR will be described. This circuit includes a column address input line ADR
(1134) buffer circuit 1150.

Next, the buffer circuit (potential control means)
The internal configuration of 1150 will be described. This buffer circuit 11
50 has an address input line A and a write control signal input line W, and the output line NOUT is connected to the selector selection signal CSL116.
0, the output line POUT is connected to the selector signal line XCSL116.
1 respectively.

The output line NOUT includes a P-channel MOSFET 1152 for pull-up, an N-channel MOSFET 1153 for pull-up, and an N-channel M for pull-down.
OSFET 1154 is connected. Address input line 1
When the potential of H is 134 and the write operation is performed (WEN is "H"), the pull-up P
When the channel MOSFET 1152 is turned on, the output line N
The potential of OUT is set to the power supply potential VDD. When the potential of the address input line 1134 is “H” and a read operation is performed (when WEN is “L”), the N-channel MOSFET 1153 for pull-up is turned on, and the output line NOU is turned on.
The potential of T, that is, the potential of the selector signal line CSL1160 is set higher than the power supply voltage VDD by the N-channel MOSFET 11
An intermediate potential (VDD-
Vtn). Here, the power supply voltage VDD
Is 3.3 V and the threshold voltage Vtn of the N-channel MOSFET 1153 is 0.7 V.
Since tn increases to about 1.0 V due to the substrate bias effect, the potential of the selector signal line CSL1160 becomes an intermediate potential of about 2.3 V. When the address input line 1134 is “L”, the N-channel MOSFET 1154 for pull-down is turned on, and the output line NOUT
Is the ground potential VSS.

Further, in the buffer circuit 1150, a pull-up P-channel M is connected to the output line POUT.
OSFET 1156, N-channel MOS for pull-down
FET 1157, N-channel MOSFE for pull-up
T1155 is connected. When the potential of the address input line 1134 is “H” and a write operation is performed (WEN
Is "H"), the N-channel MO for pull-down
The SFET 1157 is turned on to set the output line POUT to the ground potential VSS. The potential of the address input line 1134 is "
When the read operation is performed at “H” (WEN is “L”), the N-channel MOSFET 1 for pull-up is used.
155 is turned on, and the potential of the output line POUT, that is, the potential of the selector signal line XCSL1161 is set to the intermediate potential (VDD-Vtn = 2.3 V) as described above. When the address input line 1134 is “L”, the pull-up P-channel MOSFET 1156 is turned on to set the power supply potential VDD.

The buffer circuit 1150 is provided with a P-channel MOSFET 1158 (equalizing means). This P-channel MOSFET 1158 is used to quickly pull down the selector signal line set to the power supply voltage VDD to a predetermined intermediate potential when reading data from the memory cell array in the same column immediately after writing. For example, assuming that the selector signal line CSL1160 is set to the power supply potential VDD at the time of writing and data is read immediately after that, the power supply voltage VSL
DD and the selector signal line XCS set to the ground potential VSS.
L1161 is equalized by a P-channel MOSFET 1158 to set the selector signal line CSL1160 to an intermediate potential. This P-channel MOSFET 115
A state transition detection circuit 1155 is provided in order to apply a control voltage to the gates 8. Write enable line (WE
N) 1139 changes from “H” to “L”, the state transition detection circuit 1155 generates a pulse voltage, and the selector signal lines CSL1160 and XCSVL only during the generation period.
1161 is equalized. After that, N channel MOS
The FET 1155 pulls up to the intermediate potential (VDD-Vtn).

Reference numeral 1151 denotes a buffer circuit having the same configuration as the buffer circuit 1150. When the column address signal ADR is "L", this circuit selects the selector signal lines CSR1162 and XCSR according to the write or read operation.
It operates to set the potential of 1163.

Next, the read operation of the RAM according to the present embodiment will be described with reference to the operation timing chart shown in FIG. This description will be made based on the ON condition expression of the MOSFET of the expression 2 and the saturation operation condition expression of the expression 3 described in the first embodiment. In FIG. 12, the potential waveforms corresponding to the signal line numbers of the read circuit shown in FIG. 11 are denoted by the same reference numerals as those of the signal lines. For comparison, the potential waveform of the conventional example shown in FIG. 14 is also shown.

The potential of the bit line 1133 is Vb, and the potential of the data line 1136 output from the selector circuit 1105 is Vb.
a, the potential of the selector signal XCSL1161 (that is, the gate potential of the P-channel MOSFET 1143) is Vgp,
The threshold voltage of P-channel MOSFET 1143 is Vt
Let p. The potential Vb of the bit line 1133 and the data line 11
Since the potential Va of 36 changes with the reading of data, the timing of satisfying Expressions 2 and 3 changes according to these potential changes.

The column address input line 1134 is set at "H", the bit lines 1132 and 1133 of the column 1101 are selected by the selector circuit 1105, and the memory cell 1
It is assumed that data of logic “1” is stored in 103. Since the potential of the bit line 1132 is set in advance to the precharge potential and there is no discharge from the memory cell 1103, the potential does not change.

At the beginning of data reading, when word line 1130 changes to "H" at time t1, bit line 1133
Is discharged to “L” by the memory cell 1103, and the bit line 1132 outputs “H”.

At this time, the P-channel MOSFET 114
The gate-source voltage of No. 3 is expressed by Expression 12, and the source-drain voltage is expressed by Expression 13.

Vgs = Va−Vgp (Equation 12) Vds = Va−Vb (Equation 13) By substituting these two equations into Equations 2 and 3 of the first embodiment, the following can be simplified. P-channel MOSFET11
The ON condition expression of 43 is represented by Expression 14, and the saturation operation condition expression is represented by Expression 15.

Vgp ≦ Va−Vtp (Equation 14) Vgp ≧ Vb−Vtp (Equation 15) Here, as in the first embodiment, actual numerical examples will be described. Also in the present embodiment, the power supply voltage VDD is set to 3.
3V, the threshold voltage Vtp of the P-channel MOSFET 1143 is set to 0.7V. Selector signal line XCSL11
The potential of 61, that is, the potential Vgp of the gate of the P-channel MOSFET 1143 is 2.3 V as described above. Therefore, although the ON condition expression 14 is satisfied, the saturation operation condition expression 15
Is not satisfied, and the P-channel MOSFET 1143 operates in the linear region.

On the other hand, N-channel MOSFET 1144 operates as follows. That is, the selector signal CSL116
Assuming that the potential of 0, that is, the gate potential of the N-channel MOSFET 1144 is Vgn and its threshold voltage is Vtn,
The gate-source voltage of the N-channel MOSFET 1144 is expressed by Expression 16, and the source-drain voltage is expressed by Expression 17.

Vgs = Vgn-Va (Equation 16) Vds = Vb-Va (Equation 17) Here, the bit line 11
It is assumed that only the potential Vb of 33 is higher than the data line Va. Substituting these two equations into Equations 2 and 3 and simplifying them, Equation 18 is the ON condition equation of the N-channel MOSFET 1144 and Equation 19 is the saturation operation condition equation.

Vgn ≧ Va + Vtn (Equation 18) Vgn ≦ Vb + Vtn (Equation 19) In this embodiment, the threshold voltage Vtn of the N-channel MOSFET 1144 is set to 0.7V. N-channel MO
The gate potential Vgn of the SFET 1144 is 2.
3V. Therefore, the above-mentioned saturation operation condition expression 19 is satisfied, but the ON condition expression 18 is not satisfied.
ET1144 is off.

Next, when the potential Vb of the bit line 1133 drops and reaches 3.0 V, the saturation operation condition expression 15 is satisfied, the P-channel MOSFET 1143 starts operating in a saturation region, and the bit line 1133 and the data line The impedance between the signal lines 1136 approaches infinity, and the distance between both signal lines becomes equal to the open state.

On the other hand, at time t2, two bit lines 113
When the potential difference ΔVb1 between the 2 and 1133 reaches a predetermined potential,
The potential of the sense enable line 1137 becomes “H”. The sense circuit 1107 operates as a latch circuit and is in an equilibrium state when the potentials of the two data lines 1135 and 1136 are equal.
When the potential difference ΔVb1 is generated between the potentials 133 and 133, the potential difference ΔVb1 is operated to amplify the potential difference ΔVb1 so that the potential of the “H” side data line 1135 is reduced to the power supply voltage VDD and the potential of the “L” side data line 1136 is increased. To the ground potential VSS. As described above, the P-channel MOSFET 1143 operates in a saturation region, and the bit line 1133 and the data line 11
36 is equal to the open state, and the data line 1136 is
Large load (wiring capacitance, wiring resistance and memory cell 110
Bit line 1 having a load equal to the sum of the drain capacitances and the like of FIG.
133 is in a separated state. As a result, FIG.
As shown in the waveform of FIG.
3 is almost the N-channel MOSF of the memory cell 1103.
Only the ET is discharged, and the conventional example of FIG.
33, the potential of the latch type sense circuit 1107 discharges only the data line 1136 having a small load capacitance, and the data line 11
The steep drop in the potential at 36 causes a significant change in the potential as compared with the conventional example of FIG. 14 (the potential change indicated by the broken line of the bit line 1436), and data reading can be performed at a higher speed.

Thereafter, as the discharge of data line 1136 progresses, potential Va of data line 1136 changes to bit line 11.
33, the gate-source voltage of the P-channel MOSFET 1143 at this time becomes:
0, the source-drain voltage is given by equation 21.

Vgs = Vb−Vgp (Equation 20) Vds = Vb−Va (Equation 21) By substituting these two equations into the above Equations 2 and 3, the ON condition of the P-channel MOSFET 1143 becomes In Expression 22, the saturation operation condition expression is Expression 23.

Vgp ≦ Vb−Vtp (Equation 22) Vgp ≧ Va−Vtp (Equation 23) At this time, since the above-mentioned on-condition expression 18 is not satisfied,
P-channel MOSFET 1143 turns off.

On the other hand, N-channel MOSFET 1144
When the potential Va of the data line 1136 is further reduced by discharge and becomes lower than 1.6 V, the ON condition expression 18 is satisfied and the device operates in a saturation region. Therefore, the impedance between the bit line 1133 and the data line 1136 is close to infinity, and these signal lines become equal to the open state, so that the electric charge of the data line 1136 is separated from the bit line 1133, Discharged through the sense circuit 1107.

At time t0, the potential of the data line 1136 becomes lower than the logic threshold value of a circuit (not shown) at the subsequent stage.
The read data is determined.

Thereafter, when the potential Vb of the bit line 1133 drops to 1.6 V or less due to the discharge of the memory cell 1103, the N-channel MOSFET 1144 does not satisfy the saturation operation condition expression 19 and operates in a linear region where the impedance is small. However, there is no problem since the potential Va of the data line 1136 is determined and the reading is completed.

Therefore, in most of the read operation,
Since the impedance between the data line 1136 and the bit line 1133 can be made close to infinity and the load capacitance driven by the sense circuit 1107 can be reduced to only the capacitance of the data line 1136, the read time can be shortened.

On the other hand, during the write operation, the P channel M
The gate potential of the OSFET 1143 is set to the selector signal line XC
SL1161 sets the ground potential Vss, and the gate potential of N-channel MOSFET 1144 changes the selector signal line C
The power supply potential VDD is set by SL1160. Therefore, the P-channel MOSFET 1143 and the N-channel M
The gate-source voltage of the OSFET 1144 is maximized, and its on-resistance is minimized. as a result,
The data write time is shortened, and a high-speed write operation is realized.

The potentials of the word line 1130, the precharge enable line 1131 and the sense enable line 1137 are
The clocks operate at almost the same clock timing. Therefore, when the word line 1130 becomes “L”, the precharge enable line 1131 and the sense enable line 1137
Also, the bit lines 1132 and 1133 and the data lines 1135 and 1136 are cut off from the sense circuit 1107, and precharge and equalization are performed.

(Seventh Embodiment) FIG. 13 shows a main configuration of a read circuit of a RAM according to a seventh embodiment of the present invention. The same components as those in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment is a partial improvement of the sixth embodiment. That is, the selector circuit 1105
, Four N-channel MOSFETs 1142, 1
As described in the sixth embodiment, 144, 1146, and 1148 are turned off from the beginning of the read operation, and operate in the saturation region by satisfying Expressions 18 and 19 at a predetermined time in the latter half. At the beginning, these four N-channel MOSFETs are always turned off during the read operation.

In FIG. 13, reference numeral 1250 denotes a column address input line buffer circuit (potential control means) having an address input line A and a write control signal input line W, and an output line NOUT having a selector selection signal CSL 1260 and an output line. P
OUT is connected to each of the selector signal lines XCSL1261. When the potential of the address input line 1134 is “H” and the write operation is performed (WEN is “
H ”), a pull-up P-channel MOSF
When the ET1251 is turned on, the power supply potential becomes VDD,
When the potential of the address input line 1134 is “H” and a read operation is performed (WEN is “L”), and when the address input line 1134 is “L”, the ON operation of the pull-down N-channel MOSFET 1252 is performed. To the ground potential VSS. The buffer circuit 1150 of FIG.
N-channel MOSFET 11 for generating intermediate potential
53 is not provided. The configuration for setting the potential of the output line POUT is the same as the configuration of the buffer circuit 1150 shown in FIG. 1251 is the buffer circuit 12
50 is a circuit having the same configuration as 50.

Therefore, in this embodiment, for example, at the time of the read operation in which the bit lines 1132 and 1133 are selected,
Two N-channel MSOFETs of selector circuit 1105
Although both 1142 and 1144 are always off,
Since the two P-channel MSOFETs 1141 and 1143 operate in the saturation region, the gap between the bit lines 1132 and 1133 and the data lines 1135 and 1136 is equal to an open state, and as a result, the latch type sense circuit 1107 has a small load capacitance. Since only the data lines 1135 and 1136 are discharged, the reading speed can be increased, and the N-channel MOSFET for generating the intermediate potential shown in FIG.
Since the 1153 is not provided, an effect that the configuration of the buffer circuit 1250 can be simplified is obtained. During a write operation, the sixth
The MOSF of the selector circuit 1105 is similar to the embodiment of FIG.
Since the ET operates in the linear region, data can be transmitted to the memory cell with low impedance, and a high-speed write operation is ensured.

In the above description, a MOSFET is used as a transistor. However, it goes without saying that a bipolar transistor, a GaAs MESFET, or the like may be used because of the similarity in operation.

[0145]

As described above, according to the first to eleventh aspects of the present invention, at the time of reading data, the first data line having a large load capacitance and the second data line having a small load capacitance are connected to each other. The impedance between the two lines is close to infinity and equal to the open state, so that only the charge of the second data line having a small capacity can be discharged, and the discharge can be performed in a short time, thereby speeding up data reading. it can.

In particular, according to the second to seventh aspects of the present invention, since the current supply path from the current supply means to the current mirror circuit is cut off after reading data, useless DC current flowing through the current mirror circuit is reduced. Can be reduced.

Further, according to the eighth aspect of the present invention, the second
Since the current mirror circuit is cut off from the second data line when precharging the data line of
And the precharge time can be reduced.

According to the twelfth to seventeenth aspects of the present invention, at the time of data reading, the impedance between the bit line and the data line is made close to infinity to be equal to the open state. Since the charge discharged by the sense circuit is limited to only the charge of the data line, the data line can be discharged in a short time and the speed of data reading can be increased. On the other hand, when writing data, since the data is transmitted to the memory cells with low impedance, a high writing speed can be secured.

[Brief description of the drawings]

FIG. 1 is a diagram showing a main configuration of a register file reading circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart of an operation of a register file reading circuit according to the first embodiment;

FIG. 3 is a diagram illustrating a configuration of an intermediate potential generation circuit in a register file read circuit according to the first embodiment;

FIG. 4 is a diagram showing a main configuration of a register file reading circuit according to a second embodiment of the present invention;

FIG. 5 is a diagram showing a main configuration of a register file reading circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram illustrating a main configuration of a register file reading circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a main configuration of a read circuit of a ROM according to a fifth embodiment of the present invention.

FIG. 8 is a diagram illustrating a main configuration of a decoder circuit in a read circuit of a ROM according to a fifth embodiment;

FIG. 9 is a diagram showing a configuration of a conventional register file reading circuit.

FIG. 10 is a diagram showing a configuration of another conventional register file reading circuit.

FIG. 11 is a diagram illustrating a main configuration of a read circuit of a RAM according to a sixth embodiment of the present invention.

FIG. 12 is a diagram showing a timing chart of the operation of the read circuit of the RAM according to the sixth embodiment;

FIG. 13 is a diagram illustrating a main configuration of a read circuit of a RAM according to a seventh embodiment of the present invention;

FIG. 14 is a diagram showing a main configuration of a conventional read circuit of a RAM.

FIG. 15 is a diagram showing a timing chart of the operation of a conventional RAM read circuit.

[Explanation of symbols]

101 memory cell 104 P-channel MOSFET (current supply means) 105 N-channel MOSFET (first
Transistor) 106 N-channel MOSFET (second
107 P-channel MOSFET (control transistor) 108 Inverter circuit 110 First data line 111 Second data line 114 Sense output line (output line) 130 Current mirror circuit IN Current input terminal OUT Current output terminal 300 Intermediate potential generation Circuits (opening control means) 401, 402 P-channel MOSFETs (supply current amount control means) 501, 502 N-channel MOSFETs (supply current amount control means) 600 Potential setting means (isolation means) 700 Memory cells 711, 716 1 data line) 701, 706 P-channel MOSFET (current supply means) 703, 708 P-channel MOSFET (transistor) 803, 804 Intermediate potential setting circuit 1103 Memory cell 1104 Precharge circuit 1105 cell Lector circuit (potential control means) 1107 Latch type sense circuit in1, in2 Input terminal out1, out2 Output terminal 1107a First input line 1107b Second input line 1160 First inverter circuit 1162 Second inverter circuit 1132, 1133 bits Line 1135, 1136 Data line 1141, 1143 1145, 1147 P-channel MOSFET 1142, 1144 1146, 1148 N-channel MOSFET 1158 P-channel MOSFET (equalizing means) 1170, 1171, 1172, 1173 CMOS transfer gate CSL, CSR Selector signal line XCSL , XCSR Other selector signal lines

Claims (18)

(57) [Claims] 1. A data read circuit in a semiconductor memory device comprising a dynamic circuit which is precharged to a predetermined potential during a precharge period and has a first data line connected to a plurality of memory cells, wherein: A second data line that is precharged to a predetermined potential during a charging period; and a second data line that is connected to the first data line, detects a potential change in the first data line, and supplies a current when the potential change is detected. Current supply means, a current input terminal for inputting a supply current of the current supply means,
And a current output terminal connected to the second data line, wherein a current is supplied from the current output terminal to ground using the supply current of the current supply means input to the current input terminal as a reference current. A current mirror circuit for discharging the electric charge of the second data line; a control transistor for connecting the first data line and the second data line; Open control means for setting the potential of the control electrode of the transistor to an intermediate potential at which the control transistor operates in a saturation region, and equalizing the open state between the first data line and the second data line; A data reading circuit in a semiconductor memory device, comprising: 2. An inverter circuit having an input side connected to a second data line and having an output line for outputting a potential obtained by logically inverting the potential of the second data line, and an output line of the inverter circuit. 2. A data read operation in a semiconductor memory device according to claim 1, further comprising a supply current amount control means for limiting a current amount supplied from the current supply means to a small value after the change of the potential of the output line. circuit. 3. The supply current control means comprises a P-channel MOSFET arranged between the current supply means and a current input terminal of a current mirror circuit, and an output line of an inverter circuit is provided at a gate of the P-channel MOSFET. 3. The data read circuit according to claim 2, wherein the data read circuit is connected. 4. The supply current control means comprises a P-channel MOSFET arranged between a current mirror circuit and a ground, and an output line of an inverter circuit is connected to a gate of the P-channel MOSFET. 3. A data read circuit in a semiconductor memory device according to claim 2, wherein 5. A supply current amount control means connected to a second data line and for limiting the amount of current supplied from the current supply means to a small amount after the end of the change of the potential of the second data line. 2. A data read circuit in a semiconductor memory device according to claim 1, wherein: 6. The supply current amount control means comprises an N-channel MOSFET arranged between the current supply means and a current input terminal of the current mirror circuit, and a gate of the N-channel MOSFET has a second data line connected thereto. 6. The data read circuit according to claim 5, wherein the data read circuit is connected. 7. The supply current control means comprises an N-channel MOSFET arranged between a current mirror circuit and ground, and a gate of the N-channel MOSFET is connected to a second data line. 6. A data read circuit in a semiconductor memory device according to claim 5, wherein 8. When the second data line is precharged, the potential of the current input terminal of the current mirror circuit is forcibly set to the ground potential, and the current output terminal of the second data line and the current mirror circuit are set. 2. A data read circuit in a semiconductor memory device according to claim 1, further comprising a disconnecting means for disconnecting the data from the data. 9. A current mirror circuit is arranged between a current input terminal and a ground line, and a first transistor whose control electrode is connected to the current input terminal; and a current transistor between the current output terminal and the ground line. 4. The device according to claim 1, wherein the control electrode is configured by a second transistor connected to the current input terminal.
9. A data reading circuit in the semiconductor memory device according to 5, 6, 7, or 8. 10. The data read circuit according to claim 9, wherein the first and second transistors are both N-channel MOSFETs. 11. The current supply means is a P-channel MOSFE.
The P-channel MOSFET has a gate connected to a first data line, a source connected to a power supply line, and a current flowing from a drain serving as a supply current of a current supply unit. Claims 1, 2, 3, 4, 5, 6,
11. A data reading circuit in the semiconductor memory device according to 7, 8, 9, or 10. 12. A bit line pair consisting of two bit lines connected to a memory cell, a data line pair consisting of two data lines, connected to the bit line pair, and connected to the data line pair. A latch-type sense circuit for reading data stored in the memory cell from the bit line pair to the data line pair, and when writing data, the data is transmitted from the data line pair to the memory cell via the bit line pair. In a data read circuit in a semiconductor memory device capable of writing data, the data read circuit is arranged between the bit line pair and the data line pair.
Control transistors, and potential control means connected to the control electrodes of the control transistors and controlling the potential of the control electrodes, wherein the potential control means performs a data read when the latch-type sense circuit operates. The potential of the control electrode of each control transistor is set to an intermediate potential that is lower than the power supply voltage and higher than the ground potential, so that each control transistor operates in a saturation region. A data reading circuit in a semiconductor memory device, wherein a potential of a control electrode is set to operate in a region. 13. A latch type sense circuit comprising: first and second inverter circuits each having an input terminal and an output terminal; and an input terminal of the first inverter circuit and an output terminal of the second inverter circuit. And a second input line connecting an output terminal of the first inverter circuit and an input terminal of the second inverter circuit, wherein the first and second inputs are connected to each other. 13. The data read circuit in a semiconductor memory device according to claim 12, wherein an input line pair formed of a line is connected to a data line pair. 14. A selector circuit provided corresponding to a plurality of bit line pairs and comprising a transistor disposed between the corresponding plurality of bit line pairs and the data line pair. One bit line pair is selected from the corresponding plurality of bit line pairs by operation to read and write data, and a control transistor is constituted by a CMOS transfer gate forming each selector circuit. 13. A data read circuit in a semiconductor memory device according to claim 12, wherein: 15. The number of selector circuits provided is equal to the number of bit lines constituting a plurality of corresponding bit line pairs, and the number of CMOs connected to the corresponding bit lines is equal.
15. The semiconductor according to claim 14, comprising an S-type transfer gate, wherein each of the CMOS-type transfer gates includes a P-channel MOSFET and an N-channel MOSFET, and each source and drain of both MOSFETs are connected. A data reading circuit in a storage device. 16. A potential control means, in a read operation for selecting a predetermined pair of bit lines, among the CMOS type transfer gates constituting the selector circuit, the potential control means controls the predetermined pair of bit lines to be selected. The gate potentials of the two P-channel MOSFETs and the two N-channel MOSFETs forming the two connected CMOS transfer gates are set to intermediate potentials lower than the power supply potential and higher than the ground potential. On the other hand, during a write operation for selecting a predetermined pair of bit lines, two CMOS transfer gates connected to the predetermined pair of bit lines to be selected are operated. The potential of each gate of the two P-channel MOSFETs is set to the ground potential, and the CMOS transfer gate Set each gate potential of the two N-channel MOSFET constituting the door to the supply potential, four MO of this such
16. The data reading circuit according to claim 15, wherein the SFET operates in a linear region. 17. A potential control means, in a read operation for selecting a predetermined pair of bit lines, among the CMOS type transfer gates constituting the selector circuit, the potential control means applies the predetermined pair of bit lines to be selected. The potential of each of the two P-channel MOSFETs forming the two connected CMOS transfer gates is set to an intermediate potential lower than the power supply potential and higher than the ground potential, and the two P-channel MOSFETs are saturated. In addition to operating in the region, the potential of each gate of the two N-channel MOSFETs constituting the CMOS transfer gate is set to the ground potential to turn off these two N-channel MOSFETs. During a write operation for selecting a bit line, two Cs connected to a predetermined pair of bit lines to be selected are selected. The potential of each gate of the two P-channel MOSFETs forming the OS transfer gate is set to the ground potential, and the potential of each gate of the two N-channel MOSFETs forming the CMOS transfer gate is set to the power supply potential. And these four MOS
16. The data reading circuit according to claim 15, wherein the FET operates in a linear region. 18. Two CMOs connected to a bit line pair
In the S-type transfer gate, two P-channel MOs forming both CMOS type transfer gates
The gates of the SFETs are commonly connected to a selector signal line, and constitute two CMOS type transfer gates.
The gates of the N-channel MOSFETs are commonly connected to another selector signal line, and the potential control means performs a data read operation via the bit line pair immediately after a data write operation via the bit line pair. 17. The data read circuit in a semiconductor memory device according to claim 16, further comprising: equalizing means for equalizing said selector signal line and said another selector signal line.