JP2862151B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller for automatically controlling electronic equipment, and more particularly, to a programmable controller capable of expanding electronic equipment to be controlled.

[0002]

2. Description of the Related Art Conventional programmable controllers are:
As shown in FIG. 4, the CPU mainly comprises a CPU module 1 and an optional input / output module 7.

An optional input / output module 7 is provided between a device to be controlled and a CPU module, and mutually converts an input / output signal for the device to be controlled and an input / output signal for the CPU module into a signal corresponding to each transmission mode. . The optional input / output module can be detachably connected to the CPU module 1 via the bus interface 8.

The CPU 2 in the CPU module 1 sequentially reads the input signals from the controlled device stored in the link memory 5 at the previous scan time, and executes a sequence operation. Further, the result of the sequence operation is written to the link memory 5 as an output signal to the control target device (section T2 in FIG. 5).

After the completion of the sequence calculation, the CPU 2 in the CPU module 1 reads out the output signal of the link memory 5 and transfers it to the common memory 11 of the optional input / output module 7 and the input signal used for the next sequence calculation from the common memory 11. Is transferred to the link memory 5 in the CPU module 1 (section T2 in FIG. 5).

[0006]

In the conventional programmable controller, sequence operation processing and input / output processing with the optional input / output module 7 in the CPU module 1 are collectively performed for each of a plurality of input / output signals. , A link memory 5 is provided. However, the number of connectable optional input / output modules 7 is limited by the memory capacity of the link memory 5. Also, the optional input / output module 7 and CP
The conventional device has a problem that the operation cycle time (scan time) becomes longer because two data transfer processes of external data transfer to and from the U module 1 and internal data transfer in the CPU module 1 occur. .

In view of the above, an object of the present invention is to provide a programmable controller capable of shortening an operation cycle time and connecting a large number of optional input / output modules to a CPU module. is there.

[0008]

In order to achieve the above object, the present invention relates to a programmable controller having one or more input / output modules detachable from a programmable controller main body. Are provided with storage means for storing an input signal to be subjected to a sequence operation in the programmable controller body and an output signal obtained as a result of the sequence operation, and the programmable controller body defines the sequence operation. Storage control means for directly reading / writing the input signal and the output signal by designating an address to the storage means by a sequence instruction in the sequence program.

[0009]

According to the present invention, the input / output signals used for the sequence operation are read out from the storage means of the input / output module directly by the sequence instruction when the sequence operation is executed.
It is not necessary to provide a temporary storage memory for input / output signals in the main body of the programmable controller unlike the related art.

The input / output signal transfer process in the main body of the programmable controller only needs to be performed once compared with the conventional two processes, which can contribute to a reduction in scan time.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of a programmable controller according to an embodiment of the present invention.

The same parts as those in the conventional example shown in FIG. 4 are denoted by the same reference numerals, and detailed description will be omitted.

In FIG. 1, the CPU 2 in a CPU 21 module (the main body of the programmable controller of the present invention)
2 executes a sequence calculation process by executing a sequence program stored in the user program memory 3. The user data memory 24 temporarily stores various data for this sequence operation. The user data memory 24 is not provided with a link memory area for input / output signals.

The common memory 21 (storage means of the present invention) on the option input / output module 27 functions as a link memory on the CPU 21 module side, and is read / written by the CPU 22 on the CPU module 21 side and the CPU 10 on the option input / output module 27 side. Writable.

The CPU 10 reads / writes from / to the common memory 21 when it is time to transfer an input / output signal to the device to be controlled via the external interface 29.

In this embodiment, when the CPU 22 designates an address for the bus interface 8 as the storage control means of the present invention, the bus interface 8 connects the common memory 21 and the CPU 22 by bus, and Access to

Hereinafter, the sequence operation of the CPU module 21 will be described with reference to the flowchart of FIG.

At the execution timing of the sequence program (timing TT1 in FIG. 2), the CPU 22 initializes the internal program counter to the start address of the user program memory 3, and then reads the sequence instruction at the start position from the user program memory 3. (Step S10 → S20 in FIG. 3).

The CPU 22 determines the memory from which the operation data is read / written based on the identification code of the operation data in the sequence instruction (steps S30 and S10 in FIG. 3).
0), data is read / written for sequence operation by specifying an address for the corresponding memory.

The present embodiment differs from the prior art in that reading / writing is performed directly to the common memory 21 of the optional input / output module 27 during sequence operation. For this reason, the link memory on the CPU module side, which is required in the conventional example, becomes unnecessary.

On the other hand, if the read sequence instruction is an instruction instructing an operation other than reading / writing from the memory, other processing is executed as usual (steps S30 → S in FIG. 3).
100 → S110).

Hereinafter, the program counter is updated every time such an operation according to the type of the sequence instruction is executed, and the above-described processing is repeatedly executed up to the program processing portion (the loop of steps S20 to S300 → S310 in FIG. 3). processing).

[0024]

As described above, according to the present invention, the storage means for input / output signals is provided on each input / output module side, so that the storage means for input / output signals is not required on the main body of the programmable controller. Becomes For this reason, conventionally, the memory capacity of the storage means is also variable in accordance with the number of input / output modules installed. An effect that commonality can be obtained is also obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the operation content of the embodiment of the present invention.

FIG. 3 is a flowchart showing an operation procedure of the embodiment of the present invention.

FIG. 4 is a block diagram showing a circuit configuration of a conventional example.

FIG. 5 is an explanatory diagram showing an operation content of a conventional example.

[Explanation of symbols]

 1,21 CPU module 2,22 CPU 4,24 User data memory 5 Link memory 7,27 Optional input / output module 11,21 Common memory

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G05B 19/05

Claims (1)

(57) [Claims] 1. A programmable controller having one or more input / output modules detachable from a programmable controller main body, wherein each of the input / output modules includes an input signal to be subjected to a sequence operation in the programmable controller main body. A storage unit for storing an output signal obtained as a result of the sequence operation is provided. The programmable controller main body stores an address in the storage unit by a sequence instruction in a sequence program that defines the sequence operation. Designation
And a storage controller for directly reading / writing the input signal and the output signal.