JP2859880B2 - Variable gain amplifier circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier circuit, and is particularly suitable for an AGC circuit which obtains an output signal having a constant amplitude with respect to a wide range of changes in the amplitude of an input signal. Variable gain amplifier circuit.

[Conventional technology]

In wireless devices, an AGC (Automatic Gain Control) circuit is used to stabilize a change in signal amplitude caused by the strength of incoming radio waves. In an imaging apparatus, an AGC circuit that compensates for a lack of subject illuminance by increasing a circuit gain and obtains a constant video signal amplitude is often used. An important factor in constructing these AGC functions is a variable gain increasing circuit having a wide gain variable width and operating without distortion with respect to a wide range of change in an input signal. An example is disclosed in FIG. 10 of Utility Model Publication No. 62-28409.

[Problems to be solved by the invention]

In this known example, an input signal is applied to a T1 terminal, gain is controlled by a control voltage applied to a T2 terminal, and an output signal is obtained at a T3 terminal. The gain variable width is R22 / R31 to R22 (1 / R3
1 + 1 / R30). In addition, in order to operate this circuit without distortion up to the maximum input voltage (± Vm), it is necessary to set the bias currents previously supplied to R27 and R28 to values larger than Vm / R30 and Vm / R31, respectively. .

From the above, in order to obtain a wide gain variable width, the value of R30 must be reduced.
(And R26) bias current. However, if the bias current is increased, the voltage drop of R22 increases, and the desired gain cannot be obtained or the power supply voltage must be increased. The increase in the bias current is proportional to the increase in the transistors Q21 and Q22 (Q2
4 and Q25) increase the transconductance of the differential amplifier type current divider, increase the amplification of this transistor against internal noise, and degrade S / N.

As described above, in the known example, it is difficult to obtain a wide gain variable width while maintaining the maximum allowable input voltage at a required value. In other words, an AG that seeks to obtain a constant output signal amplitude by compensating for a decrease in the input signal amplitude by increasing the gain
When this is used for the C circuit, the range of the input signal amplitude at which the AGC operation functions cannot be widened.

Accordingly, an object of the present invention is to provide a variable gain amplifier circuit that can cope with a wide range of changes in the amplitude of an input signal and has a wide variable gain range. Still another object is to provide a variable gain amplifier circuit in which generation of excessive noise is suppressed.

[Means for solving the problem]

The above object is achieved by connecting a plurality of variable gain circuits having different gain control voltage acceptance ranges in parallel.
More specifically, the gain control voltage has an acceptable range of V1 to V2, and the gain is changed from G1 to G2 (G1 <G2) correspondingly. Is V3 to V4, and the corresponding gain change range is 0 to 3.
G4 times, the magnitude relationship between V3 and V4 with respect to V1 and V2, respectively, is large when V2> V1 and small when V2 <V1. Achieved by connecting.

Here, the acceptable range of the gain control voltage means that the gain at the boundary of the range is maintained for the control voltage exceeding the range, and the gain control is possible only for the control voltage within the range. I do.

[Action]

Now, consider a case where V2> V1 and V3 and V4 are both larger than V1 and V2, respectively.

When the gain control voltage Vc gradually increases from V1, the gain of the first variable gain circuit gradually increases from G1, the gain reaches G2 at Vc = V2, and maintains G2 for Vc above. .
On the other hand, the gain of the second variable gain circuit keeps zero until the gain control voltage Vc reaches V3, starts rising from zero only after Vc exceeds V3, and reaches V4 when Vc = V4.

It should be noted here that the second variable gain circuit has no effect or side effect on the operation of the entire circuit when a gain control voltage of Vc <V3 is given. Incidentally, the relationship between the amplitude of the voltage applied as an input signal to the variable gain amplifier circuit and the gain control voltage is as follows.
The maximum value is obtained when the voltage is equal to or lower than V1 and the voltage decreases as the gain control voltage increases. This can be understood from the fact that the AGC circuit to which this circuit is provided works to increase the gain control voltage as the input signal amplitude decreases and to keep the output signal amplitude at a constant value. From the above,
It can be seen that the amplitude of the input signal to be accepted by the second variable gain circuit can be smaller than that of the first variable gain circuit. Specifically, the amplitude of the input signal to be received by the second variable gain circuit is the gain of the first variable gain circuit when a gain control voltage of Vc = V3 is given. Is equal to the input signal amplitude to be accepted divided.

Therefore, the second variable gain circuit can be designed for an input signal having a smaller amplitude than that of the first variable gain circuit. There is no increase in bias current as required by technology.

In the present variable gain amplifying circuit including the first and second variable gain circuits, the first variable gain circuit operates on a large amplitude input signal, and the first variable gain circuit operates on a relatively small amplitude input signal.
By operating both the variable gain circuit and the second variable gain circuit, it is possible to comprehensively control the gain in a wide range for a wide range of input signal amplitude, and the original object is achieved.

〔Example〕

A first embodiment of the present invention will be described with reference to FIGS. In FIG. 1, reference numerals 11 and 12 denote first and second variable gain circuits, respectively, and reference numerals 21 and 22 denote respective signal input terminals, 3
1 and 32 are respective output terminals, and 41 and 42 are respective gain control terminals. Reference numerals 2, 3, and 4 denote signal input terminals, output terminals, and gain control voltage application terminals of the entire circuit, to which corresponding terminals of the first and second variable gain circuits are connected in parallel, respectively. I have. However, the parallel connection referred to here means to apply substantially the same signal (or voltage) to two terminals or to apply two outputs equally. FIG. 2 shows the relationship between gain control voltage and gain (gain control characteristic) of the first and second variable gain circuits. In the figure, the solid line A indicates the gain control characteristic of the first variable gain circuit, and the solid line B indicates the gain control characteristic of the second variable gain circuit. The gain of the first variable gain circuit is such that the gain control voltage is from V1.
It is controlled only when it is in the range up to V2, and changes from G1 to G2. For control voltages outside this range, the gains G1 and G2 at the boundary are maintained. That is, the acceptable range of the gain control voltage of the first variable gain circuit is from V1 to V2. Similarly, the gain of the second variable gain circuit is zero when the gain control voltage is equal to or lower than V3, is constant at G4 when the gain control voltage is equal to or higher than V4, and V3 and V4
The gain is controlled only between. That is, the acceptable range of the gain control voltage of the second variable gain circuit differs from the acceptable range of the first variable gain circuit, and is from V3 to V4. A dotted line C shows a gain control characteristic of the entire circuit including the first and second variable gain circuits connected in parallel. When the gain control voltage Vc is gradually increased from V1, only the first variable gain circuit operates in the region of V1 <Vc <V3, and both variable gain circuits operate in the region of V3 <Vc <V2. Controlled, V2 <Vc
In the region <V4, the first variable gain circuit exhibits a constant gain, and only the second variable gain circuit is subject to gain control. Second
In the variable gain circuit described above, the gain is zero in the region of Vc <V3. At this time, no problem occurs even if an excessive input is applied. It is in the region of VcV3 that the input signal amplitude to be accepted by the second variable gain circuit should be considered. However, the signal amplitude input when VcV3 is smaller than the signal amplitude input when Vc = V1, so that the input signal amplitude to be accepted by the second variable gain circuit is equal to that of the first variable gain circuit. Smaller is allowed. Let the gain of each variable gain circuit be expressed as a function of the gain control voltage as follows:

The gain of the first variable gain circuit ₁ (Vc) The second 〃 ₂ (Vc) The gain of the whole circuit (Vc) According to this description, the input signal amplitude to be accepted by the second variable gain circuit is , that of _{1 (V} of the first variable gain circuit
1) / ₁ (V3). Therefore, the second variable gain circuit only has to handle an input signal having a relatively small amplitude as compared with the first variable gain circuit, and its maximum gain (G4 in the example of FIG. 2).
It becomes easy to design high. As a result, as a general circuit, a wide gain variable width of G1 to (G2 + G4) can be obtained as indicated by a dotted line c.

In FIG. 2, each gain control characteristic is represented by a combination of straight lines, but this is for the sake of clarity of explanation, and is such a smooth curve-shaped gain control characteristic often found in an actual circuit. The characteristics do not hinder the implementation of the present invention. In the same figure, V3 <V2
, And the acceptable range of the gain control voltage is made different so that the first and second variable gain circuits have a slightly overlapping area. However, this is not essential, and for example, the two ranges are The receiving ranges of the gain control voltages of the first and second variable gain circuits may be made different from each other so that they are in contact with each other or if there is a slight gap.

The above description with reference to FIG. 2 relates to a case where a circuit of a gain control characteristic in which the gain increases with an increase in the gain control voltage, that is, a characteristic on the upper right in FIG. In this case, the conditions relating to the acceptable range of the gain control voltage for the present invention to hold are V1 <V2, V1 <V3, V2 <V4, where G1 <G2.

Next, in the case where the gain control characteristic is opposite to the above,
Supplementary explanation will be given with reference to the drawings. In this case, the gain control voltage is V1
The gain gradually increases as it gradually decreases from, and only the horizontal axis is inverted in the example of FIG. Accordingly, the operation of the present invention will be readily understood by reference to the foregoing. In this case, the conditions regarding the acceptable range of the gain control voltage are as follows: V1> V2, V1> V3, V2> V4, where G1 <G2.

Next, a second embodiment of the present invention will be described with reference to FIGS. In FIG. 4, reference numeral 13 denotes a third variable gain circuit.
23, 33, and 43 are a signal input terminal, an output terminal, and a gain control terminal of this circuit, respectively. The rest is the same as the first embodiment. That is, in the second embodiment, the first, second, and third
Are connected in parallel. FIG. 5 shows gain control characteristics of each variable gain circuit. The solid line A shows the gain control characteristic of the first variable gain circuit, from Vc = V1 to Vc
The gain changes from G1 to G2 for changes up to = V2. Similarly, b is the gain control characteristic of the second variable gain circuit, where Vc = V3
The gain changes from zero to G4 for changes from Vc to V4. C is the control characteristic of the third variable gain circuit, where Vc = V5
The gain changes from zero to G6 for changes from Vc to Vc. The dashed-dotted line E is the overall gain control characteristic, and the gain changes from G1 to (G2 + G4 + G6) with respect to the change from Vc = V1 to Vc = V6. The second variable gain circuit operates at Vc
In the V3 region, as in the case of the first embodiment, it is sufficient to handle an input signal having a smaller amplitude than that of the first variable gain circuit, so that the maximum gain (corresponding to G4) is set to the first variable gain circuit. It is easy to design a variable gain circuit higher than that of the variable gain circuit (corresponding to G2). The operation region of the third variable gain circuit is a smaller amplitude input signal region than that of the second variable gain circuit, and it is easy to obtain a higher maximum gain (corresponding to G6).
As described above, the first, second, and third variable gain circuits have different maximum input signal amplitudes to be received, and are designed to obtain high maximum gains corresponding to the respective variable gain circuits. Can be done without increasing. Thus, a variable gain amplifier circuit having a wide gain variable width is realized.

Incidentally, in FIG. 5, the gain control characteristic obtained by connecting the first variable gain circuit and the second variable gain circuit in parallel is indicated by a dotted line d. The one-dot chain line E, which is the overall gain control characteristic, can be regarded as obtained by a combination of the characteristic of the dotted line d and the gain control characteristic of the third variable gain circuit (solid line c). Accordingly, the gain control characteristic (dotted line d) obtained by combining the first and second circuits is
The gain control characteristic of the first variable gain circuit in the first embodiment is regarded as equivalent to the gain control characteristic of the first variable gain circuit (FIG. 2A), and the gain control characteristic of the third variable gain circuit in the second embodiment is considered. (FIG. 5C) can be regarded again as equivalent to the gain control characteristic (FIG. 2B) of the second variable gain circuit in the first embodiment. That is, the configuration in which the first and second variable gain circuits in the second embodiment are connected in parallel can be regarded as a configuration example of the first variable gain circuit in the first embodiment. In other words,
The second embodiment is an embodiment of the first embodiment and can be said to be included therein. From a different point of view, it can be said that the second embodiment has the first variable gain circuit in the first embodiment configured with the circuit format shown in the first embodiment. If this idea is pushed forward, the number of variable gain circuits connected in parallel can be increased indefinitely in principle, and accordingly, a variable gain amplifier circuit with a wider gain variable width can be realized. .

Next, a third embodiment of the present invention will be described with reference to FIGS. In FIG. 6, the portion surrounded by two dotted lines is the first variable gain circuit 11 and the second variable gain circuit 11 in the first embodiment.
Of the variable gain circuit 12. The same reference numerals as those in the first embodiment denote the same symbols assigned to the terminals. The first and second two variable gain circuits include a current source 51 (52) exhibiting a transconductance gm1 (gm2) with respect to an input signal voltage, and a differential transistor pair Q11, Q12 (Q21, Q2).
2). The differential transistor pair shunts the signal current flowing out of the current source and outputs the respective output terminals 31 (32).
Tell The shunt ratio (shunt ratio) depends on the gain control voltage applied to the bases of the transistor pairs, whereby the transconductance from the signal input terminal 21 (22) to the output terminal 31 (32) is controlled. Thus, a so-called current distribution type variable gain circuit is formed. The load _RL connected to the output terminal 3 acts in common for the first and second variable gain circuits, and a signal voltage generated at both ends of the load _RL is used as an output voltage. minus in applied signal voltage V _i to become voltage gain. FIG.
This shows how the gain thus defined is controlled by the gain control voltage Vc (gain control characteristic). In FIG. 7, the scale on the vertical axis is normalized by setting the maximum value (gm1 × _RL ) of the gain of the first variable gain circuit to 1. In the figure, curves A and B are gain control characteristics of the first and second variable gain circuits, respectively, and C is an overall gain control characteristic. The gain control characteristic diagram of the first embodiment (second
In contrast to the figure, the minimum gain of the first variable gain circuit
It can be seen that this corresponds to the case where G1 is zero. When the gain control voltage receiving ranges of the first and second variable gain circuits are symmetrical with respect to FIG. 2, V1 = −100 mV, V2 = 100 mV, V3 = 0.
V, V4 = 200 mV, and the second variable gain circuit
The acceptable range of the gain control voltage of the variable gain circuit is shifted by 100 mV. This shift of the acceptance range is obtained by inserting a voltage source Vd at the base of Q22 of the transistor pair of the second variable gain circuit.

When the gain of the variable gain circuit is expressed as a function of the gain control voltage Vc as described above, it is as follows.

_{(Vc) = 1 (Vc)} + 2 (Vc) (3) where, h = kT / q, k : Boltzmann constant, T: absolute temperature, q: electronic charge, epsilon: base of natural logarithm As can be seen, To shift the gain control voltage acceptance range of the second variable gain circuit, a voltage source Vd having the opposite polarity may be inserted at the base of Q21.

Next, a fourth embodiment of the present invention will be described with reference to FIG.
Compared to FIG. 6, the transistors Q13 and Q14 and the resistor R1
The differential amplifier circuit composed of R1, R13 and R14 corresponds to the current source 51 having the transconductance gm1 in FIG. 6, and similarly, the differential amplifier circuit composed of the transistors Q23 and Q24 and the resistors R21, R23 and R24 is a current source. Equivalent to 52. The mutual conductance of these two differential amplifier circuits is expressed as follows.

gm1 ≒ 1 / R11 (4) gm2 ≒ 1 / R21 (5) Therefore, when R11 and R21 are selected to appropriate values, the same gain control characteristics as those in FIG. 7 can be obtained. At this time, in order to satisfy gm1 <gm2, the resistance value of R21 must be reduced, but as can be seen from the characteristics in FIG.
Since the second variable gain circuit operates in the high gain region of the first variable gain circuit, that is, in the small amplitude signal region, R
It is not necessary to increase the bias current flowing in advance 24 in particular. Therefore, a variable gain amplifier circuit having a wide gain variable width, which is an object of the present invention, can be easily obtained.

Next, a fifth embodiment of the present invention will be described with reference to FIG.
In this embodiment, Q13, R13, Q23, and R23 are deleted from the fourth embodiment. Q14 and Q24 operate as grounded base amplifiers, the transconductance is expressed in the same manner as in the equations (4) and (5), and the operation is the same as in the fourth embodiment.

Next, a sixth embodiment of the present invention will be described with reference to FIGS. In Fig. 6, Q11, Q12, Q11 ', Q12', Q14, Q1
4 ', R11, R11', R14, R14 'constitute a first variable gain circuit, and Q21, Q22, Q21', Q22 ', Q24, Q24', R21, R24, R24 '
Form a second variable gain circuit. Each variable gain circuit has two pairs of differential transistors for current distribution, and they work complementarily. Therefore, the fluctuation of the DC potential of the output terminal due to the gain control is suppressed.
Also, the transconductance of the first variable gain circuit is R1
It is determined by 1 and R11 ', and the gain is controlled between them.

The gain of each variable gain circuit can be expressed as a function of the gain control voltage as follows:

_{(Vc) = 1 (Vc)} + 2 (Vc) (8) where (corresponding to about 25mV) h = kT / q FIG. 11 shows the gain control characteristic. In the figure, curves A and B respectively show gain control characteristics of the first and second variable gain circuits, and curve C shows an overall gain control characteristic. The scale on the vertical axis is normalized so that the minimum gain of the first variable gain circuit is 1. The figure shows an example when R ₁₁ ′ / R11 = 3, R11 / R21 = 2, and Vd = 100 mV. The operation of the second variable gain circuit is started when the gain control voltage Vc exceeds about 0 V. At this time, the gain of the first variable gain circuit has increased to twice. Therefore, the input signal amplitude handled by the second variable gain circuit is the first variable gain circuit.
Of the variable gain circuit of FIG. Therefore, even though the resistance value of R21 is smaller than R11 by half, the bias current to be flown into R24 in advance may be the same as that of R14.
By the way, in order to obtain the effect of suppressing the fluctuation of the DC potential of the output terminal due to the gain control described above, R14 = R14 ', R24 = R24'
As a result, in this embodiment, assuming that the current consumption of the first variable gain circuit is 1, the second current gain is also 1 and the total current consumption is 2. On the other hand, as in the prior art, the second variable gain circuit is omitted,
If it is attempted to obtain characteristics equivalent to those of the present embodiment using only the first variable gain circuit, the resistance of R11 is reduced to 1/3, and accordingly,
The resistance of R14 and R14 'must also be reduced by a factor of three to increase the bias current by a factor of three. As a result, the current consumption becomes 3, which is 1.5 times as large as that of the present embodiment. The effect of reducing the current consumption according to the present invention is extremely large when the number of variable gain circuits connected in parallel is increased to obtain a wider gain variable width as in the second embodiment. Become.

Next, the effect of suppressing excessive noise according to the present invention will be described. Differential transistor pair for current distribution (Q11 and Q1
2, Q11 'and Q12') are generally known to cause excessive noise. Transistors generally have various noise generating factors, and can be considered as a noise electromotive force in series with a base electrode. This noise electromotive force is converted into collector current noise by the mutual conductance of the differential transistor pair and mixed into the signal current. By the way, the transconductance increases in proportion to the current of the sink current source (Q14, Q14 ', Q24, Q24') which sinks the current of the coupled emitter of the differential transistor pair. It reaches a peak when the emitter current of the transistor is balanced (the base potential is balanced). As can be understood from the description of the effect of reducing the consumption flow according to the present invention, according to the present invention, the above-described effect of reducing the suction current can be obtained.
Therefore, the mutual conductance of the differential transistor pair with respect to the noise electromotive force is reduced, and as a result, the effect of suppressing the generation of the excessive noise is obtained. In addition,
As can be seen from FIG. 11, the point at which the differential transistor pair becomes balanced is Vc = 0 V in the first variable gain circuit, Vc = 100 mV in the second variable gain circuit, and the noise electromotive force is different. Since the peak points of the transconductance do not coincide with each other, the effect of suppressing the occurrence of excessive noise can be obtained from this viewpoint as well.

Incidentally, also in the sixth embodiment (FIG. 10), each input signal can be supplied via an emitter follower transistor as in the example shown in FIG.

Next, a seventh embodiment of the present invention will be described with reference to FIG.
This embodiment is different from the sixth embodiment (FIG. 10) in Q1.
4 ″ and R14 ″ are added, and the point where the connection point of R11 ′ is moved from the emitter of Q14 ′ to the emitter of Q14 ″ is new.
This can be regarded as a modification of the first variable gain circuit. R1
Since the signal injected into Q14 "through 1 'is always effectively used as an output signal regardless of the gain control, the resistance of R11 can be increased by that amount, and the gain of the first variable gain circuit can be increased. The gain control characteristic of the first variable gain circuit is expressed as follows, following the equation (6).

From the comparison between the expressions (6) and (6 ′), it can be understood that −1 of the second term numerator in ｛｝ is removed, and the gain variable width increases.

Next, an eighth embodiment of the present invention will be described with reference to FIGS. This embodiment differs from the seventh embodiment (FIG. 12) in that Q31, Q32, Q31 ', Q32', Q34, Q34 ', R34, R34', R22, V
What is new is that a third variable gain circuit composed of d2 is added. This is functionally equivalent to the second embodiment (FIG. 4). Expressing the gain of each variable gain circuit as a function of Vc is as follows.

(Vc) = ₁ (Vc) + ₂ (Vc) + ₃ (Vc) (12)
The design example of each constant is shown below.

R11 '/ R11 = 1, R11' / R21 = 2, R11 '/ R31 = 4
It is shown in Figure 14. In the figure, the scale on the vertical axis is normalized by _RL / R11 '. The horizontal axis represents the gain control voltage Vc, and is scaled using h (= kT / q) as a scale. The curve group is 0, 1h, 2 while Vd1 = Vd2 in order from the left.
The respective characteristics when h, 3h,... 8h are shown. In the case of Vd1 = Vd2 = 8h, the gain control is relayed in sequence while contacting the acceptable range of the gain control voltage of each variable gain circuit, and the effects of current saving and suppression of excessive noise, which are the objects of the present invention, are best exhibited. I do. However, as can be seen from the figure, there is a problem with the smoothness of the control characteristics. When Vd is small, the control characteristics are smoother, but the effect on the object of the present invention is weakened. Vd =
Practical settings are 2h to 8h, but especially Vd1 = Vd2 = about 4h is the setting that satisfies both the best.

Next, a ninth embodiment of the present invention will be described with reference to FIG.
This embodiment is new in that the signal output unit includes a common base transistor. As a result, Q11, Q11 ′, Q14 ″, Q21, Q2
The problem that the high-frequency gain is reduced by the capacitance associated with the 1 'collector electrode is improved. The effect is remarkable when the number of variable gain circuits connected in parallel is large.

Next, a tenth embodiment of the present invention will be described with reference to FIG.
This embodiment is new in that the signal output unit includes D1, D2, Q51, Q52, and the like. As a result, the power supply voltage use efficiency can be improved by the DC level shift, and the effect of improving the high-frequency characteristics as in the ninth embodiment can be obtained. The DC level shift by D1, D2, etc. is described in detail in Japanese Patent Laid-Open Publication No. 59-125107. R11 'is connected to the emitter of Q52,
52 also plays the role of Q14 ″.

Next, an eleventh embodiment of the present invention will be described with reference to FIG.
This embodiment is different from the eighth embodiment (FIG. 13) in that switches S1 and S3 are added. When both S1 and S2 are tilted to the A side, the same operation as in the eighth embodiment is performed. In a state where the fallen to the B-side it is biased to the voltage V _G. V _G is set from 100mV or more higher maximum possible value is the gain control voltage Vc, gain of the variable gain circuit the switch is lying on the B side is the minimum value, i.e., zero. Therefore, when only S2 is tilted to the B side, the gain control ranges obtained by the first and second variable gain circuits are different from those of S1 and S2.
Are both on the B side, the gain control range is obtained only by the first variable gain circuit. Thus, the variable gain range can be selected. Even when the number of variable gain circuits connected in parallel is larger, a similar function can be obtained by adding a switch correspondingly.

Next, a twelfth embodiment of the present invention will be described with reference to FIG.
In the present embodiment, reference numeral 6 is a gain control voltage generation circuit. The rest is the same as the first embodiment. The gain control voltage generation circuit 6 compares the output signal amplitude with a reference, and generates a control voltage for increasing the gain when the output signal amplitude is insufficient. This is usually composed of a signal averaging circuit or an amplitude detection circuit and a comparator. With the configuration of the present embodiment, an AGC circuit for making the output signal amplitude constant is configured. According to the effects of the present invention, it is possible to stabilize the output with respect to a change in the input signal amplitude in a wide range.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a variable gain amplifier circuit that can cope with a wide range of change in the amplitude of an input signal and has a wide variable gain width. Further, an effect of suppressing the generation of excessive noise can be obtained.

[Brief description of the drawings]

 FIG. 1 is a block diagram of a first embodiment of the present invention, FIGS. 2 and 3 are operation explanatory diagrams of the first embodiment, FIG. 4 is a block diagram of a second embodiment of the present invention, FIG. 5 is an operation explanatory diagram of the embodiment of FIG. 2, FIG. 6 is a circuit diagram of the third embodiment of the present invention, FIG. 7 is an operation explanatory diagram of the embodiment of FIG. 3, and FIG. FIG. 9 is a circuit diagram of a fifth embodiment of the present invention, FIG. 10 is a circuit diagram of a sixth embodiment of the present invention, FIG. FIG. 12 is a circuit diagram of a seventh embodiment of the present invention, FIG. 13 is a circuit diagram of an eighth embodiment of the present invention, and FIG. 14 is a circuit diagram of the eighth embodiment of the present invention. FIG. 15 is a circuit diagram of a ninth embodiment of the present invention, FIG. 16 is a circuit diagram of a tenth embodiment of the present invention, and FIG. 17 is a circuit diagram of an eleventh embodiment of the present invention. FIG. 18 is a circuit diagram of a twelfth embodiment of the present invention.

Claims (4)

(57) [Claims] 1. The first, second,..., N-th (where N is an integer of 3 or more) currents whose gains are controlled by supplying the same gain control voltage varying in a predetermined range. A distribution type variable gain circuit is connected in parallel with each other, and the same input signal is supplied to the N current distribution type variable gain circuits and amplified according to the respective gains. , The Nth current-distribution-type variable gain circuit has a configuration in which the i-th (with the exception that the reception range of the gain control voltage is different) i
= 1, 2,..., N), the gain control voltages V _i1 , V set i-th as viewed from one limit side of the predetermined change range of the gain control voltage. _The accepting range V _i having _{i 2 as} a limiting voltage on both sides is assigned. In the first current distribution type variable gain circuit, one limiting voltage V ₁₁ and the other limiting voltage V of the assigned accepting range V ₁ are assigned. ₁₂
The gain changes between values G ₁₁ and G _12, where G ₁₁ <G ₁₂ , and the assigned limit in the acceptable range V ₁ for the change in the gain control voltage at the outside than the one limit voltage V _11, a gain value G _11, the limit voltage at the assigned the receiving range V ₁ is said other V ₁₂ against the change in the gain control voltage at the outside than the limit, the gain is respectively set to the value G _12, in the current distribution type variable gain circuit of said i other than the current distribution type variable gain circuit of said first For a change in the gain control voltage between one limit voltage V _i1 and the other limit voltage V _i2 of the assigned acceptance range V _i , the gain has a value of 0, G _i2 (where G _i2> 0) varies between, and assigned for the change of the gain control voltage at the outside than the one limit of the limit voltage V _i1 in the receiving range V _i The gain value 0, for the change of the gain control voltage at the outside limit voltage than said other limit of the V _i2 of the allocated the receiving range V _i, setting each gain to a value G _i2 A variable gain amplifier circuit. 2. The method according to claim 1, wherein the second current-distribution-type variable gain circuit has a second gain.
A variable gain amplifier circuit wherein the maximum amplitude of the input signal is smaller when the gain control voltage is within the allocated reception range in the Nth current distribution type variable gain circuit. 3. The ith current distribution type variable gain circuit according to claim 1, wherein the emitter electrodes of the first and second transistors are respectively coupled to each other, and the ith current distribution type variable gain circuit responds to the input signal from the coupling point. Signal current is injected,
The injected signal current is shunted to the first and second transistors at a ratio corresponding to the gain control voltage applied between the base electrodes of the first and second transistors, and is applied to the first transistor. The output signal current is taken out from the collector electrode, and the first to Nth current distribution type variable gain circuits are all connected to the collector electrode side of the first transistor.
It is assumed that the N-th current distribution type variable gain circuit is connected in parallel, and in the second to N-th current distribution type variable gain circuits,
A variable gain amplifier circuit comprising means for causing different offsets in the gain control voltages applied between the base electrodes of the second transistor. 4. A transistor according to claim 1, 2 or 3, wherein a transistor constituting a grounded base amplifier is connected to a parallel connection point where output terminals of said N current-variable variable gain circuits are connected to each other. Variable gain amplifier circuit.