JP2859048B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer.

[0002]

2. Description of the Related Art An example of a conventional microcomputer is shown in FIG. In FIG. 3, the microcomputer includes an instruction unit 1 that fetches an instruction and decodes the fetched instruction, an operation unit 2 that operates according to the decoded instruction, a program counter 3 that indicates an address of the instruction to be fetched, An instruction memory 4 for a privileged interrupt indicated by the program counter 3, an interrupt control unit 5 for performing a privileged interrupt process, and an instruction unit 1
And an input / output unit 6 operating independently of the arithmetic unit 2 and a command decoder 7.

A clock signal 101 is externally supplied to the microcomputer, and operations are performed based on the clock signal 101. The instruction written in the instruction memory 4 is fetched and decoded by the instruction unit 1 when the privileged interrupt is activated, and the instruction is executed in the arithmetic unit 2. This privileged interrupt is in a special state defined in advance in the arithmetic unit 2 (this state may be of various patterns, but is not the essence of the present invention, and will not be described here). And transmitted to the instruction unit 1 via the control line 211. Further, in the instruction unit 1, in response to the privileged interrupt request, a request signal for outputting a head address specified in advance in the instruction memory 6 is output and sent to the program counter 3 through the control line 213. In the instruction memory 4, the output from the program counter 3 and the address bus 2
In response to the address signal input via the interface 05, an instruction code signal corresponding to the address signal is output and input to the instruction unit 2 via the instruction code bus 203.

In the instruction unit 1, the input instruction code is decoded, the operation of the program counter 3 is controlled through the control line 213 in accordance with the instruction, and the operation of the arithmetic unit 2 is controlled through the data bus 205. Is controlled. However, since the operation of this unit has no direct relation to the present invention, it will not be described here.

The microcomputer can fetch an instruction signal from outside as well as the instruction memory 4 included therein. For this, the program
In the counter 3, it is possible to output an address signal to the outside through the address bus 201,
Further, an external instruction signal is transmitted to the instruction code bus 202.
Can be input to the instruction unit 1. When the interrupt signal 102 is externally input, the interrupt control unit 2
, An interrupt signal 103 is generated and output, and transmitted to both the instruction unit 1 and the arithmetic unit 2. In response to the interrupt signal 103, the instruction unit 1 and the arithmetic unit 2 execute predetermined processing, respectively. When an external reset signal 104 is input from outside, both the instruction unit 1 and the arithmetic unit 2 are initialized.

[0006] The input / output unit 6 includes the arithmetic unit 2.
And a mode signal 106 for determining an operation mode, including a test clock 105 serving as an operation reference of the input / output unit 6, and an input data signal 10
7, output data signal 108 and input / output unit 6 concerned
A test / reset signal 109 for resetting is input / output. The data signal input to the input / output unit 6 can be viewed as a simple data signal,
It can also be viewed as a command signal that causes the microcomputer to perform some operation. For this purpose, the above-described mode signal 106 may be controlled, and this function is provided in the input / output unit 6. For example,
To send a predetermined data signal as a command signal to the microcomputer, a code signal 10
6, the operation mode is set to the command input mode, and the data signal 107 is subsequently input. The input data signal is transmitted to the bus 204
Through to the command decoder 7. In the command decoder 7, a predetermined control signal is input to the instruction unit 1 and the arithmetic unit 2 via control lines 208 and 207 in response to the command signal.
A predetermined operation is instructed. Since these operations are performed with reference to the test clock signal 106, the instruction unit 1 and the arithmetic unit 2 operate independently.

[0007]

In the conventional microcomputer described above, when the microcomputer is started, in order to send the values of the internal registers and the memory to the external host machine, the internal memory of the instruction memory 4 is required. , 113, 11 in advance
It is necessary to write necessary instructions including 4 and the like. However, in order to write these instructions into the instruction memory 4, it is indispensable to execute them via the input / output unit 6. In this case, if the address is accessed by the instruction unit 1 during the writing, it is impossible to guarantee the normal operation of the microcomputer. When writing is being performed by the input / output unit 6, the instruction unit 1 must surely access a part other than the instruction memory 4. However, generally, at the time of startup, it is not possible to define which area is being accessed. Therefore, conventionally, there is a disadvantage that data cannot be reliably written to the memory area at the time of startup.

In the case where the microcomputer starts operating in synchronization with the external reset signal 104 and before that it needs to be stopped without performing any processing, It cannot respond as an operation. For example, considering a case where an instruction for processing for performing the above-described privileged interrupt is written into the instruction memory 4, at the time of writing the instruction, it is assumed that bidirectional access is not performed as described above. In addition, if the microcomputer operates without permission after the instruction is written into the instruction memory 4, a privilege interrupt occurs at a stage before the required time. Not preferred. In order to prevent such a situation, there is a method of stopping the operation of the microcomputer by a halt instruction. However, when such a measure is taken, it is necessary to write an instruction for this purpose.
There is a disadvantage in that the number of available memories in the instruction memory 4 is limited, and further, there is a possibility that the written halt instruction may be executed again.

[0009]

A microcomputer according to the present invention comprises: an instruction unit for fetching / decoding and outputting an instruction described in a memory included in an external or internal memory; An operation unit that executes an operation, an input / output unit that operates independently of the operation of the instruction unit and the operation unit, and inputs and outputs a data signal to and from an external device, And a command decoder that receives a data signal to be decoded as a command signal and outputs a plurality of types of command signals in response to the command signal. Is a predetermined initialization command signal, The reception of the external reset signal input from the outside is stopped via the external reset signal invalidation request signal output from the command decoder, the stopped state is maintained, and the command signal is used to enable the external reset signal. External reset control means for receiving and outputting the external reset signal via an external reset signal validation request signal output from the command decoder,
When the command signal decoded by the decoder is a predetermined initialization command signal, it receives an internal reset signal request signal output from the command decoder, generates a predetermined reset signal, and generates the predetermined reset signal. When the command signal is sent to the arithmetic unit and the command signal becomes a signal requesting the activation of an external reset signal, the command unit and the arithmetic operation are performed via the external reset signal input from external reset control means. Reset signal generating means for outputting a signal for releasing the reset state of the unit.

[0010]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, the present embodiment has an instruction unit 1 that fetches an instruction and decodes the fetched instruction, an operation unit 2 that operates according to the decoded instruction, and a program that indicates the address of the instruction to be fetched. The counter 3, the instruction memory 4 for the privileged interrupt indicated by the program counter 3, the interrupt control unit 5 for performing the privileged interrupt processing, and the transfer of input / output data signals independently of the instruction unit 1 and the arithmetic unit 2 An input / output unit 6 operable to perform the operation, and a command decoder 7
And an external reset control unit 8 and a reset signal generation unit 9. As is clear from comparison with the above-described conventional example shown in FIG. 3, the external reset control unit 8 and the reset signal generation unit 9 are different from the configuration described in the related art section in the above-described manner. , Have been newly added.

In FIG. 1, after the microcomputer is started, an external input / output unit 6
The data signal 107 is input. In the input / output unit 6, when it is confirmed that the data signal 107 is a command signal, the data signal is transmitted to the data bus 20.
4 to the command decoder 7. In the command decoder 7, when this command signal is coded and the decoding result is an initialization command signal, an external reset signal for invalidating the external reset signal 104 corresponding to the command signal is invalidated. The activation request signal 110 is output and input to the external reset control unit 8. In response to the external reset signal invalidation request signal 110, the external reset control unit 8 stops the function of receiving the external reset signal 104 input from outside.

At the same time, the command decoder 7 generates and outputs an internal reset request signal 112 for requesting the output of an internal reset signal, instead of the external reset signal 104. It is sent to the unit 9. In the reset signal generator 9,
In response to the internal reset request signal 112, a reset signal 113 is generated and output, and is input to the instruction unit 1 and the arithmetic unit 2. This reset signal 113
In response, instruction unit 1 and arithmetic unit 2 perform a predetermined initialization operation. In the reset signal generation unit 9, when an output request for an internal reset signal is once accepted by the above-mentioned initialization command, the external reset signal activation request signal 111 input from the command decoder 7 is output. After the enable command is executed, the reset signal 113 is continuously output until the external reset signal 104 is actually input from the outside and the external reset signal 104 is cut off.

FIGS. 2 (a), (b), (c) and (d)
Is a timing chart showing this operation state. In FIG. 2, all logics are active high. When the internal reset request signal 112 corresponding to the initialization command is output from the command decoder 7 as an active signal, the internal reset request signal 1
As a trigger of 12, the reset signal 113 output from the reset signal generator 9 becomes active. Thereafter, the external reset signal 104 is ignored until the external reset enable request signal 111 is output at the active level. Then, when the external reset enable request signal 111 becomes active level and the external reset signal 104 is actually input from the outside and then the external reset signal is turned off, the reset signal 113 is also turned off.

While the reset state is maintained by the initialization command, data written to the instruction memory 4 is transmitted via the input / output unit 6. At this time, since the program counter 3 is also in a reset state, the program counter 3 is not in a state of pointing to a storage area in the instruction memory 4. Therefore, the risk of simultaneous access from two directions is eliminated.

When the writing of the predetermined data to the instruction memory 4 is completed, the processing exits the reset processing and the processing is started. For this reason, the input / output unit 6 is instructed to activate the external reset signal 104 by a command. Is input. The input / output unit 6 confirms that the data is a command and inputs the data to the command decoder 7. The external reset signal validation request signal 111 decoded and output to the command decoder 7 is output as an active signal and input to the external reset control unit 8. After that, when the external reset signal 104 is input from the outside, the external reset control unit 8 receives the external reset signal 104 and sends it to the instruction unit 1 and the arithmetic unit 2 as a reset signal 113. When the input of the external reset signal 104 is interrupted, the reset signal 113 for the instruction unit 1 and the arithmetic unit 2 becomes inactive accordingly. In response to the input of such a reset signal, a predetermined operation by the instruction unit 1 and the arithmetic unit 2 is started.

[0016]

As described above, according to the present invention, the initialization state of the microcomputer can be held until the microcomputer is designated, and the instruction is transmitted from the input / output unit which operates independently of the instruction unit and the arithmetic unit. When writing data to the memory, it is possible to reliably access the storage area other than the storage area of the instruction memory, and it is possible to reliably write data to the instruction memory without error.

Also, after the data is written to the instruction memory, there is an effect that the microcomputer can be executed out of the initialization state in synchronization with the external reset signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing an operation in the embodiment.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Instruction unit 2 Operation unit 3 Program counter 4 Instruction memory 5 Interrupt control unit 6 I / O unit 7 Command decoder 8 External reset control unit 9 Reset generation unit

Claims (1)

(57) [Claims] 1. An instruction unit for fetching / decoding an instruction described in a memory included in an external or internal memory and outputting the instruction, an operation unit for executing an operation according to the instruction decoded by the instruction unit, and the instruction unit An input / output unit that operates independently of the operation of the arithmetic unit and inputs / outputs a data signal to / from an external device; and receives a data signal input through the input / output unit and decodes the command signal. A command decoder that outputs a plurality of types of command signals in response to the command signal, wherein the command signal decoded by the command decoder is a predetermined initialization command signal. Is the external reset output from the command decoder Via the signal invalidation request signal, stop receiving an external reset signal input from the outside, maintain the stopped state, and when the command signal becomes a signal requesting the activation of the external reset signal, External reset control means for receiving and outputting the external reset signal via an external reset signal validation request signal output from the command decoder; and resetting the command signal decoded by the command decoder to a predetermined initialization. When the command signal is a command signal, a predetermined reset signal is generated in response to an internal reset signal request signal output from the command decoder, and is transmitted to the instruction unit and the arithmetic unit. If the signal requires the activation of the external reset signal, Via the external reset signal that is more input, microcomputer, characterized in that it comprises a reset signal generating means for outputting a signal for releasing the reset state of said instruction unit and said arithmetic unit.