JP2854204B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter for converting an analog input value into a digital value, and in particular, it is possible to reduce the size and to perform high-speed A / D conversion. It relates to an A / D converter. Alternatively, the present invention relates to an A / D converter provided with a plurality of comparators for converting an analog input value into a digital value, and in particular, suppresses a peak value of fluctuations in current consumption and reduces power supply noise accompanying fluctuations in current consumption. The present invention relates to an A / D converter that can be reduced.

[0002]

2. Description of the Related Art A / D converters have long been used in the industrial field for measuring devices, such as digital voltmeters and programmable power supplies. In recent years, A / D
Converters have come to be used in consumer applications such as compact disk players and special fields such as codecs for connecting telephones to digital lines.

[0003] A home VTR (video tape recorder)
) For special reproduction and noise reduction on the device.
A capable of high-speed operation of 6 to 8 bits at 10 to 20 MHz
/ D converter is used. Relatively large DR
A / D converters have been widely used in image processing devices and digital signal processors due to recent advances in digital technology, such as the use of dynamic random access memory (AM) at relatively low cost.
A / D converters used in such image processing devices and digital signal processors are required to operate at higher speeds.

A flash A / D converter is known as an A / D converter capable of operating at high speed. This flash A / D converter is, for example, when it is an n-bit flash A / D converter,
By operating a total of (2 ⁿ -1) comparators simultaneously, A
/ D conversion. The sum of these (2 ⁿ −
To each of the 1) comparators, different reference voltages having different voltages obtained by dividing a reference voltage by using a ladder resistor in which a total of 2 ⁿ resistance elements having the same resistance value are connected in series are input. . Therefore, each comparator
The comparison reference voltage and the analog signal voltage respectively input are compared. Further, based on the comparison results by such a total of (2 ⁿ -1) comparators, an encoded n-bit digital signal is output. According to such a flash type A / D converter, a digital signal corresponding to an input analog signal voltage can be obtained much faster than an integration type A / D converter or a successive approximation type A / D converter. it can.

[0005] Regarding an A / D converter capable of high-speed operation, Japanese Patent Publication No. 2-39136 discloses a technique related to a so-called two-step flash A / D converter in recent years. The two-step flash A / D converter disclosed in Japanese Patent Publication No. 2-39136 is:
For example, if this is an (m + n) -bit A / D converter, first, A / D conversion corresponding to the upper m bits is performed using a total of (2 ^m -1) comparators, and then, the upper m bits Based on the result of the A / D conversion, A / D conversion corresponding to the lower n bits is performed using a total of (2 ⁿ -1) different comparators. Therefore, the total number of comparators used in the two-step flash A / D converter is (2 ^m +2 ⁿ −
2), which can be greatly reduced as compared with the above-mentioned general flash A / D converter.

Further, such a two-step flash type A
In recent years, a chopper type comparator has been used as a comparator of the / D converter. This chopper type comparator is a CMOS (complementary metal oxide se
miconductor) First, input the analog signal voltage to the capacitor connected in series to the input of the inverter.
By shorting its input and output of the CMOS inverter, a charge Q corresponding to the analog signal voltage is stored on the capacitor. Thereafter, the input and output of the CMOS inverter are opened, and the capacitor to which the analog signal voltage has been input is connected to the comparison reference voltage. At this time, the output of the CMOS inverter is an output according to the sign of the difference between the analog signal voltage and the comparison reference voltage.

Japanese Patent Application Laid-Open No. 1-259628 discloses an A / D converter.
A technique of providing a correction input terminal in a comparator used for a converter, particularly a comparator using a differential amplifier, is disclosed. The comparator using the differential amplifier is a comparator widely used in the A / D converter together with the chopper type comparator. According to the technique disclosed in Japanese Patent Application Laid-Open No. 1-259628, the technique is not affected by variations in offset voltage,
A highly accurate and high speed A / D converter can be provided.
For example, a MOS of a comparator using the differential amplifier
(Metal oxide semiconductor) In the case of using a transistor, the problem of variation in offset voltage due to uneven threshold voltages of transistors used in pairs can be reduced.

[0008]

However, the flash A / D converter described above has an advantage that it can perform a much higher speed conversion than the integrating A / D converter and the successive approximation A / D converter. However, there is a problem that the number of comparators used is very large.

Further, the two-step flash type A / D described above is used.
In the converter, the usual flash type A / D
Although the number of comparators used is reduced compared to the converter, there is still a problem that the number of comparators used is large. For example, an 8-bit two-step flash A / D converter requires a total of (2 ⁴ +2 ⁴ −2 = 30) comparators. Therefore, the two-step flash type A / D
The flash A / D converter, including the converter, has a problem that the circuit scale becomes large and the chip size when integrated is increased.

The chopper type comparator used in the A / D converter has two voltages to be compared,
That is, the analog input value and the comparison reference voltage must be input alternately. Therefore, the conversion operation time has been long. The A / D conversion operation of the chopper type comparator performs operations such as charging of electric charge according to an analog input value to a capacitor, charging of electric charge according to a comparison reference voltage, and initialization by short-circuit discharge of electric charge. And has a problem such as generation of noise. Further, the chopper type comparator performs such a dynamic operation during the A / D conversion, so that there is a problem that power consumption is relatively large.

On the other hand, a comparator using the differential amplifier used in the A / D converter has an operation speed of 2
It is about 0 to 30 MHz. Therefore, it cannot be used for the A / D converter that performs the conversion operation at a higher speed.

The first invention of the present application has been made in order to solve the above-mentioned conventional problems, and it is possible to further reduce the size and to perform high-speed A / D conversion. Setting of logical thresholds more easily,
An object of the present invention is to provide an A / D converter capable of suppressing variations in various operations due to variations in circuit parameters (hereinafter, referred to as a first object).

On the other hand, the second and third inventions of the present application have been made in order to solve the above-mentioned conventional problems. The present invention suppresses the peak value of the fluctuation of the current consumption, and is accompanied by the fluctuation of the current consumption. An object of the present invention is to provide an A / D converter capable of reducing power supply noise (hereinafter, referred to as a second object).

[0014]

According to a first aspect of the present invention, an A / D converter for converting an analog input value to a digital value outputs a voltage according to a voltage difference between a positive input and a negative input. A voltage corresponding to the magnitude of the comparison reference voltage of the switching comparator is input to the differential amplifier, the output of which is used as the power supply of the switching comparator, and the input and output are short-circuited to the minus input of the differential amplifier. In addition to being connected to the power supply, the power supply includes a power supply buffer including an inverter to which the power supply is supplied, and outputs a comparator output by a switching active element according to a comparator input and a predetermined logic threshold value. When the power supply is supplied, the logical threshold value is set within the range of the analog input value. The first object by providing at least one of the switching comparators described above, introducing the analog input value to the comparator input, and determining the digital value based on the comparator output. It has been achieved.

On the other hand, the second invention has an A / D having a plurality of comparators each receiving an analog input and comparing them with different thresholds set internally or externally.
In the converter, a comparison operation stop switch is provided between the comparator input and the analog input of at least one of the comparators, and the threshold operation is performed in the descending order of the threshold value so that the on / off operation of the comparison operation stop switch is operated according to the output of another comparator. By cascading and sequentially operating a plurality of comparators in a plurality of stages, including those without the comparison operation stop switch, by shifting the operation timing of at least some of the plurality of comparators The second object has been achieved.

In the third invention, the A / D includes a plurality of comparators each of which receives an analog input and compares the analog input with different thresholds set internally or externally.
In the converter, two of the comparators that determine the digital value of the same bit are paired,
A comparison operation stop switch is provided between a comparator input of each of at least one set of comparators and the analog input, and the on / off of the comparison operation stop switches of the pair of comparators is opposite to each other, and a digital of upper bits common to these comparators is provided. In accordance with the outputs of the other comparators that determine the values, by sequentially operating a plurality of comparators including those without the comparison operation stop switch in a plurality of stages, the operation timing of at least some of the plurality of comparators can be determined. By shifting, the second object is achieved.

[0017]

First, the operation of the A / D converter of the first invention will be described.

As described above, the chopper type comparator generally used for the A / D converter and the comparator using the differential amplifier have problems to be improved. In order to solve such a problem, the first invention has been made by finding a comparator different from the conventional one.

In particular, the active element such as a transistor used is such that the degree of its drive is continuously operated when its output is driven (hereinafter referred to as an analog active element). In comparison, active elements such as transistors, such as logic gates such as inverters, are discontinuously turned on or off when their output is driven,
Alternatively, a device using a device that switches almost discontinuously (hereinafter, referred to as a switching active device) is made by focusing on the fact that a much higher speed operation is possible.

For example, DTL (diode-transistor logi)
c) Logic gate, TTL (transistor-transistor logic)
A) A logic gate, an ECL (emitter-coupled logic) logic gate, a CMOS logic gate, or the like outputs a predetermined logic output from the switching active element such as a transistor according to the logic input and a predetermined logic threshold. The first invention is based on a completely new viewpoint of using such a logic gate as a comparator. Such a logic gate using the switching active element is compared with a comparator using the differential amplifier constituted by the analog active element,
Much faster operation is possible.

That is, in the first invention, as described above,
According to a logic input and a predetermined logic threshold, a logic output is output at the switching active element such as a transistor, for example, for a logic gate, the logic input is a comparator input, and the logic output is a comparator output, The switching comparator compares a comparator input with the predetermined logical threshold.

Further, the switching comparator sets the logical threshold to a desired value by adjusting a circuit parameter relating to the switching active element. The value of the logic threshold value set by the switching comparator is set within a possible range of an analog input value which is input to the comparator input and converted into a digital value. Adjustment of the circuit parameter relating to the switching active element in the switching comparator, which is performed to set the logical threshold value of the switching comparator, includes, for example, an amplification factor β of the switching active element, an on-resistance of the switching active element, It can be adjusted by the off-resistance of the switching active element, the threshold voltage of the switching active element, the voltage applied to the switching active element, and the like.

For example, the amplification factor, the on-resistance and the off-resistance of the switching active element can be adjusted by the gate width W and the gate length L when the switching active element is, for example, a MOS transistor. is there.
Further, the voltage applied to the switching active element can be adjusted by the resistance value of a resistance element and the like.
The adjustment can also be performed by the voltage of the power supply supplied to the entire switching comparator including the switching active element.

Note that the switching invention used in the first invention is not specifically limited by the first invention. As described above, a predetermined switching active element is provided according to the comparator input and a predetermined logic threshold. Any circuit can be used as long as it can output the comparator output, and by adjusting the circuit parameters,
The logical threshold may be configured to be set to a desired value within a range that the analog input value can take. With such a CMOS inverter configuration,
It is possible to reduce the power consumption of the switching comparator. The power consumption of the CMOS inverter is extremely low in a steady state where the output does not change. Further, whether the switching comparator is a CMOS inverter or not, a number of different reference voltages that require a general A / D converter, such as the above-mentioned Japanese Patent Publication No. 2-39136, are used. The ladder resistance generated by dividing the voltage from the reference voltage can be made unnecessary in the first invention, and in this case, the power consumption of the ladder resistance becomes unnecessary. In comparison, a comparator using the differential amplifier generally includes a constant current source in the differential amplifier and generates steady power consumption.

As described above, there are various adjustments of the circuit parameters related to the switching active element for setting the logical threshold value in the first embodiment. In the present invention, the setting of the logical threshold is performed by adjusting the supply power supply voltage supplied to the switching comparator according to the present invention, thereby reducing the fluctuation of the logical threshold due to a variation in the manufacturing process of the switching comparator. It is possible. When such a switching comparator is formed into a semiconductor integrated circuit,
Since the logical threshold is adjusted by the voltage of the power supply, a plurality of switching comparators having different logical thresholds can be formed with the same integrated circuit pattern. For example, the size and shape of transistors to be manufactured can be made the same between the switching comparators, and the amount of work for designing an integrated circuit layout pattern can be reduced.

The switching comparator according to the first aspect of the present invention may be configured such that the logic threshold value is variable. For example, a threshold variable switch group including a plurality of threshold variable switch elements may switch a circuit parameter for determining the logical threshold of the switching comparator to make the logical threshold variable. For example, when the individual threshold variable switch elements of the threshold variable switch group are turned on and off, the number of the switching active elements connected in parallel with each other of the switching active element group constituted by a plurality of the switching active elements is determined. And the logical threshold value may be changed accordingly. According to the switching comparator according to the first aspect, in which the logical threshold is variable, the fact that the analog input value to be converted into a digital value is compared with a plurality of the logical thresholds is as follows.
This can be performed by one of the switching comparators, and the number of comparators used in the A / D converter can be reduced.

Hereinafter, the operation of the second invention and the third invention will be described.

In recent years, Bi CMOS (bipolar complement)
2. Description of the Related Art Due to advances in process technology and the like, analog / digital mixed LSIs (large scale integrated circuits) in which an analog circuit portion and a digital circuit portion are mixed on a single semiconductor chip have been widely used. . In particular, the A / D converter is often integrated into a single chip together with the digital circuit portion due to the property that its output is connected to a digital circuit. In recent years, the degree of integration of LSIs including such analog / digital mixed LSIs has been dramatically improved, and accordingly, an increase in power consumption per chip has become a problem.

The present invention particularly includes a plurality of comparators in order to reduce the power consumption of the A / D converter and to reduce noise generated from the A / D converter. In an A / D converter for converting the analog input value to a digital value, at least one of the comparators is provided with a comparison operation stop switch. By providing the comparison operation stop switch in this way, the operation time of the comparison operation of the comparator including the comparison operation stop switch can be shifted compared to the comparison operation of the other comparators.

Therefore, A / A having a plurality of comparators
In the D converter, the operation timing of the specific comparator can be deliberately shifted to reduce the number of the comparators operating simultaneously, and the peak power consumption of the entire A / D converter due to the power consumption of the comparators operating simultaneously can be reduced. It is possible to reduce the value. In addition, by reducing the number of the comparators that operate at the same time, it is possible to reduce the noise peak generated due to the comparison operation of the comparators.

The A / D converter to be applied to the present invention may be any one provided with a plurality of comparators.
This is not particularly limited. However, the effects of the present invention are more conspicuous with respect to, for example, the chopper-type comparator and the switching comparator of the first invention, in which the current consumption is concentrated or the current consumption fluctuates during the comparison operation. It is exhibited in.

The invention does not specifically limit the specific ON / OFF timing of the comparison operation stop switch. The comparison operation timing of at least some of the comparison operations of the plurality of comparators is shifted. Just do it. However, if the comparison operation of the comparator provided with the comparison operation switch is started according to the output of another comparator that determines the digital value of the higher-order bit than the comparator, for example, the third embodiment described later As in the example, it is possible to reduce the number of the comparators that actually perform the comparison operation until the digital value obtained by A / D conversion of the analog input value is determined, and to reduce the power consumption until the A / D conversion is completed. Can be reduced. In other words, the comparison operation of a certain comparator can be prevented from being performed at all by the output of the comparator that determines the digital value of the higher-order bit. Therefore, the A / D converter is reduced by the power consumption of the comparator that does not perform the comparison operation. It is possible to reduce the overall power consumption.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a first embodiment and a fourth embodiment to which the first invention is applied, a second embodiment to which the first and second inventions are applied, and furthermore, FIG. FIG. 11 is a circuit diagram of a switching comparator that can be used in the first embodiment and the third embodiment to which the third invention is applied.

FIG. 1 shows the switching comparator to which the first invention is applied.
The configuration of the switching comparator is a configuration of a CMOS inverter, and its power consumption is further reduced. The current consumed by the CMOS inverter mainly flows when the comparator output Cout changes.

In FIG. 1, the switching comparator comprises a P-channel MOS transistor TP,
It comprises an N-channel MOS transistor TN.

The source of the P-channel MOS transistor TP is connected to the power supply V _DD (or VRn), and the drain of the P-channel MOS transistor TP is connected to the comparator output Cout and the drain of the N-channel MOS transistor TN. . That is, the drain of the N-channel MOS transistor TN is connected to the drain of the P-channel MOS transistor TP and also to the comparator output Cout. The source of the N-channel MOS transistor TN is
It is connected to ground GND. The P-channel MO
The gate of the S transistor TP and the N-channel MOS
The gates of the transistors TN are all connected to the comparator input Cin.

The logic threshold value V of the switching comparator having the configuration of the CMOS inverter shown in FIG.
_TH indicates a power supply voltage of V _DD , a threshold value of the P-channel MOS transistor TP of V _TP ,
Assuming that the threshold value of the transistor TN is V _TN , it can be expressed by the following equation.

V _TH = {V _DD + V _TN · β _R ^1/2 − | V _TP |} / {1 + β _R ^1/2 } (1)

[0040] In the above equation (1), beta _R is the ratio of the amplification factor beta _N and amplification factor beta _P of the P-channel MOS transistor TP of the N-channel MOS transistor TN, are as follows is there.

Β _R = β _N / β _P (2)

The N-channel MOS transistor T
Amplification factor beta _P amplification factor beta _N and the P-channel MOS transistor TP of N are all can be calculated by the equation for determining the amplification factor of the formula beta.

Β = μ · C _ox · W / L (3)

In the above equation (3), μ is the carrier mobility, _Cox is the gate capacitance of the MOS transistor, W is its gate width, and L is its gate length.

As shown in the equations (1) to (3), the logical threshold value of the switching comparator using the CMOS inverter shown in FIG. 1 is listed next to the circuit shown in FIG. It is possible to set by adjusting such circuit parameters.

(1) Adjustment of the power supply voltage V _DD (see equation (1)) (2) Adjustment of the threshold value V _TN of the N-channel MOS transistor TN or adjustment of the threshold value V _TP of the P-channel MOS transistor TP (3) by adjusting at least one of the gate capacitance _Cox , the gate width W, and the gate length L of the N-channel MOS transistor TN. (See equations (1) to (3) above) (4) At least one of the adjustment of the gate capacitance _Cox , the adjustment of the gate width W, or the adjustment of the gate length L of the P-channel MOS transistor TP. With one adjustment (see the above equations (1) to (3))

As described above, according to the switching comparator using the CMOS inverter as shown in FIG. 1, according to the comparator input Cin and the predetermined logical threshold V _TH ,
That is, the P-channel MOS transistor TP and the N
The comparator output Cout can be output by the channel MOS transistor TN. Further, as described with reference to the expressions (1) to (3), the logical threshold value V _TH can be set within a range that the analog input value Ain input from the comparator input Cin can take. FIG. 1
The operation speed of the CMOS inverter as shown in FIG. Therefore,
According to the first switching comparator, it is possible to provide a comparator which can be used also for an A / D converter capable of high-speed A / D conversion. Further, a CMOS inverter as shown in FIG.
In particular, the power consumption is low, and especially the comparator input Cin
When the signal being input to is in a steady state, its power consumption is almost zero.

It is to be noted that the switching comparator according to the present invention is the same as the CMOS shown in FIG.
The present invention is not limited to the inverter, and may be a CMOS logic gate having another circuit configuration, such as the TTL logic gate, the DTL logic gate, or the ECL.
It may be a logic gate or the like. Alternatively, M of an enhancement-depletion (ED) configuration as shown in FIG.
It may be an OS logic gate (inverter).

The MOS inverter shown in FIG.
The N-channel MOS transistor TND is used as an enhancement transistor, and the N-channel MOS transistor TNL is
This is used as a load device that is a depletion transistor whose gate and source are short-circuited. As shown in FIG.
The logical threshold value V _TH of the OS inverter is obtained by setting the threshold value of the N-channel MOS transistor TND to V _TND ,
Assuming that the threshold value of the channel MOS transistor TNL is V _TNL , it can be expressed by the following equation.

V _TH = {V _TND · β _R ^1/2 − | V _TNL |} / {1 + β _R ^1/2 } (4)

In the above equation (4), β _R is the amplification factor β _ND of the N-channel MOS transistor TND,
The amplification factor β _NL of the N-channel MOS transistor TNL
And is as follows:

Β _R = β _ND / β _NL (5)

It should be noted that the amplification factor β _ND of the N-channel MOS transistor TND and the amplification factor β _NL of the N-channel MOS transistor TNL shown in the above equation (5)
Can be calculated by the equation (3) for obtaining the amplification factor β.

FIGS. 3 and 4 show the entire switching comparator shown in FIG. 1 or the entire switching comparator shown in FIG. 2 and are used in FIGS. 7 to 10 and FIG. It is a diagram showing a symbol.

FIG. 3 shows the switching comparators denoted by reference symbol Cn. Further, the comparator input Cin, the comparator output Cout, the power supply V _DD (or VRn).
) And the ground GND. On the other hand, FIG. 4 does not show the power supply _VDD and the ground GND, and shows the comparator input Cin and the comparator output Cout of the comparator Cn.

FIG. 5 is a circuit diagram of a power supply circuit for generating a plurality of power supplies having different voltages supplied to the plurality of comparators of the first to third embodiments.

In FIG. 5, the power supply circuit includes a total of 256 resistance elements R0 to R255 and a total of 255 power supply buffers B1 to B255.

A total of 256 resistance elements R0 to R25
5 are connected in series in order. Terminal VR at the both ends
A predetermined reference voltage Vs is applied between T and the terminal VRB. The terminal VRT is connected to the plus of the reference voltage Vs, and the terminal VRB is connected to the reference voltage Vs.
Minus is connected. Further, a total of 255 comparison reference voltages V1 to V255 are extracted from a total of 255 series connection points of a total of 256 resistance elements R0 to R255 having the same resistance value.

A total of 255 power supply buffers B1 to B
255 respectively include the comparison reference voltages V1 to V255.
Is entered. These power buffers B1 to B255
Are supply power sources VR1 to VR of voltages corresponding to the comparison reference voltages V1 to V255 input thereto, respectively.
255 is output. These power supplies VR1 to VR255
Is supplied as power to each of a total of 255 switching comparators C1 to C255 described below, which are used in the first to third embodiments, respectively. These power supply buffers B1 to B255 are constant voltage power supplies that output the supply power supplies VR1 to VR255, respectively, according to the comparison reference voltages V1 to V255 input thereto.

FIG. 6 is a circuit diagram of a first example of the power supply buffer used in the power supply circuit.

FIG. 6 shows one power supply buffer Bn having a total of 255 power supply buffers B1 to B255 shown in FIG. The power supply buffer Bn has a buffer 30n which is a differential amplifier having a positive input and a negative input, and outputs a power supply of a voltage according to a voltage difference between the positive input and the negative input. In the buffer 30n, the comparison reference voltage Vn is input to the plus input, and the output is the power supply VRn. In the buffer 30n, the output voltage of the supply power supply VRn is negatively fed back to its negative terminal. Therefore, the power supply buffer Bn shown in FIG.
The power supply VRn is supplied at a voltage equal to n.

FIG. 7 is a circuit diagram of a second example of the power supply buffer used in the power supply circuit.

In FIG. 7, the power supply buffer Bn is
It is composed of a buffer 30n and an inverter 32n.

The buffer 30n is the same as the buffer 30n described with reference to FIG. The buffer 3
The inverter 32n is inserted in the negative feedback loop 0n. The input and output of the inverter 32n are shorted and connected to the negative input of the buffer 30n. The power supply VRn output from the buffer 30n is supplied to the power supply of the inverter 32n. Since the input and output of the inverter 32n are connected, the voltage of the output of the inverter 32n becomes the logical threshold voltage V _{TH of the} inverter 32n. Therefore,
The logic threshold voltage V _{TH of the} inverter 32n when the voltage of the power supply VRn is supplied to the inverter 32n is supplied to the minus input of the buffer 30n.

[0065] Thus, in the power buffer Bn shown in FIG. 7, the comparison reference voltage Vn, the relationship between the logic threshold voltage V _TH of the inverter 32n becomes as follows.

Vn = _VTH (6)

[0067] In the switching comparator shown the switching comparator and FIG 2 shown in FIG. 1, the said logic threshold V _TH, the power supply V
By supplying Rn, it is set to be equal to Vn, and it is possible to prevent variations in the logical threshold value of the inverter due to variations in circuit parameters. Therefore, variations in various operations due to variations in circuit parameters can be suppressed.

FIG. 8 is an overall circuit diagram of the A / D converter of the first embodiment to which the first invention is applied.

Referring to FIG. 8, a total of 255 switching comparators C1 to C255 used in the A / D converter 1 are the ones to which the first invention described above with reference to FIG. 1 is applied. I have. A
The overall configuration of the / D converter 1 is a flash type A / D converter that A / D converts an analog input value Ain into 8-bit digital values D1 to D8.

The A / D converter 1 mainly includes a total of 255 switching comparators C1 to C25.
5 and the encoder 2.

Each of the 255 switching comparators C1 to C255 is supplied as a power source with the power sources VR1 to VR255 output from the power source circuit described above with reference to FIG. 5 and having different voltages. . These switching comparators C1 to C25
5 has the same circuit, and the voltages of the supplied power supplies VR1 to VR255 are different from each other. Further, since the respective supply powers VR1 to VR255 supplied in this way are different from each other, these switching comparators C1 to C255
Respective threshold V _TH1 ~V _TH255 of has a mutually different values.

The total of 255 switching comparators C1 to C255 are respectively connected to thresholds V _TH1 to V _TH1 .
_They are arranged in parallel in ascending order of the value of V _TH255 . or,
These threshold values V _{TH1 to} V _TH255 are defined as the range that the analog input value Ain can take, that is, the range between the lower limit value Amin and the upper limit value Amax of the analog input value Ain (hereinafter referred to as full scale). 8-bit resolution of digital values D1 to D8 output from the A / D converter 1 (2 ⁸ =
256). For example,
The threshold value V _{THn of} the n-th switching comparator Cn
Is as shown in the following equation (n is from “1” to “25”).
5 "integer).

V _THn = Amin + n × (Amax−Amin) / 256 (7)

In the first embodiment, the threshold V _TH1 of each of the switching comparators C1 to C255 is set.
To V _TH255 are mainly supplied to the power supplies VR1 to VR supplied to the switching comparators C1 to C255.
It is set by a voltage of 255. However, the threshold values V _{TH1 to} V _TH255 of each of the switching comparators C1 to C255 may be set by other means. For example, the threshold values V _{TH1 to} V _TH255 of each of the switching comparators C1 to _C255 may be, for example, the P channel MOS transistor TP and the N
It may be set by the gate width W and the gate length L of the channel MOS transistor TN ((1) above).
Equations (3) to (3)).

In this manner, the threshold values V _{TH1 to} V _TH255
The analog input value Ain held by an input buffer (not shown) or a sample and hold circuit (not shown) is input to the comparator inputs Cin of all the switching comparators C1 to C255 in which is set respectively. In addition, these switching comparators C1 to C1
The respective comparator output Cout of C255 is:
It is input to the encoder 2 independently.

The switching comparator C1
To C255, the analog input value Ain input to the comparator input Cin corresponds to the threshold V
If it is smaller than _{TH1 to VTH255} , each of the comparator outputs Cout outputs a logical value "1". On the other hand, each of these switching comparators C1 to C255, when the input analog input value Ain is larger than each of the thresholds V _{TH1 to} V _TH255 ,
A logical value "0" is output from each of the comparator outputs Cout.

The encoder 2 is connected to the switching comparators C1 to C255, which are input independently.
Is binary-coded into an 8-bit binary number, and digital values D1 to D8 are output.

For example, when the analog input value Ain is the lower limit value Amin, the switching comparator C1
To C255 are all "1".
The encoder 2 converts this into a binary code, and the digital values D1 to D8 are all "0".
When the analog input Ain has the value of the upper limit value Amax, the comparator outputs Cout of the switching comparators C1 to C255 are all "0", and the encoder 2 converts the digital value into a binary code, and outputs the digital values D1 to D8. Are all "1". The magnitude of the analog input value Ain is different from the lower limit value Amin and the upper limit value Ama.
x, when the analog input value Ain increases, the switching comparators C1 to C2
55, the output of each of the comparator outputs Cout sequentially becomes "0" from the switching comparator C1 side to the switching comparator C255 side.
Outputs “1”.

For example, when the analog input value Ain is a certain value, a total of 23 switching comparators C1 to C23 output a logical value “0” corresponding to the value, and the other switching comparators C24 to C24 output a logical value “0”. C25
5 outputs a logical value "1". At this time, the encoder 2 is connected to the switching comparators C1 and C2.
The output of 55 such logical values is coded and the digital values D1 to D8 as shown in the following equations are output.

D8 = D7 = D6 = D4 = 0 (8a) D5 = D3 = D2 = D1 = 1 (8b)

That is, the digital values D1 to D8 represented by the above equations (8a) and (8b) are expressed as "00" in binary.
010111 "and" 23 "in decimal.

As described above, according to the first embodiment, the threshold values V _{TH1 to} V _TH255 of the 255 switching comparators C1 to C255 to which the first invention is applied are different from each other. The value can be set as shown in the above equation (7), and a flash A / D converter can be configured. These switching comparators C1 to C255 can perform higher-speed comparison operation in addition to the comparator using the differential amplifier and the chopper-type comparator. Therefore, according to the first embodiment, the conversion speed of the flash A / D converter capable of high-speed A / D conversion can be further improved. Further, the switching comparators C1 to C255 can be downsized as compared with the comparator using the differential amplifier or the chopper type comparator. Therefore, according to the first embodiment, the entire A / D converter 1 is used. Occupied area can be reduced, and the degree of integration can be improved.

According to the estimations of the present inventors, the occupied area of the A / D converter of the first embodiment is 1 / compared to the A / D converter of the same number of bits using the conventional chopper type comparator. It can be reduced to about 2, and the A / D conversion speed can be expected to be improved to about 5 to 10 times.

FIG. 9 is an overall circuit diagram of the A / D converter of the second embodiment to which the first invention and the second invention are applied.

The second embodiment shown in FIG. 9 employs a total of 255 switching comparators Cn shown in FIG. 1 to which the first invention is applied. In addition, the A / D converter 1 has the above-described embodiment applied as an entire configuration, and improvements such as reduction in power consumption fluctuation and noise reduction of the conventional flash A / D converter have been made. Things.

The A / D converter 1 of the second embodiment
Is mainly composed of a total of 255 switching comparators C1 to C255, a total of 254 N-channel MOS transistors T1 to T254 corresponding to the comparison operation stop switch element of the second invention, and an encoder 2. I have. The switching comparators C1 to C255 and the encoder 2 used in the second embodiment are the same as those of the first embodiment described above with reference to FIG. And performs the same operation. The switching power supplies V are respectively provided to the switching comparators C1 to C255.
R1 to VR255 are supplied, so that these switching comparators C1 to C255 are cascaded in the order of the threshold value.

The feature of the second embodiment is that the comparator input C of each of a total of 254 switching comparators C1 to C254 is different from the first embodiment.
n and the terminal of the analog input value Ain, respectively, the N-channel MOS transistors T1 to T254
Are connected in series for each source and drain. The gates of the N-channel MOS transistors T1 to T254 are connected to the comparator outputs Cout of the switching comparators C2 to C255 shown one above each in FIG. For example, the n-th N
Regarding the channel MOS transistor Tn, the (n +
1) The switching comparator C (n + 1)
Of the comparator Cout.

Therefore, in the second embodiment, since the cascade connection is performed as described above, the output of the (n + 1) th switching comparator C (n + 1) is logically connected to the nth switching comparator Cn. Value "1"
That is, when the magnitude of the analog input value Ain is equal to the (n + 1) -th switching comparator C (n +
Only when it is smaller than the threshold value V _{TH (n + 1) of 1)} ,
When the n-th N-channel MOS transistor Tn is turned on, it is driven. Therefore, in the second embodiment, the n-th switching comparator C
The comparison operation of n is performed at least after the comparison operation of the (n + 1) -th switching comparator C (n + 1) is completed, and a total of 255 switching comparators C1 to C255 operate. These operation timings are determined by the threshold values V _{TH1 to} V _TH255.
It becomes the order of bigger. The comparison operation is sequentially performed in a plurality of stages at least by shifting the operation time by a very short time.

Therefore, the through current of the switching comparators C1 to C255 in the CMOS inverter configuration does not concentrate at one time, the peak current value of the power supply current due to the through current is suppressed, the fluctuation of the power supply voltage is reduced, and the power supply voltage is reduced. Noise can be reduced. Also, depending on the value of the analog input value Ain, only the required number of switching comparators C1 to C255 are compared, and the average power consumption of the A / D converter 1 can be reduced. It is possible.

In the second embodiment, even if the comparison operations of the switching comparators C1 to C255 are sequentially performed as described above, the comparison operations of the switching comparators C1 to C255 must be performed at high speed. , The A / D converter 1
There is no significant delay in the processing speed of the entire / D conversion.

In the second embodiment, when the n-th switching comparator Cn determines that the magnitude of the analog input value Ain is larger than the threshold value V _THn , the other switching thereafter. The comparison operation of the comparators C1 to C (n-1) is not performed, and the comparator output Cout of these switching comparators C1 to C (n-1) becomes indefinite. Therefore, the encoder 2 takes this point into consideration. That is, in the encoder 2, the output of the (n + 1) th switching comparator C (n + 1) is a logical value "1".
And the output of the n-th switching comparator Cn next to this has a logical value "0". Thus, the logical value "1" and the logical value "0" are the most The one on the switching comparator C255 side (the side opposite the switching comparator C1) is determined, and based on this, the 8-bit digital values D1 to D8 are coded.

FIG. 10 is an overall circuit diagram of the A / D converter of the third embodiment to which the first invention and the third invention are applied.

A of the third embodiment shown in FIG.
The / D converter 1 is the switching comparator C to which the first invention is applied as described above with reference to FIG.
n are provided in total. In the third embodiment, the overall configuration is a 3-bit flash A / D converter to which the third invention is applied. The A / D converter converts the analog input Ain into the 3-bit digital values D1 to D3.

The A / D converter 1 of the third embodiment is
Mainly, a total of seven switching comparators C
1 to C7, encoder 2, and a total of seven N channels M
It comprises OS transistors T1 to T7 and a total of three inverters 3 to 5.

The switching comparators C1 to C7
The power supplies VR1 to VR7 generated by the power supply circuit shown in FIG. The power supply circuit used in the third embodiment shown in FIG. 11 is composed of a total of eight resistance elements R0 to R7 having the same resistance value and a total of seven power supply buffers B1 to B7. The power supply buffers B1 to B7 are the same as those shown in FIG. 5, and either one shown in FIG. 6 or one shown in FIG. 7 is used.

In FIG. 10, a total of seven switching comparators C1 to C7 have the same internal circuit as shown in FIG.
Also, the integrated circuit layout patterns are the same as each other. On the other hand, these switching comparators C
The supply power sources VR1 to VR7 supplied from the power supply circuit described above with reference to FIG.
A power supply of VR7 having different voltages from each other is supplied. For this reason, the threshold values V _{TH1 to} V _TH1 of each of the seven switching comparators C1 to C7 are used.
_TH7 has different values. The threshold value V _THn of the n-th switching comparator Cn can be expressed by the following equation (n is an integer from “1” to “7”).

V _THn = Amin + n × (Amax−Amin) / 8 (9)

In FIG. 10, the analog input value Ain is input to the comparator input Cin of the switching comparator C4. The N-channel MOS transistors T1 to T3 and T5 are sequentially connected between the comparator input Cin of each of the six switching comparators C1 to C3 and C5 to C7 and the terminal of the analog input value Ain. To T7 are connected in series for each source and drain.

The output of the switching comparator C4 whose threshold value V _TH4 is half the full scale of the lower limit value Amin and the upper limit value Amax is connected to the gate of the N-channel MOS transistor T2. And the input of the inverter 3 are connected. The output of the inverter 3 is connected to the gate of the N-channel MOS transistor T6. Therefore, when the value of the analog input value Ain is smaller than the threshold value V _TH4 , the switching comparator C2 performs a comparison operation. On the other hand, when the value of the analog input value Ain is larger than the threshold value V _TH4 , the switching comparator C6 performs a comparison operation.

Further, the switching comparator C2
Is connected to the gate of the N-channel MOS transistor T1 and the input of the inverter 4.
The output of the inverter 4 is connected to the gate of the N-channel MOS transistor T3. Therefore, when the value of the analog input value Ain is smaller than the threshold value V _TH2 , the switching comparator C1 performs a comparison operation. On the other hand, when the analog input value Ain is equal to the threshold V
If it is greater than _TH2 , the switching comparator C3 performs a comparison operation.

On the other hand, the switching comparator C6
, The output of which is connected to the gate of the N-channel MOS transistor T5 and the input of the inverter 5. The output of the inverter 5 is connected to the gate of the N-channel MOS transistor T7.
Therefore, the value of the analog input value Ain is equal to the threshold value V _TH6.
If it is smaller, the switching comparator C5 performs a comparison operation. On the other hand, the analog input value Ain
Is larger than the threshold value V _TH6 , the switching comparator C7 performs a comparison operation.

The encoder 2 converts the inverted value of the output of the switching comparator C4 into the most significant bit (MSB).
The digital value is D3 of the ficant bit). That is, when the logical value of the output of the switching comparator C4 is "1", the logical value of the digital value D3 is "0", and when the logical value of the output of the switching inverter C4 is "0", the digital value is The logical value of D3 is "1".

When the logical value of the output of the switching comparator C4 is "1", the encoder 2 outputs the inverted value of the output of the switching comparator C2 as the logical value of the digital value D2. On the other hand, when the logical value of the output of the switching comparator C4 is “0”, the inverted value of the output of the switching comparator C6 is set as the logical value of the digital value D2.

Further, when the logical value of the output of the switching comparator C4 is "1" and the logical value of the output of the switching comparator C2 is also "1", the encoder 2 outputs the signal of the switching comparator C1. The inverted value of the output is set to LSB (least significant bi
The digital value D1 in t) is used. The logic value of the output of the switching comparator C4 is "1",
When the logical value of the output of the switching comparator C2 is "0", the inverted value of the output of the switching comparator C3 is replaced with the digital value D1 of LSB.
Logical value.

On the other hand, when the logical value of the output of the switching comparator C4 is "0" and the logical value of the output of the switching comparator C6 is "1", the encoder 2 outputs the signal of the switching comparator C5. The inverted value of the output is the logical value of the digital value D1 of LSB. When the logical value of the output of the switching comparator C4 is "0" and the logical value of the output of the switching comparator C6 is also "0", the inverted value of the output of the switching comparator C7 is calculated as LSB. Of the digital value D1.

In the A / D converter according to the third embodiment, the switching comparators C1 to C
3, N-channel MOS transistors T1 to T3 and T5 to T7 corresponding to the comparison operation stop switch of the third invention are provided in each of C5 to C7. or,
In the third embodiment, the N-channel MOS transistors T1 to T3, T
5 to T7 are digital values D determined by the corresponding comparators C1 to C3 and C5 to C7, respectively.
1, other switching comparators C2, C4, C6 for determining digital values D2 to D3 of higher bits than D2
It operates according to the output of For this reason, after the analog input value Ain is supplied, the digital values D1 to D1 are finally obtained.
In the period until each value of D3 is determined,
The comparator that performs the comparison operation is the analog input value Ain of the seven switching comparators C1 to C7 in total.
There are only three predetermined totals determined according to.

That is, immediately after the analog input value Ain is input, first, the switching comparator C4
Only the comparison operation is performed. In the second stage, only one of the switching comparators C2 and C6 performs the comparison operation. In the subsequent third stage, only one of the switching comparators C1, C3, C5 and C7 performs the comparison operation. By the operation of only three of the switching comparators C1 to C7 in the first to third stages,
The values of the digital values D1 to D3 are determined.

As described above, according to the third embodiment, at the time of A / D conversion of the analog input value Ain, only a total of three switching comparators C1 to C7 perform a comparison operation. Power consumption can be reduced. Further, the switching comparator C
Of the three units 1 to C7, those that perform the comparison operation also do not perform the comparison operation at the same time, and their operation timings are shifted by a very short time. Therefore, the peak value of the current consumption in the third embodiment is suppressed, the fluctuation amount of the current consumption is reduced, and the power supply noise is reduced accordingly. Even if the operation time of the comparison operation is shifted as described above, the comparison operation of the switching comparators C1 to C7 is performed at a relatively high speed, so that it is necessary for the A / D conversion of the entire A / D converter 1. The processing time is not unnecessarily extended.

FIG. 12 is a circuit diagram of an A / D converter according to the fourth embodiment to which the first invention is applied.

A of the fourth embodiment shown in FIG.
The / D converter 1 includes a switching comparator 10 composed of a total of m P-channel MOS transistors P1 to Pm and a total of one N-channel MOS transistor N1. The switching comparator 10
Is a configuration of a CMOS inverter, to which the first invention is applied.

The A / D converter 1 includes a switching comparator 10 and a variable threshold switch group ST composed of a total of m N-channel MOS transistors ST1 to STm, a controller 11, and an inverter 12. It is configured.

In the switching comparator 10 of the fourth embodiment, a total of m P-channel MOS
All the transistors P1 to Pm have their sources connected to the power supply V _DD , their drains connected to the comparator output Cout, and their drains also connected to the drain of the N-channel MOS transistor N1. . The gates of the P-channel MOS transistors P1 to Pn are connected to the N-channel MOS transistors corresponding to the respective ones in the threshold variable switch group ST.
The transistors ST1 to STm are connected to the comparator input Cin via the source-drain.

Therefore, for example, when the N-channel MOS transistor ST1 is turned on, the P-channel MOS transistor ST1 is turned on.
The gate of the transistor P1 is connected to the comparator input Cin.
Becomes conductive. When the N-channel MOS transistor ST2 is turned on, for example, the P-channel MOS transistor ST2 is turned on.
The gate of the S transistor P2 is connected to the comparator input C
It becomes conductive state in.

On the other hand, in the switching comparator 10, the drain of the N-channel MOS transistor N1 is connected to all the sources of the P-channel MOS transistors P1 to Pm, and also connected to the comparator output Cout. I have. The source of the N-channel MOS transistor N1 is connected to the ground GND, and the gate is connected to the comparator input Cin.

The switching comparator 10 according to the fourth embodiment includes the individual N-channel MOS transistors ST1 to ST of the variable threshold switch group ST.
By turning on and off m, a total of m P-channel MOs
Any one of the gates of the S transistors P1 to Pm can be selectively made conductive to the comparator input Cin. Thus, the number of the P-channel MOS transistors P1 to Pm connected to the comparator input Cin of each gate can be changed.

Therefore, in the switching comparator 10, the threshold variable switch group ST
N-channel MOS transistors ST1 to ST1
By turning on and off STm, the logical threshold value V _TH of the switching comparator 10 can be changed. This is because a total of n P-channel MOS transistors P1 to P1 connected in parallel with respect to the source and the drain
If Pn is assumed to be a complex single P-channel MOS transistor P, the element parameters of the P-channel MOS transistor P change by turning on and off the individual N-channel MOS transistors ST1 to STn of the variable threshold switch group ST. It can be thought that it is done. For example, it can be considered that the virtual gate width W is changed in the P-channel MOS transistor P.

According to the switching comparator 10, the desired logical threshold V _TH is set by turning on and off the individual N-channel MOS transistors ST1 to STm in the variable threshold switch group ST by the controller 11. can do. Further, the switching comparator 10 can compare the logical threshold value V _TH with the analog input value Ain.

In the A / D converter 1 of the fourth embodiment, a total of one switching comparator 10
Is input to the controller 11 via the waveform shaping inverter 12. The controller 1
1 turns on / off the individual N-channel MOS transistors ST1 to STn of the threshold variable switch group ST in response to the input from the inverter 12, and the like.
During this time, the digital output Dout outputs MSB to LSB.
, The digital values D1 to D3 are output. For example, the operation of the controller 11 can be the operation of a conventional successive approximation A / D converter or the operation of a conventional tracking comparison A / D converter.

For example, when the operation of the A / D converter 1 is the operation of the successive approximation type A / D converter by the controller 11, first, as a first step,
The N of the variable threshold switch group ST is set so that the switching comparator 10 can compare the analog input value Ain with the analog input value Ain at the logical threshold value V _{TH which is}の of the full scale of the analog input value Ain. Channel MO
The individual S transistors ST1 to STn are turned on and off individually. Based on the comparison result of the switching comparator 10 at this time, that is, based on the digital output Dout, the controller 11 determines the M of the digital values D1 to Dn.
SB can be obtained.

Next, as a second step, based on the comparison result of the first step, the controller 11 sets the threshold V _TH of the switching comparator 10 to a value of １ ／ of the full scale, 3/4 of the full scale
The threshold VTH of the switching comparator 10 is set by _turning on and off the variable threshold switch group ST based on the determination. Further, the comparison result of the switching comparator 10 based on the threshold value V _TH set in this way is the digital value D1.
Are output from the digital output Dout as logical values of the second bit from the MSB of .about.Dn.

The same processing is performed for the third and subsequent steps. During such a series of processing, a total of three logical values sequentially output from the digital output value Dout provide MS
The digital values D1 to D3 of the A / D conversion result of the analog input value Ain can be obtained from B to LSB.

As described above, according to the fourth embodiment, the A / D conversion of the analog input value Ain can be performed by only one switching comparator 10.
The number of required elements can be reduced, and the degree of integration can be improved. In addition, the switching comparator 1
A value of 0 enables high-speed operation as compared with a conventional comparator. Therefore, the A / D converter 1 of the fourth embodiment is
Can achieve higher speed than the conventional successive approximation type A / D converter and the conventional follow-up comparison type A / D converter.

In the fourth embodiment, the switching comparator 10 having a CMOS inverter configuration is used.
The P-channel MOS transistor P connected to the power supply V _DD side is operated by the variable threshold switch group ST to change the logical threshold V _TH . However, the N-channel MOS transistor N1 is
It is also possible to compose a complex structure using a large number of N-channel MOS transistors and switch the same with the same one as the threshold variable switch group ST, thereby changing the logical threshold V _TH . Alternatively, the P-channel M of the switching comparator 10 having a CMOS inverter configuration
Both the OS transistor and the N-channel MOS transistor may be combined.

Note that the first to third embodiments described above are used.
In the embodiment, the switching comparators C1 to C1
When each output of C255 is input to the encoder 2, one or more waveform shaping inverters may be provided in this path. Thereby, the encoder 2
Can be performed more stably.

In the second and third embodiments, the switching comparator to which the first invention is applied is used. However, in the second and third embodiments, other comparators, such as the chopper type comparator and the comparator using the differential amplifier, may be used.

In the first to fourth embodiments, the switching comparator having the CMOS inverter configuration described with reference to FIG. 1 is used. However, the switching comparator having another configuration, for example, the switching comparator shown in FIG. A configuration using an ED type MOS inverter as shown in FIG. 2 may be used.

[0127]

As described above, according to the first aspect of the present invention, it is possible to further reduce the size and to achieve a high speed A / A
An excellent effect that an A / D converter capable of D conversion can be provided can be obtained. In addition, the second
According to the invention and the third invention, it is excellent that an A / D converter capable of suppressing the peak value of the fluctuation of the current consumption and reducing the power supply noise accompanying the fluctuation of the current consumption can be provided. The effect can be obtained.

[Brief description of the drawings]

FIG. 1 is a first embodiment to which the first invention of the present application is applied, second and third embodiments to which the first and second inventions of the present application are applied, respectively, and the first invention to which the first invention is applied. Circuit diagram of a switching comparator used in the A / D converter of the fourth embodiment

FIG. 2 is a circuit diagram of a modification of the switching comparator.

FIG. 3 is a first symbol diagram showing the switching comparator;

FIG. 4 is a second symbol diagram showing the switching comparator;

FIG. 5 is a circuit diagram of a power supply circuit used in the first embodiment and the second embodiment.

FIG. 6 shows a first example of a power supply buffer used in the power supply circuit.
Circuit diagram showing an example

FIG. 7 shows a second power supply buffer used in the power supply circuit.
Circuit diagram showing an example

FIG. 8 is an overall circuit diagram of the A / D converter of the first embodiment.

FIG. 9 is an overall circuit diagram of an A / D converter according to the second embodiment.

FIG. 10 is an overall circuit diagram of an A / D converter according to the third embodiment.

FIG. 11 is a circuit diagram of a power supply circuit used in the third embodiment.

FIG. 12 is an overall circuit diagram of an A / D converter according to the fourth embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... A / D converter 2 ... Encoder 10, Cn, C1-C255 ... Switching comparator 12 ... Inverter 30n ... Buffer (differential amplifier) 32n ... Analog inverter Ain ... Analog input value Bn ... Power supply buffer Cin ... Comparator input Cout ... Comparator Outputs D1 to D8: Digital values R0 to R255: Resistors SR1 to SRn: N-channel MOS transistors (variable threshold switching elements) TN, TND: N-channel MOS transistors (switching active elements) TNL: N-channel MOS transistors (load devices) TP, P1 to Pm: P-channel MOS transistors (switching active elements) T1 to T254: N-channel MOS transistors (comparison operation stop switch) V1 to V255: comparison reference voltage VR1 to VR255 Power supply of the switch ring comparator

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiroshi Ogasawara 2-3-2 Uchisaiwai-cho, Chiyoda-ku, Tokyo Kawasaki Steel Corporation Tokyo Head Office (56) References JP-A-56-58323 (JP, A) JP-A JP-A-58-81327 (JP, A) JP-A-3-186018 (JP, A) JP-A-1-95831 (JP, U) JP-B-61-2337 (JP, B2)

Claims (3)

(57) [Claims] 1. A converter for converting an analog input value into a digital value
In the / D converter, a voltage corresponding to a voltage difference between a positive input and a negative input is output, a voltage corresponding to a magnitude of a comparison reference voltage of a switching comparator is input to the positive input, and an output of the switching comparator is output. A power supply buffer composed of a differential amplifier used for a power supply, and an input and an output short-circuited and connected to the minus input of the differential amplifier, and a power supply including an inverter supplied with the power supply. In accordance with a comparator input and a predetermined logic threshold, a switching active element outputs a comparator output, and
The power supply is provided with at least one switching comparator whose logical threshold value is set within a range that the analog input value can take when the power supply is supplied, and the analog input value is introduced to the comparator input. And the digital value is determined based on the output of the comparator.
D converter. 2. An A / D converter comprising a plurality of comparators, each receiving an analog input and comparing with an internally set or an externally set mutually different threshold value, wherein a comparator input of at least one of the comparators and the analog input And a cascade connection in the order of the thresholds so that the on / off of the comparison operation stop switch is operated according to the output of another comparator. The comparison operation stop switch is not provided sequentially. A, by operating a plurality of comparators in a plurality of stages including at least one of the plurality of comparators, the operation timing of at least some of the plurality of comparators is shifted.
/ D converter. 3. An A / D converter comprising a plurality of comparators each receiving an analog input and comparing with different thresholds set internally or externally, wherein a digital value of the same bit among the comparators is calculated. A comparison operation stop switch is provided between a comparator input of each of at least one set of comparators and the analog input, wherein a pair of the two to be determined is paired. By sequentially operating a plurality of comparators including those without the comparison operation stop switch in a plurality of stages in accordance with the outputs of other comparators that determine the digital value of the upper bit common to these comparators, Stagger the operation of at least some of them A / D converter, characterized in that there was Unishi.