JP2853630B2 - Memory cell circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a CMOS (Complementary MOS) and Bi-CMOS.
(Bipolar-CMOS) relates to a memory circuit.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration of a conventional memory cell circuit. Referring to FIG. 3, this conventional memory cell circuit includes first, second, and third inverter circuits 1, 2, 3,.
And N-channel MO acting as transfer gate
It comprises S transistors QT1, QT2, and QT3.

A first inverter circuit 1 includes a P-channel MOS connected in series between a power supply VDD and a ground GND.
Transistor Q1 and N-channel MOS transistor Q2
, Whose input terminal is a gate commonly connected to P-channel MOS transistor Q1 and N-channel MOS transistor Q2, and whose output terminal is a P-channel MOS transistor Q2.
1 and a common connection point between the drains of the N-channel MOS transistor Q2.

Similarly, the second inverter circuit 2 includes a P-channel MOS transistor Q3 and an N-channel MOS transistor Q4.

The first and second inverter circuits 1 and 2 each have an output terminal of one of the inverter circuits connected to an input terminal of the other inverter circuit, and have nodes (also referred to as "memory holding nodes") N1 and N2. N2 constitutes a data holding loop. The node N1 indicates a node of a connection point between the output terminal of the first inverter circuit 1 and the input terminal of the second inverter circuit 2, and the node N2 indicates the first inverter circuit 1
2 shows a connection point between the input terminal of the second inverter circuit 2 and the output terminal of the second inverter circuit 2.

For example, if the output of the first inverter circuit 1 is at a low (low) level (the transistor Q2 is in an on state), the input of the second inverter circuit 2 is at a low level, and its output is High ( High) level (transistor Q3 is on). As a result, the input of the first inverter circuit 1 becomes High level, and the output thereof becomes Low level. In this way, data can be held.

[0007] N-channel MOS transistors QT1, QT
T2 is the node N of the data holding loop described above.
1, N2 and a bit line pair BLB / BLB
Are complementary signals), and their gates are commonly connected to a word line (word line for writing) WLB.

Data holding nodes N1, N2 are connected through bit line pair BLB / BLB # and transistors QT1, QT2.
, And these are used as write ports.

Further, similarly, a third inverter circuit 3 is constituted by the P-channel MOS transistor Q5 and the N-channel MOS transistor Q6, and the input terminal of the third inverter circuit 3 is connected to the node of the data holding loop. N2, the output of which is N-channel MO
It is connected to the drain of S transistor QT3.

The source of the transistor QT3 is connected to the read bit line BLA, the gate is connected to the word line (read word line) WLA, and operates as a transfer (transfer) gate.

The data held in the above-described data holding loop is transmitted to the third inverter circuit 3 and the N channel M
The data is read to the bit line BLA via the OS transistor QT3, and is used as a read port.

As described above, the conventional memory cell circuit shown in FIG. 3 constitutes a two-port memory cell capable of one-port read and one-port write.

Note that N channel MOS transistors QT1, QT2, QT in the memory cell circuit shown in FIG.
A similar memory cell circuit can be configured even if part of 3 is replaced with a P-channel MOS transistor.

FIG. 4 shows an example of such a conventional memory cell circuit. The N-channel MOS transistor QT3 shown in FIG.
4 shows the memory cell circuit replaced with No. 4. The remaining configuration and operation of the conventional memory cell circuit shown in FIG. 4 are the same as those of the circuit of FIG.

By the way, in the read operation of the conventional memory cell circuit shown in FIG.
When the h level is output, even if the output of the third inverter circuit 3 has risen to the same potential as the VDD potential, the potential of the BLA corresponds to the threshold voltage (gate threshold) of the transfer gate MOS transistor QT3. Value voltage V _Tn )
(I.e., VDD- _VTn ).

For this reason, when the threshold voltage of the transfer gate MOS transistor QT3 fluctuates due to manufacturing variations or the like, a sufficient High level cannot be transmitted to the bit line BLA. ,
Incorrect data may be read. Similarly, in the conventional memory cell circuit shown in FIG.
When a low level is output to the bit line BLA, the bit line BLA is turned on by the transistor Q with respect to the GND potential.
The level rises by the threshold (V _TP ) voltage of T4.

Further, in the conventional memory cell circuit, the MOS transistors of the first to third inverter circuits 1, 2 and 3 and the transfer gate MOS transistor QT
Since the gate width of No. 3 is selected for the purpose of high integration and large capacity, a value (usually １ ／ or less) which is considerably smaller than the gate widths of MOS transistors of other peripheral circuits is used.

This means that, despite the large load capacitance of the entire bit line, the CMOS inverter circuit with low driving capability drives the entire bit line indirectly via the transfer gate.

Therefore, at the time of the read operation, after the memory cell is selected, the data on the bit line BLA becomes L
The waveform distortion when switching from the low level to the high level (or from the high level to the low level) tends to be larger than the waveform distortion of other peripheral circuits.

[0020]

As described above, in a conventional memory cell circuit, a high or low level is propagated to a bit line via a transfer gate during a read operation. The high level of the bit line is lowered or the Low level is raised by an amount corresponding to the threshold voltage, so that the noise margin is reduced.
There is a problem that the threshold voltage of the OS transistor is greatly affected by manufacturing variations. As a result, in the conventional memory cell circuit, there is a problem that erroneous reading occurs when the noise margin is reduced.

In the conventional memory cell circuit,
Since a CMOS inverter circuit having a low driving capability is configured to indirectly drive a high-load bit line via a transfer gate MOS transistor, the switching of bit line data is also slow. I have. For this reason, it is difficult to realize a high-speed access time of the memory device.

Accordingly, the present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to prevent the amplitude of a bit line from being affected by a variation in a threshold voltage due to a variation in manufacturing of a MOS transistor or the like. By outputting a constant amplitude, it is possible to increase the noise margin, prevent erroneous reading, always guarantee the data of the memory cell correctly, and reduce the waveform distortion at the switching of the bit line pair. To provide a memory cell circuit capable of high-speed operation.

[0023]

In order to achieve the above object, the present invention provides a first and second inverter circuits for connecting an output terminal and an input terminal to each other to form a data holding loop; A first and a second word lines connected between two connection nodes between an input terminal and an output terminal of the second inverter circuit and the first bit line pair, and a first word line commonly connected to a gate. And a control circuit for inputting at least one of the two connection nodes of the first and second inverter circuits and a first word line signal and outputting a predetermined control signal. And a pull-up circuit and a pull-down circuit for directly setting a second bit line to a first or second logic level based on a control signal output from the control circuit. I will provide a

[0024]

The memory cell circuit according to the present invention comprises a data holding loop composed of two inverter circuits, two one-conductivity transistors for write ports connected to both ends of the data holding loop, and a read port. Hig directly to
a high drive capability pull-up circuit for providing an h level, a high drive capability pull-down circuit for directly providing a low level, a control circuit for controlling the pull-up circuit and the pull-down circuit depending on the state of the word line and the data holding node; The bit line for the read port is directly pulled up to the power supply potential or pulled down to the ground potential to be at High level or L level.
By setting the level to the low level, the noise margin of the bit line potential can be increased without receiving a change in the threshold voltage due to manufacturing variations of the MOS transistors.

According to the present invention, the bit line switching time can be reduced by selecting a pull-up circuit and a pull-down circuit having a high load driving capability.

[0026]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1A is a diagram showing a configuration of an embodiment of a memory cell circuit according to the present invention. Referring to FIG. 1A, the memory cell circuit according to the present embodiment differs from the conventional memory cell circuit described with reference to FIGS. MOS for gate
In place of the transistor, a control circuit 6, a pull-up circuit 4, and a pull-down circuit 5 are provided.

That is, the P-channel MOS transistor Q1 and the N-channel MOS transistor Q2 connected in series between the power supply VDD and the ground form the first inverter circuit 1, and the P-channel MOS transistors Q3 and N
The channel MOS transistor Q4 forms a second inverter circuit 2, and includes first and second inverter circuits 1, 2
Are connected to each other (nodes N1,
N2), a data holding loop is formed similarly to the conventional memory cell circuit, and a transfer (transfer) gate is provided between the bit line pair BLB / BLB # and the nodes (also referred to as “storage holding nodes”) N1 and N2. Working N-channel M
OS transistors QT1 and QT2 are inserted, and the gates of MOS transistors QT1 and QT2 share word line W
Connected to LB.

In this embodiment, a bit line pull-up circuit 4 having a high driving capability and a driving capability are provided between a data holding loop composed of the first and second inverter circuits 1 and 2 and the read bit line BLA. And a control circuit 6 for controlling the pull-up circuit 4 and the pull-down circuit 5.

The pull-up circuit 4 is a circuit for pulling up a bit line to a power supply potential VDD, and its output is connected to the bit line BLA. When the pull-up circuit 4 is selected (activated) by a control signal input from the U terminal of the control circuit 6 to the control input terminal, the pull-up circuit 4 becomes High.
It outputs an h level, and enters a high impedance state when not selected, and outputs two logic states according to an input control signal.

The pull-down circuit 5 is a circuit for pulling down the bit line to the ground potential GND. Like the pull-up circuit 4, the output is connected to the bit line BLA. The pull-down circuit 5 outputs a low level when selected (activated) by a control signal input from the D terminal of the control circuit 6 to the control input terminal, and enters a high impedance state when not selected. Outputs two logic states according to the input control signal.

The control circuit 6 includes a pull-up circuit 4
One input terminal (word line input terminal) W is connected to a word line (word line for reading) WLA, and the other input terminal (memory holding node input terminal) N Is connected to the storage node N2. An output terminal U is a pull-up control output terminal for outputting a signal for controlling selection (activation) of the pull-up circuit 4, and an output terminal D is selection (activation) of the pull-down circuit 5.
This is a pull-down control output terminal that outputs a signal for controlling the pull-down control.

The operation of this embodiment will be described below with reference to FIG. FIG. 1B summarizes the relationship between the inputs W and N of the control circuit 6 and the outputs U and D and the logical state of the bit line BLA.

First, in the write operation of the memory cell circuit according to the present embodiment, similarly to the above-mentioned conventional memory cell circuit, the bit line pair BLB / BLB # is supplied with mutually inverted data to act as a transfer gate. By performing writing from both ends N1 and N2 of the storage node of the data holding loop via the transistors QT1 and QT2, the writing is ensured.

The word lines WLB independent of the read word line WLA are connected to the gates of the transistors QT1 and QT2, so that independent one-port writing is possible.

Next, a read operation of the memory cell circuit according to the present embodiment will be described.

The memory holding loop composed of the first and second inverter circuits 1 and 2 is the same as that of the conventional memory cell circuit, and the control circuit 6 determines the next according to the value of the memory holding node N2 and the word line signal WLA. Like 3
It is configured so that different types of operation states are defined.

The first operation state is a case where the potential of the word line WLA is at a level indicating a non-selected state. At this time, regardless of the value of the storage node N2, the pull-up circuit 4 and the pull-down circuit 5, a non-selection signal is output from the output terminals U and D as a control signal, the pull-up circuit 4 and the pull-down circuit 5 are both in a high impedance state, and the memory cell circuit is disconnected from the bit line BLA. You.

In the second operation state, when the potential of the word line WLA is at the selected level, and when the value of the storage node N2 is at the High level, the pull-up circuit 4 is selected (activated) and the pull-down circuit 5 is activated. A control signal that is not selected is output from the output terminals U and D, respectively. That is, at this time, the bit line BLA is forcibly fixed to the High level.

The third operation state is a case where the potential of the word line WLA is at the selection level but the storage holding node N2 is at the Low level. In this case, the non-selection signal is output from the output terminal U to the pull-up circuit 4. The output signal is output (the control signal output from the output terminal U is inactive), and the selection signal (the control signal output from the output terminal D is active) is output from the output terminal D to the pull-down circuit 5. At this time, the bit line BLA
Is forcibly fixed to the low level.

In the present embodiment, the control circuit 6 having the memory holding node N2 and the read word line WLA as inputs generates such a control signal, thereby pulling the memory cell without using a transfer (transfer) gate. By the up circuit 4 and the pull-down circuit 5, the bit line BL
The potential of A is changed to a high level or a low level.

As described above, the memory cell circuit shown in FIG. 1 constitutes a two-port memory cell capable of one-port read and one-port write in which the output voltage of the read port is not affected by the threshold voltage of the MOS transistor. I have.

FIG. 2 is a diagram showing an example of a detailed circuit configuration of one embodiment of the memory cell circuit of the present invention shown in FIG.

Referring to FIG. 2, pull-up circuit 4 is an NPN bipolar transistor having a collector connected to power supply terminal VDD, an emitter connected to bit line BLA, and a base connected to output terminal U of control circuit 6. When the control circuit 6 outputs a signal indicating a selected state (in this case, High level) from the output terminal U, the bit line BLA is clamped to High level. When a signal indicating the selected state (in this case, a low level) is output, the bit line BLA enters a high impedance state (the NPN bipolar transistor Q7 is turned off). That is, in the present embodiment, the pull-up circuit 4 and the pull-down circuit 5 are composed of a Bi-MOS circuit combining the high speed of a bipolar transistor and a MOS circuit, and are suitable for driving the bit line BLA having a large load capacitance. You.

The pull-down circuit 5 includes two N-channel MOS transistors Q8 and Q9 connected in series between the emitter of the NPN bipolar transistor Q7 and ground.
And the signals D and D 'of the control circuit 6 simultaneously indicate the selected state (in this case, both D and D' are High).
h level), the bit line BLA is pulled low.
Clamp to level.

The outputs D and D 'of the control circuit 6
Is in a state indicating non-selection (in this case, outputs D and D ').
When at least one of them outputs Low level), the bit line BLA becomes high impedance and becomes disconnected.

The control circuit 6 comprises a two-input NAND logic gate NAND1 and an inverter circuit INV.
1, the input terminal W connected to the word line WLA is connected to one input terminal of the NAND1, and the input terminal N connected to the storage node N2 is connected to the other input terminal of the NAND1. .

The input of the inverter INV 1 forming the control circuit 6 receives the output of the NAND 1, and the output of the inverter circuit INV 1 is output as it is as the output U of the control circuit 6.

The output terminal D of the control circuit 6
For D ', the output of NAND1 is connected to pull-down circuit 5
, And the word line WLA signal is output as it is for D ′.

Regarding the operation of the control circuit 6, when the potential of the word line WLA is at the Low level, NAND1 is High regardless of the logical value of the storage node N2.
The output of the NAND1 is received by the inverter circuit INV1, a low level is output to the output terminal U, and the pull-up circuit 4 is brought into a high impedance state. In addition, since the word line WLA is at the Low level, the signal D 'is at the Low level, so that the N channel M
The OS transistor Q8 is turned off, the pull-down circuit 5 is also in a high impedance state, and the memory cell circuit is disconnected from the bit line BLA.

On the other hand, when the potential of the word line WLA is at the high level and the storage holding node N2 is at the high level, the output D of the NAND1 is at the low level, so that the gate in the pull-down circuit 5 is connected to the output of the NAND1. The turned off N-channel MOS transistor Q9 turns off the pull-down circuit 5 from the bit line BLA. Further, in response to the low level of NAND1, the output U of the inverter circuit INV1 becomes high level, and the bipolar transistor Q7 of the pull-up circuit 4
Is turned on, and the bit line BLA is clamped to the high level.

When the word line WLA is at the high level and the storage node N2 is at the low level, NA
The output of ND1 becomes High level and the inverter circuit I
Since the output of NV1 is at the Low level, the pull-up circuit 4 is disconnected from the bit line BLA, and the outputs D and D 'are also at the High level, so that the N-channel MOS transistors of the pull-down circuit 5 are both turned on. , The bit line BLA is clamped to a low level.

As described above, the word line WLA is set to High
At the time of the level, the control circuit 6 controls the pull-up circuit 4 and the pull-down circuit 5 to propagate the high level or the low level of the logical value held in the memory holding loop to the bit line BLA.

The pull-up circuit 4 is constituted by an NPN bipolar transistor Q7, and the bit line BL
Since the current driving capability for the capacity (load capacity) of A is higher than that of the MOS transistor, the rise time of the bit line BLA is longer than that of the CMOS in the conventional memory cell circuit.
It is faster than the configuration of the combination of the inverter and the transfer gate.

Further, in the above embodiment, the inverter of the storage holding loop is constituted by a CMOS circuit, but two high-resistance resistors R1 and R2 for load are used instead of the P-channel MOS transistors Q1 and Q3. A high resistance load type memory cell may be used.

In addition to the single-phase input of the memory holding node N2, the control circuit 6 uses the single-phase input of the node N1 or the differential (complementary) type input of the nodes N1 and N2 to generate the pull-up circuit 4 / pull-down. The circuit 5 may be controlled.

[0057]

As described above, according to the memory cell circuit of the present invention, even if the threshold voltage of the transistor greatly fluctuates from a predetermined target value due to the influence of manufacturing variations,
During the read operation, the bit line is not affected,
In addition, erroneous reading of data can be prevented, and data in a memory cell can be correctly propagated to the next stage.

Further, according to the present invention, by directly driving a bit line using a pull-up circuit and a pull-down circuit having a higher driving capability than a transfer gate, data of a high-load bit line can be transferred at a high speed. This has the effect of being able to be inverted.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional memory cell circuit.

FIG. 4 is a diagram showing another configuration of a conventional memory cell circuit.

[Explanation of symbols]

Q1, Q3, Q5, QT4 P-channel MOS transistors Q2, Q4, Q6, Q8, Q9, QT1, QT2, QT
3 N-channel MOS transistor Q7 NPN bipolar transistor BLA, BLB, BLB￣ Bit line WLA, WLA￣, WLB Word line N1, N2 Storage holding node U Pull-up circuit control signal D Pull-down circuit control signal W, N Control circuit control signal

Claims (6)

(57) [Claims] An output terminal and an input terminal are connected to each other to form a data holding loop, and a first and a second inverter circuit; and an input terminal and an output terminal of the first and the second inverter circuits. First and second one-conductivity-type transistors each connected between one connection node and a first bit line pair and having a gate connected to a first word line in common; A control circuit which receives at least one connection node of the two connection nodes of the inverter circuit and a second word line signal and outputs a predetermined control signal; and a second control circuit based on a control signal output from the control circuit. And a pull-up circuit and a pull-down circuit for directly setting the bit line to the first or second logic level. 2. The memory cell circuit according to claim 1, wherein said pull-up circuit includes a bipolar transistor as an element for pulling up said second bit line. 3. The memory cell circuit according to claim 2, wherein said pull-down circuit includes one or more N-channel MOS transistors connected in series between said emitter and ground terminal of said bipolar transistor. 4. The control circuit outputs a control signal for setting the outputs of the pull-up circuit and the pull-down circuit to a high impedance state when the second word line is at a potential indicating a non-selected state. 2. The memory cell circuit according to claim 1, wherein the memory cell circuit is configured as follows. 5. The control circuit is configured to output a control signal such that when one of the pull-up circuit and the pull-down circuit is in an active state, the other output is set to a high impedance state. The memory cell circuit according to claim 1, wherein: 6. A memory cell circuit for outputting a value stored in a data holding loop connecting an output terminal and an input terminal of a first and a second inverter circuit to a bit line by selecting a word line. A predetermined storage node of the data holding loop and the word line are input, and when the word line is in a selected state, a predetermined control signal is output based on a value of the storage node.
A control circuit, based on the value of the control signal outputted from the control circuit, and a circuit means for pulling up or pulling down the bit line to a high level or low level, said circuit means, said bit line The output terminal is connected to
Include Lee polar transistor, is pulled up by the bar <br/> Lee Paula transistors are turned on the bit lines to a high level, the memory cell circuit, characterized in that.