JP2850390B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory that performs various tests and evaluations using an output signal of a self-excited oscillator that drives a substrate potential generating circuit.

[Conventional technology]

Conventional semiconductor memories include a dynamic memory and a static memory. Here, the dynamic memory will be described.

FIG. 4 is a block diagram of a semiconductor memory showing an example of such a prior art.

As shown in FIG. 4, in a conventional semiconductor memory, particularly in a dynamic memory, ▲ ▼, ▲ ▼, ▲
▼, D _IN , D _OUT , Ai (i = 0 to n) are external terminals of the semiconductor memory, respectively, ▲ ▼ is a row address strobe, ▲ ▼ is a column address strobe, and ▲ ▼ is a write enable control terminal. . Ai (i = 0 to n) is an address input terminal, D _IN
Is a data input terminal, and D _OUT is a data output terminal.

First, for ▲, the 発 生 clock generator 4 and the CBR determination circuit 7A are driven, and the row address is taken into the address input circuits 9A to 9N while keeping the setup time and the hold time. The fetched address information is determined by the row decoder 12 by the address buffer 10, and a word line is selected. Next, the sense amplifier 14 amplifies the bit line to which a small signal difference is given by the potential of the memory cell on the word line of the selected memory cell array 15. On the other hand, the column decoder 11 maintains the setup time and the hold time with respect to the signal from the CAS clock generation circuit 5,
The output of the column decoder 11 determined by An drives the I / O gate 13 and connects the amplified bit line to the I / O line. In the read cycle, the I / O switch 18 connects the I / O line to the _DOUT buffer 17 and outputs data to the _DOUT terminal. In the write cycle, when the ▲ ▼ terminal is enabled, ▲ ▼
The _DIN buffer 16 is driven from the clock generation circuit 6, and the data of the _DIN terminal is written to the I / O line.
Desired data is written to the memory cells of the memory cell array 15 through the I / O gate 13.

The above operations are the read and write operations of the dynamic memory.

However, the dynamic memory requires the following refresh operation. That is, in order to prevent a malfunction at the time of reading due to “1” level leakage of a memory cell in the memory cell array 15, a word line is selected during a certain period, and data of the memory cell is amplified by the sense amplifier 14. Therefore, it is necessary to reset a high "1" level to the memory cell. This is an operation called refresh. Of course, in the read cycle and the write cycle as well, the selected word line performs the above-described operation, so that the refresh is performed.

For example, in a 256K memory, a general dynamic memory performs 256 refreshes in 4 msec, and a 1M memory performs 512 refreshes in 8 msec.
ONLY REFRESH) and CBR (CAS BEFORE RAS) refresh.

This ROR is performed by periodically applying a pulse only to the ▲ ▼ terminals, but it is necessary to change the data of the input address in each cycle, and the use of memory is complicated,
The memory after 256K memory has been improved so that it can be refreshed by CBR refresh. That is, the memory having the CBR determination circuit 7A and the refresh address counters 8A to 8N shown in FIG. 4 is the mainstream after 256K. Such a CBR refresh, ▲ ▼ from the V _IH
Initiated by quickly transition time of V _IL ▲ ▼ than that of. Which is earlier is determined by the internal CBR determination circuit 7A. If it is determined that the cycle is the CBR cycle, the fetching of the information of the external terminals Ai (i = 1 to n) is prohibited, and the information of the refresh address counters 8A to 8N is fetched by the respective address input circuits 9A to 9N. Information of the refresh address counter 8A~8N is output from the CBR decision circuit 7A for each entering the CBR cycle, the signal phi _A is input to the refresh address counter 8A lowest bit _'
Is incremented or decremented. Therefore, in a memory requiring a refresh operation 256 times in 4 msec, the refresh address counters 8A to 8A to i = 1 to 8 are obtained by performing 256 CBR cycles.
All combinations of 8N 8-bit data are changed, all word lines are selected, and all memories are refreshed.

Further, the substrate potential generating circuit 2 in FIG. 4 is described to keep the substrate potential at a negative potential, which is described as “increase in the leakage current of the transistor in the memory → floating of the substrate potential → threshold voltage of the transistor”. V _T decrease →
This is provided in order to prevent a loop of “increase in transistor leakage current”. For this reason, a configuration is often adopted in which the substrate potential generation circuit 2 is periodically driven by the self-excited oscillator 1 and the substrate potential is periodically pumped as shown in FIG. Since the self-excited oscillator 1 is operated even when the memory device is in a standby state, the self-excited oscillator normally operates regardless of the level applied to the external terminal.

[Problems to be solved by the invention]

The conventional semiconductor memory described above has a configuration in which the substrate potential generating circuit is periodically driven by the self-excited oscillator, and thus has a drawback that it is difficult to evaluate the frequency characteristics of the drive signal in the following points.

That is, firstly, it is difficult to evaluate at the wafer stage, and secondly, it is troublesome to remove the mold resin and the like in the evaluation after assembly, so that it takes time and effort to observe the waveform,
The third problem is that it is difficult to evaluate the frequency characteristics of the drive signal because the evaluation at low or high temperatures is difficult.

An object of the present invention is to provide a semiconductor memory capable of easily evaluating the frequency characteristics of a driving signal after such a wafer stage or assembling and facilitating the evaluation of the frequency characteristics at low and high temperatures.

[Means for solving the problem]

A semiconductor memory according to the present invention includes a built-in self-excited oscillator, a substrate voltage generation circuit for generating a substrate voltage by a drive signal from the self-excited oscillator, and a plurality of refresh address counters for setting a refresh address for a memory cell array. And the row address strobe signal,
A refresh determination circuit for performing a refresh operation by the plurality of refresh address counters when a column address strobe signal satisfies a predetermined condition; an external test terminal for supplying a test signal from outside; A test terminal is connected to the self-excited oscillator and the refresh judging circuit. When the test signal and the judgment output of the refresh judging circuit enter a test cycle, the drive signal of the self-excited oscillator is supplied to the plurality of refresh circuits. A test circuit for outputting to the least significant refresh address counter of the address counters, wherein outputs of the plurality of refresh address counters are controlled by the drive signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory showing one embodiment of the present invention.

As shown in FIG. 1, the present embodiment is the same as the above-described conventional example except for the test circuit 3 and its periphery, so that the description of the circuits having the same numbers as those of the conventional example will be omitted. First, TE is the test enable terminal, phi ₀ is a signal having a phase difference own output signal of the excited oscillator 1, or against it which drives the substrate potential generating circuit 2. Further, the phi _A is the output signal of the CBR decision circuit 7, phi _{A 'is} the input signal to the least significant of the refresh address counter 8A. The operation of this embodiment is the same as that of the conventional example in a normal write cycle and a read cycle, and is not affected by the test circuit.

 FIG. 2 is a configuration diagram of the test circuit shown in FIG.

As shown in FIG. 2, the test circuit in this embodiment is
N-channel transistor between ground and TE terminal Q ₁₁ to Q _{1 m} and Q ₂₁ to Q _2n are connected. I is an inverter,
Q _P1 and Q _P2 are P-channel transistors, and Q _N1 and Q _N2 are N-channel transistors. The operation of the test circuit will be described with reference to FIG.

FIG. 3 is a timing chart of various signals in FIG. 1 and FIG.

As shown in FIG. 3, the test circuit in the present embodiment, since the low level is applied to the TE terminal in CBR cycle, the phi _T is at a low level. Therefore, since the transistors Q _N1 and Q _P1 are turned on, φ _A becomes φ _{A '} , and the data of the refresh address counters 8A to 8N is set to 1
Only increment. In the test cycle, since ▲ and ▼ are at the high level, the memory is in the standby state. At this time, by the high level of phi _T by a high level added to the TE terminal, and turns off the transistor Q _N1, Q _P1, transistor
_{Turn on} Q _N2 and Q _P2 . In this cycle, φ ₀ becomes φ
_{A ′} , and φA _′ is clocked at the cycle of the self-excited oscillator 1. Therefore, if the time of the test cycle is t _C and the cycle of the self-excited oscillator 1 is t ₀ , the data of the refresh address counters 8A to 8N are incremented by t _C / t ₀ . In FIG. 3, the test cycle t _C is 2t
₀ , so refresh address counters 8A-8
The data of N is incremented by two.

〔The invention's effect〕

As described above, in the semiconductor memory of the present invention, in the test cycle, the bit information of the refresh address counter can be incremented by the output signal of the self-excited oscillator for driving the substrate potential generating circuit, so that the information of the refresh address counter has increased. By knowing this, the cycle or frequency of the asynchronous signal can be evaluated. Moreover, since this evaluation does not require waveform observation or the like and can be performed only by executing a test pattern with a normal memory tester, Regardless of the above, there is an effect that the frequency of the self-excited oscillator can be easily measured.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory showing one embodiment of the present invention, FIG. 2 is a block diagram of a test circuit shown in FIG.
FIG. 4 is a timing chart of various signals in FIGS. 1 and 2, and FIG. 4 is a block diagram of a semiconductor memory showing an example of a conventional example. 1 self-excited oscillator, 2 substrate potential generation circuit, 3 test circuit, 4 clock generation circuit, 5 clock circuit
▲ ▼ Clock generation circuit, 6 ... ▲ ▼ Clock generation circuit, 7 ... CBR determination circuit, 8A-8N ... Refresh address counter, 9A-9N ... Address input circuit, 10 ... Address buffer, 11 ... … Column decoder,
12 ...... row decoder, 13 ...... I / O gate, 14 ...... sense amplifier, 15 ...... memory cell array, 16 ...... D _IN buffer, 17 ...... D _OUT buffer, 18 ...... I / O switch, Q ₁₁ ~ Q
_{1m, Q 21 ~Q 2n, Q} N1, Q N2 ...... N -channel transistor,
Q _P1 , Q _P2 ... P-channel transistor, φ _A ... CBR judgment output, φ ₀ ... Self-excited oscillator output, φ _{A ′} ... Least significant refresh address counter input.

Claims (1)

(57) [Claims] An internal self-excited oscillator; a substrate voltage generating circuit for generating a substrate voltage by a drive signal from the self-excited oscillator; a plurality of refresh address counters for setting a refresh address for a memory cell array; A refresh determination circuit for performing a refresh operation by the plurality of refresh address counters when the row address strobe signal and the column address strobe signal satisfy predetermined conditions; and a refresh determination circuit for externally supplying a test signal. An external test terminal,
The test signal and the judgment output of the refresh judgment circuit are connected to the external test terminal, the self-excited oscillator and the refresh judgment circuit. A test circuit for outputting to the lowermost refresh address counter of the refresh address counters, wherein the outputs of the plurality of refresh address counters are controlled by the drive signal. .