JP2842598B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2842598B2 JP2842598B2 JP63305201A JP30520188A JP2842598B2 JP 2842598 B2 JP2842598 B2 JP 2842598B2 JP 63305201 A JP63305201 A JP 63305201A JP 30520188 A JP30520188 A JP 30520188A JP 2842598 B2 JP2842598 B2 JP 2842598B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- probe
- bonding pad
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000004020 conductor Substances 0.000 claims description 6
- 239000000523 sample Substances 0.000 description 27
- 230000007547 defect Effects 0.000 description 5
- 238000006073 displacement reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 241001422033 Thestylus Species 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路のテスト容易化回路に関す
る。Description: TECHNICAL FIELD The present invention relates to a circuit for facilitating test of a semiconductor integrated circuit.
従来、半導体集積回路のボンディングパッドにプロー
ブカードの探針を合せるには、目視で合せた後、LSIテ
スタにて探針をボンディングパッドが接着していること
を確認していた。Conventionally, in order to match the probe card's probe with the bonding pad of the semiconductor integrated circuit, after visually checking, it has been confirmed that the probe is adhered to the probe with an LSI tester.
上述した従来の半導体集積回路は、第１に入出力端子
の多ピン化が進むにしたがい、プローブカードの探針数
が多くなり、また探針の集積度も高くなるので目視によ
るプローブカードの探針とボンディングパッドの位置合
せが困難になってきた。In the conventional semiconductor integrated circuit described above, first, as the number of pins of the input / output terminals increases, the number of probes of the probe card increases, and the degree of integration of the probes also increases. It has become difficult to align the needle and the bonding pad.
第２に、LSIテスタにて探針とボンディングパッドが
接触していることを確認する時、ボンディングパッドの
端に探針が接触していたり、針圧のかけすぎで探針が半
導体集積回路の内側へ食込んでボンディングパッドから
一部食出していても検出できなかった。ボンディングパ
ッドの端に探針が接触すると、パッドが欠けたりする原
因となる。Secondly, when confirming that the probe and the bonding pad are in contact with the LSI tester, the probe is in contact with the end of the bonding pad, or the probe is No detection was possible even if it digged inward and partially bleed out from the bonding pad. If the probe contacts the end of the bonding pad, the pad may be chipped.
第３に、初めにLSIテスタにてボンディングパッドと
探針が接触していることを確認しても、セッティングミ
ス等により多数のLSIを連続して測定しているとボンデ
ィングパッドと探針がずれてくることがあるが、この位
置ずれをLSIテスタでは、半導体集積回路のオープン不
良と区別できなかった。Third, even if it is first confirmed by the LSI tester that the bonding pad and the probe are in contact, if many LSIs are measured continuously due to setting mistakes, etc., the bonding pad and the probe will be misaligned. However, this displacement could not be distinguished from the open defect of the semiconductor integrated circuit by the LSI tester.
本発明の半導体集積回路は、半導体集積回路チップの
バッファ回路の外側に、ボンディングパッドより面積が
小さい位置ずれチェック用パッドを前記チップの四隅に
備え、かつ、これら四隅のチェック用パッド間を接続す
る導体を前記ボンディングパッドの外側に有したことを
特徴とする。The semiconductor integrated circuit according to the present invention includes, on the four corners of the chip, misalignment check pads having an area smaller than the bonding pads on the outside of the buffer circuit of the semiconductor integrated circuit chip, and connects the check pads at the four corners. A conductor is provided outside the bonding pad.
したがって、本発明の半導体集積回路は、第１にボン
ディングパッドとプローブカードの探針の位置ずれ，針
圧のかけすぎ等による探針の半導体集積回路内部への食
込みを電気的にチェックでき、第２半導体集積回路のオ
ープン不良か探針とボンディングパッドの位置ずれによ
る不良の判定が容易になる。Therefore, the semiconductor integrated circuit according to the present invention can firstly electrically check the position of the probe between the bonding pad and the probe card and the penetration of the probe into the semiconductor integrated circuit due to excessive application of the stylus pressure. (2) It is easy to determine a defect due to an open defect of the semiconductor integrated circuit or a displacement between the probe and the bonding pad.
次に、本発明について図面を参照して説明する。第１
図は本発明の実施例である。第１図において、“1"は半
導体集積回路のボンディングパッド、“2"はパッド、
“3"は導体、“4"はLSIチップである。Next, the present invention will be described with reference to the drawings. First
The figure shows an embodiment of the present invention. In FIG. 1, "1" is a bonding pad of a semiconductor integrated circuit, "2" is a pad,
“3” is a conductor, and “4” is an LSI chip.
パッド２はボンディングパッドの1/4の面積にしてあ
る。探針をボンディングパッド１と同様にパッド２にも
たてて、探針がパッド２に接触していれば、ボンディン
グパッドの中心の1/4の面積中に探針が接触しているこ
とになる。よってパッド2aと2bにたてている探針間の導
通チェックをすれば、ボンディングパッドとプローブカ
ード探針位置のずれ、針圧のかけすぎ等による探針の半
導体回路内部への食込みを電気的にチェックできる。The pad 2 has an area of 1/4 of the bonding pad. When the probe is placed on the pad 2 like the bonding pad 1 and the probe is in contact with the pad 2, the probe is in contact with the area of 1/4 of the center of the bonding pad. Become. Therefore, if a continuity check between the probes set on the pads 2a and 2b is performed, the displacement of the bonding pad and the probe card probe position, and the biting of the probe into the semiconductor circuit due to excessive application of the needle pressure, etc., are electrically performed. Can be checked.
第２図は、本発明の一実施例である。第２図において
“1"は半導体集積回路のボンディングパッド、“2"はパ
ッド、“3"は導体、“4"はLSIチップである。FIG. 2 shows an embodiment of the present invention. In FIG. 2, "1" is a bonding pad of a semiconductor integrated circuit, "2" is a pad, "3" is a conductor, and "4" is an LSI chip.
パッド２を四隅につけることにより、プローブカード
の傾き等による部分的な針圧のかかりすぎも電気的にチ
ェックすることが可能となる。By attaching the pads 2 at the four corners, it is possible to electrically check partial application of excessive needle pressure due to the inclination of the probe card or the like.
以上説明したように本発明は、ボンディングパッドよ
り面積が小さい少なくとも２個以上のパッド間を導体で
接続することにより、 第１に、ボンディングパッドとプローブカードの探針
の位置ずれ，針圧のかけすぎ等による探針の半導体集積
回路内部への食込みを検出でき、 第２に半導体集積回路のオープン不良か、探針とボン
ディングパッドの位置ずれによる不良かの判定が可能に
なるという効果がある。As described above, according to the present invention, at least two or more pads having an area smaller than that of a bonding pad are connected by a conductor. Secondly, it is possible to detect biting of the probe into the semiconductor integrated circuit due to overshoot or the like, and secondly, there is an effect that it is possible to determine whether the semiconductor integrated circuit has an open defect or a defect due to a displacement between the probe and the bonding pad.
第１図は、本発明の参考例、第２図は、一実施例を説明
する図である。 １……ボンディングパッド、２……パッド、３……導
体、４……LSIチップ。FIG. 1 is a diagram illustrating a reference example of the present invention, and FIG. 2 is a diagram illustrating an embodiment. 1 ... bonding pad, 2 ... pad, 3 ... conductor, 4 ... LSI chip.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 21/822 Ｈ０１Ｌ 21/88 Ｔ 27/04 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 21/822 H01L 21/88 T 27/04
Claims (1)
側に、ボンディングパッドより面積が小さい位置ずれチ
ェック用パッドを前記チップの四隅に備え、かつ、これ
ら四隅のチェック用パッド間を接続する導体を前記ボン
ディングパッドの外側に有したことを特徴とする半導体
集積回路。1. A semiconductor memory device comprising: a semiconductor integrated circuit chip having, outside a buffer circuit thereof, misalignment check pads smaller in area than bonding pads at four corners of the chip, and a conductor for connecting the four corner check pads. A semiconductor integrated circuit provided outside a bonding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63305201A JP2842598B2 (en) | 1988-12-01 | 1988-12-01 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63305201A JP2842598B2 (en) | 1988-12-01 | 1988-12-01 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02151048A JPH02151048A (en) | 1990-06-11 |
| JP2842598B2 true JP2842598B2 (en) | 1999-01-06 |
Family
ID=17942268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63305201A Expired - Lifetime JP2842598B2 (en) | 1988-12-01 | 1988-12-01 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2842598B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6833557B1 (en) * | 2000-06-27 | 2004-12-21 | Agere Systems Inc. | Integrated circuit and a method of manufacturing an integrated circuit |
| US6621280B1 (en) | 2000-06-27 | 2003-09-16 | Agere Systems Inc. | Method of testing an integrated circuit |
| WO2007055012A1 (en) * | 2005-11-10 | 2007-05-18 | Nhk Spring Co., Ltd. | Contact unit and testing system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5688333A (en) * | 1979-12-21 | 1981-07-17 | Hitachi Ltd | Detecting method of relative position between probe and contact |
| JPS6170735A (en) * | 1984-09-13 | 1986-04-11 | Sumitomo Electric Ind Ltd | Wafer or chip with alignment marks for electrical measurements |
| JPS62103255U (en) * | 1985-12-18 | 1987-07-01 |
-
1988
- 1988-12-01 JP JP63305201A patent/JP2842598B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02151048A (en) | 1990-06-11 |
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