JP2842572B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology effective for use in a logic integrated circuit such as a gate array. 2. Description of the Related Art In a gate array type semiconductor integrated circuit device, gates for clock transmission to an internal flip-flop circuit and expansion of the number of fan-outs are arranged in a cell array uniformly and regularly arranged. A clock pulse having a plurality of phases and periods is input to a flip-flop circuit in a semiconductor integrated circuit. Focusing on one clock signal, a plurality of gates acting as a kind of amplifying circuit are provided to a flip-flop circuit in a semiconductor integrated circuit which requires the clock pulse. At this time, the number of fan-outs is increased at each gate. Even for different clock pulses, distribution and transmission are performed with the same number of gate stages and the same number of fan-outs having the same configuration. The arrangement of the gates and the wiring between the gates from the clock input terminal of the plurality of clock pulses to the flip-flop circuit as described above are determined by the automatic layout program of the gate array LSI. The timing design of such a gate array is described in, for example, “Nikkei Electronics” published by Nikkei McGraw-Hill Company, 1986, No. 408, pp. 150-153. [Problems to be Solved by the Invention] With the speeding up of the semiconductor integrated circuit device as described above,
It is necessary to reduce the skew between clock pulses applied to the internal flip-flop circuit. However, in the conventional gate array, the flip-flop circuit and the preceding clock gate are arranged at an arbitrary position on the cell array, so that the clock pulse is transmitted to each flip-flop circuit with a delay time equal to each other. It becomes difficult. Accordingly, the clock pulse period must be set on the assumption that the skew occurs between the clock pulses, which hinders an increase in the frequency of the clock pulse. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device realizing high speed operation. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. [Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is,
A first clock pulse supply circuit is provided at a central portion of a semiconductor chip, and a second clock receiving a clock pulse from the first clock pulse supply circuit is provided at a central portion of each of a plurality of divided semiconductor regions. A pulse supply circuit is provided, from which a clock pulse is supplied to a logic circuit such as a flip-flop circuit.
The second clock pulse supply circuit is configured such that the complementary clock pulse output from the clock pulse supply circuit is received by the differential transistor pair. [Operation] According to the above-described means, from the input of the clock pulse,
Since the paths to the final logic circuit to which it is supplied can be set so as to be almost equivalent, the skew between the clock pulses can be suppressed to a small value.
By receiving the complementary clock pulse output from the clock pulse supply circuit of the differential transistor pair,
Preventing the pulse width of the clock pulse output from the second clock pulse supply circuit from changing due to the asymmetry of the rise and fall of the signal, thereby further reducing the skew between the clock pulses in the LSI. be able to. Embodiment FIG. 1 is a schematic block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. Each circuit block in the figure is formed by a known semiconductor integrated circuit manufacturing technique, and is drawn according to a geometrical arrangement on a semiconductor chip. In this embodiment, the semiconductor integrated circuit device LSI has four circuit areas divided into four equal parts as shown by dotted lines in FIG.
Has B1 to B4. In this embodiment, the first portion is located at the center of the semiconductor integrated circuit.
A (main) clock pulse supply circuit (clock buffer) MCG is fixedly arranged. The first clock pulse supply circuit MCG is supplied with clock pulses from the input circuits INC1 and INC2 when the internal flip-flop circuit or the like is operated by two-phase clock pulses, for example, but not particularly limited thereto. The first-phase clock pulse is input from an input circuit INC1 provided at the left central portion of the semiconductor integrated circuit device LSI, and is input to the first clock pulse supply circuit MCG via a wiring extending rightward therefrom. Is done. The clock pulse of the second phase is input from an input circuit INC2 provided at the right central part of the semiconductor integrated circuit device LSI, and is connected to the first circuit via a wiring extending leftward therefrom.
Input to the clock pulse supply circuit MCG. As described above, since the first clock pulse supply circuit MCG is arranged at the center of the chip, the wiring lengths between the input circuits INC1 and INC2 are substantially equal, and the two clock pulses are the same. With a long delay time. When supplying a large number of clock pulses having different phases to the semiconductor integrated circuit, it is desirable that the input circuits INC1 and INC2 have a waveform shaping function and have a narrow and constant clock pulse width. This makes it possible to prevent the clock pulses from overlapping each other. Also, each of the circuit areas B1 to B1 divided as described above.
In the center of B4, second (local) clock pulse supply circuits (clock buffers) LC1 to LC4 are fixedly provided. Therefore, the wiring between the first clock pulse supply circuit MCG and the second clock pulse supply circuits LC1 to LC4 is also fixed and arranged so that the mutual wiring lengths are substantially equal. In this embodiment, although the gate array realizes a general-purpose circuit function, the clock pulse supply circuit as described above is independent of the circuit function configured by the gate array. Its configuration and arrangement are fixedly configured. The second clock pulse supply circuits LC1 to LC4 each have a plurality of fan-out numbers radially, and
Almost the same number of flip-flop circuits are assigned to one output line. If the number of flip-flop circuits and the like coupled to one output line is small, an appropriate unused gate cell can be connected as a dummy circuit and set to have the same load. FIG. 2 shows a simplified equivalent circuit diagram focusing on one clock pulse. The clock pulse CLK input from the external terminal is supplied to the first clock pulse supply circuit MCG via the input circuit INC1. The first clock pulse supply circuit MCG includes gates that function as amplifier circuits corresponding to the four clock pulses having different phases as described above and the four second clock pulse supply circuits LC1 to LC4. The clock pulses output from the four gates are supplied to the gates of the four second clock pulse supply circuits LC1 to LC4. One second clock pulse supply circuit LC
1 is composed of a plurality of gates (clock buffers) acting as amplifier circuits corresponding to the number of fan-outs, and each gate includes a plurality of flip-flop circuits.
The clock pulse is transmitted to FF and the like. In this case, the dummy circuits may be connected such that the number of flip-flop circuits and the like coupled to the last-stage gate is equal to each other in all the gates. Further, the wiring length is fixedly determined in advance so as to be as equal as possible. FIG. 3 is a circuit diagram showing an embodiment of the above-mentioned gate and a flip-flop circuit corresponding to the gate when the present invention is applied to a gate array composed of an ECL (emitter-caffled logic) circuit. The flip-flop circuit FF1 of this embodiment has only a mere latch function. The input signal D is supplied to the base of the differential transistor Q20. The reference voltage Vbb1 is supplied to the base of the transistor Q21 which is in a differential form with the transistor Q20. Load resistors R10 and R11 are provided at the collectors of the differential transistors Q20 and Q21, respectively. The collector outputs of the differential transistors Q21 and Q20 are
A differential transistor Q2 is connected via an emitter follower output circuit comprising transistors Q23 and Q24 and a constant current source Io, respectively.
Supplied to the base of 5 and Q26. The collectors of the differential transistors Q25 and Q26 are connected to the collectors of the differential transistors Q20 and Q21 crosswise with respect to their inputs to form a positive feedback loop. In other words, the collectors of the differential transistors Q20 and Q21, Q25 and Q26 are connected in a latch form. Differential transistors Q22 and Q27 are provided on a common emitter of the pair of differential transistors Q20 and Q21 and Q25 and Q26. The emitters of these transistors Q22 and Q27 are commonly connected to provide a constant current source Io. The base of the transistor Q22 is supplied with an inverted internal clock pulse ▼ which will be described later, and the base of the transistor Q27 is supplied with a non-inverted internal clock pulse CK. The common collector output signal of the differential transistors Q21 and Q26 is input to an emitter follower output circuit including the transistor Q29 and the constant current source Io. An output signal Q is output from the emitter follower output circuit. If an inverted output signal is required, a similar emitter follower output circuit may be connected to the collector of the transistor Q20. Although not particularly limited, the pulses CKH and CKL are complementary clock pulses. That is, the gate as the amplifier circuit of this embodiment receives a complementary pulse as described above by the differential transistors Q41 and Q42 without having a reference voltage like a normal ECL circuit, and the same transistor as described above.
The internal clock pulses CK and ▼ are formed via an emitter follower output circuit including Q43 and Q44 and a constant current source Io. In this case, as described above, the differential transistor Q22
And Q27 are cascaded to the differential circuit receiving the reference voltage Vbb1, so that the clock pulses CK,
▲ ▼ is transmitted by being level-shifted by a level-shifting diode. Further, the first clock pulse supply circuit MCG forms a complementary clock pulse corresponding to the gate of the second clock pulse supply circuit because the gate of the second clock pulse supply circuit receives the complementary clock pulse as described above. is there. In the case of adopting the configuration of transmitting the complementary clock pulse as described above, the gate can be free from the influence of the variation and fluctuation of the reference voltage Vbb1, so that each gate has a stable signal propagation delay time. In other words, the signal propagation delay time of the rise and fall of the clock pulse becomes similar, and the pulse width of the output clock pulse does not change due to the asymmetry of the rise and fall of the signal. The complementary internal clock pulses CK and ▼ are supplied to the flip-flop circuit FF1 as well as a plurality of other flip-flop circuits (not shown). The flip-flop circuit FF1 of this embodiment captures the input signal D at the timing when the input clock pulse CKH changes from a low level to a high level. That is,
When the clock pulse CKH is low, the internal inverted clock pulse
To turn on Q22, the input signal D is captured by the differential transistors Q20 and Q21. In this state,
When the clock pulse CKH changes to the high level as described above, the inverted internal clock pulse ▼ is set to the low level, and the non-inverted internal clock pulse CK is set to the high level, so that the transistor Q22 is turned off and the transistor Q27 is turned off.
Is switched on. As a result, the differential transistors Q25 and Q26 are activated, and the levels of the load resistors R10 and R11 are held in accordance with the input signal D. In this embodiment, the clock pulse runs from the input circuit to the last end of the flip-flop circuit or the like that requires it.
All are transmitted via a clock buffer (clock supply circuit) as an amplifier circuit having the same configuration and wiring. Therefore, the difference between the signal propagation delay times of the clock pulses transmitted to the flip-flop circuits and the like can be almost eliminated, and the occurrence of skew can be minimized. Thus, it is not necessary to set the clock pulse period with a certain margin in consideration of the skew, and the frequency can be increased by that amount, so that high-speed operation can be achieved. The operational effects obtained from the above embodiment are as follows. That is, (1) the first clock pulse supply circuit formed at the center of the semiconductor chip is provided at the center of each of the semiconductor regions divided into a plurality of regions around the first clock pulse supply circuit. The second receiving the clock pulse of
By providing a clock pulse supply circuit for supplying a clock pulse to a logic circuit such as a flip-flop circuit from the clock pulse supply circuit, a path from the input of the clock pulse to the final logic circuit to which the clock pulse is supplied is provided. Since the settings can be made almost the same, the skew between the clock pulses can be reduced. As a result, it is not necessary to set the clock pulse period with a certain margin in consideration of the skew, and the frequency can be increased by that amount, so that an effect that high-speed operation can be achieved is obtained. (2) In a configuration in which a clock pulse is supplied from an external terminal, a waveform is shaped by an input circuit, and a configuration in which a complementary clock pulse is output is adopted. Therefore, each of the gates has a stable signal propagation delay time. In other words, the signal propagation delay time of the rise and fall of the clock pulse becomes the same, and the pulse width of the output clock pulse does not change due to the asymmetry of the rise and fall of the signal. by this,
The effect that the occurrence of skew can be further prevented can be obtained. (3) By using the dummy circuit to equalize the substantial fan-out number of the clock buffer at the last stage, the load can be made almost equal. As a result, an effect that the occurrence of the skew can be suppressed to the minimum can be obtained. Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor. For example, in FIG. 1, a differential amplifier circuit as a clock buffer may be inserted in the middle of the wiring connecting the input circuits INC1, INC2 and the first clock pulse supply circuit. In a large-scale semiconductor integrated circuit, a third clock pulse supply circuit may be provided, from which a clock pulse is supplied to a flip-flop circuit or the like. That is, each circuit area
B1 to Bn are each similarly divided into a plurality of regions,
A third clock pulse supply circuit is arranged at the center. In other words, the circuit areas B1 to Bn are
A wiring and a clock pulse supply circuit similar to those of a semiconductor integrated circuit LSI are provided. The clock pulse may be generated internally. In this case, an oscillation circuit may be formed in the first clock pulse supply circuit.
If external components are required to form the oscillation circuit, an oscillation circuit and a waveform shaping circuit may be provided at the input circuit INC. In addition to the ECL circuit, CMOS (complementary M
(OS) circuit. In this case, a CMOS inverter circuit is used as the clock buffer. INDUSTRIAL APPLICABILITY The present invention can be widely used for a semiconductor integrated circuit device constituting a digital integrated circuit such as a gate array. [Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a first clock pulse supply circuit is provided in a central portion of a semiconductor chip, and a second portion which receives a clock pulse from the first clock pulse supply circuit is provided at a central portion of each of the divided semiconductor regions. By providing a clock pulse supply circuit and supplying a clock pulse to a logic circuit such as a flip-flop circuit from the clock pulse supply circuit, a path from the input of the clock pulse to the final logic circuit to which the clock pulse is supplied is provided. Almost all can be set to be the same, so that the skew between clock pulses can be suppressed to a small value. Further, the complementary clock pulse output from the first clock pulse supply circuit is received by the differential transistor pair. By configuring the second clock pulse supply circuit at the same time, the skew between clock pulses in the LSI can be increased. A, it is possible to further reduce.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram showing one embodiment of the present invention, FIG. 2 is an equivalent circuit diagram focusing on one clock pulse, and FIG. FIG. 4 is a circuit diagram showing a specific example of a gate as a clock supply circuit. LSI ... Semiconductor integrated circuit device (semiconductor chip), INC1, IN
C2: input circuit, MCG: first (main) clock pulse supply circuit, LC1 to LC4: second (local) clock pulse supply circuit, FF1 to FF4: flip-flop circuit

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Masato Hamamoto               2326 Imai, Ome City, Tokyo Japan               Inside the Device Development Center at Ritsumi Works (72) Inventor Toru Kobayashi               2326 Imai, Ome City, Tokyo Japan               Inside the Device Development Center at Ritsumi Works                (56) References JP-A-55-80136 (JP, A)

Claims (1)

(57) [Claims] A first clock pulse supply circuit formed at the center of the semiconductor chip and capable of outputting complementary clock pulses; and a first clock pulse supply circuit at the center of each of the semiconductor regions formed by dividing the semiconductor chip into a plurality of regions. A second clock signal that can supply a complementary clock pulse to a plurality of logic circuits belonging to a corresponding semiconductor region based on the complementary clock pulse output from the first clock pulse supply circuit.
A clock pulse supply circuit for transmitting a complementary clock pulse from the first clock pulse supply circuit to the second clock pulse supply circuit. Are arranged to be substantially equal to each other, and the second clock pulse supply circuit has a first transistor for taking in a first clock pulse output from the first clock pulse supply circuit, A first transistor coupled logic coupled with a second transistor for receiving a second clock pulse output from the first clock pulse supply circuit in a complementary relationship with the first clock pulse; The plurality of logic circuits take in a third clock pulse output from the second clock pulse supply circuit.
And a fourth transistor for taking in a fourth clock pulse output from the second clock pulse supply circuit in a complementary relationship with the third clock pulse. A semiconductor integrated circuit device comprising: 2. 3. The logic circuit according to claim 1, wherein the logic circuit includes a uniformly arrayed cell array and is formed as a gate array.
Item 13. The semiconductor integrated circuit device according to Item 1. 3. 2. The circuit according to claim 1, wherein the second clock pulse supply circuit includes a plurality of clock pulse output terminals, and a dummy circuit is coupled such that loads coupled to the respective output terminals are equal to each other. Or a semiconductor integrated circuit device according to claim 2.