JP2840277B2 - Improved bi-CMOS read / write memory - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to the field of electronic integrated circuits, and more particularly to circuits for use in read / write memory cells.

BACKGROUND OF THE INVENTION Integrated circuit memory cells are often organized in rows and columns of memory cells, where the rows and columns are selected separately based on the value of a portion of the memory address that represents the row and column addresses. In such devices, the word "word line" generally refers to a set of conductors, one of which actively selects an addressed row of memory cells, and the word "bit line" is generally Refers to a set of conductors that carry data between a row of memory cells and a sense amplifier. A sense amplifier is a circuit that detects the data state of the data on the associated bit line, and is generally a circuit that amplifies the detected data state for transmission to the output stage.

Due to the drive capability of static memory cells, when memory cell 1 consists of latches, multiple columns of multiple static random access memories (SRAMs) share a single sensor amplifier. However, due to the detection resolution, generally the shorter the bit line associated with a single sense amplifier, the smaller the difference voltage detectable by the sense amplifier. Therefore, it is preferable to provide a single sense amplifier for each column of the memory cell array for detection.

However, providing the large number of sense amplifiers required to have one sense amplifier per column increases the load needed to drive a particular sense amplifier. For example, 256 kbits of organized S in 256 rows and 1024 columns
In a RAM, 1024 sense amplifiers must be provided to provide a one-to-one correspondence between sense amplifiers and columns. The sense amplifier associated with the selected column must therefore be able to drive the data lines connectable to the other 1023 sense amplifiers. Such capacitive loads on long data lines include parasitic loads provided by isolation transistors that disconnect the sense amplifiers from the data lines, especially those that have not been selected, but both require large drive transistors for each sense amplifier. Must be provided,
Alternatively, the read access time efficiency is reduced. In structures where a single sense amplifier is provided for each column, the space required for the sense amplifiers on a line (ie, the sense amplifier pitch) can significantly affect the size of the integrated circuit required to incorporate the SRAM device. Without being as widespread as possible, it cannot be larger than the space required to provide a column of memory cells (ie, column pitch), and such pitch suppression can of course be provided in a sense amplifier. Note that this will limit the size of the transistor.

Accordingly, it is an object of the present invention to provide a detection and decoding mechanism for static RAM devices that takes into account reduced data line loading for sense amplifiers.

It is also an object of the present invention to provide such a mechanism for an SRAM having a single sense amplifier for each column of memory cells.

It is a further object of the present invention to provide such a mechanism implemented in bi-CMOS technology.

Further, the sense amplifier of such a memory circuit is generally required to detect a small difference voltage between a pair of bit lines to which a selected memory cell is connected. For speed, each of the paired bit lines is generally
It is precharged to a predetermined voltage, and is equalized by connecting the bit lines of the pair for a short period after the precharge operation. In conventional static random access memory ("SRAM"), a pull-up device is connected between each bit line and a current source, which pulls one bit line of a bit line pair. Raised to high,
It is desirable to help pull the other bit line of the bit line pair low, and the choice of which bit line goes high depends on the detected data state of the addressed memory cell. In bi-CMOS SRAMs, it is better to use bipolar transistors as pull-up devices if possible, because they have rapid switching characteristics (the higher bit line of a bit line pair must be at least higher than the positive power source level). This is because it operates as a diode clamp for the bit line (keeping one diode drop low).

However, the diode characteristics of a bipolar pull-up device can cause problems if the positive ( _Vcc ) power source to which the pull-up transistor is connected has noise.
Since the bipolar pull-up transistor operates as a diode, the positive noise V _cc is will pull up both pit line to a higher voltage, negative noise of V _cc does not affect the voltage of the bit line. After a positive noise "bump" of _Vcc raises both bit lines to a higher level, the read cycle pulls down one bit line of the bit line pair and leaves the other bit line at the bumped voltage. Cause it. If the positive bump is too large, the precharge and equalization operations, i.e., if the pull-up of the bit line by the pull-up transistor is not sufficient to completely equalize the bit line at the end of the cycle, Default occurs in the next cycle. In the case of completely static RAM, this failure occurs when the bit line differential voltage by Nariizu is so large that the memory cell does not have enough time to provide the bit line voltage to the correct pole. It is.

Accordingly, it is an object of the present invention to provide a bit line pull-up circuit that is resistant to perturbation of a biasing power source having a bipolar pull-up device.

A write operation to a particular memory cell generally pulls one bit line of the bit line pair low (V _ee ),
It is accomplished by pulling the other bit line to a high voltage level (V _cc -V _be). After a write cycle, these bit lines must again be pulled up by a bipolar pull-up transistor to the same relative potential in preparation for a subsequent read cycle. However, a large bit line differential voltage after writing requires a very large pull-up device or a longer pull-up period if either is not desirable.

It is, therefore, another object of the present invention to provide a bit line pull-up circuit that reduces the differential voltage on a bit line during a write cycle and then increases the speed at which the bit line is restored to an equalized voltage.

It is a further object of the present invention to provide such a pull-up circuit that incorporates bi-CMOS technology.

Yet another object of the present invention is to provide one per column of memory cells.
An object of the present invention is to provide such a pull-up circuit in which a plurality of sense amplifiers are arranged.

It is yet another object of the present invention to provide such a pull-up circuit that reduces the bit line differential voltage while providing improved immunity to perturbations of the _Vcc power source.

Other objects and advantages of the present invention will become apparent to those of ordinary skill in the art by reference to the following examples in connection with the accompanying drawings.

SUMMARY OF THE INVENTION The present invention is a bi-CMOS SRAM read / write having a pair of complementary bit lines associated with each instance of a memory cell and a first stage sense amplifier associated with each column. Incorporated into memory. These first-stage sense amplifiers are arranged in groups, and each first-stage sense amplifier in the group drives a common pair of complementary data lines. A second stage sense amplifier is provided for each group, and a pair of global data lines are driven by all the second stage sense amplifiers. The column address is decoded to select one of the first stage sensor amplifiers, but the unselected first stage sense amplifiers are disabled and transmit high impedance to the local data lines. Using the most significant bits of the column address, the second stage sense amplifier associated with the selected group including the first stage sense amplifier can be used, and the other second stage sense amplifiers can be used. Disable use and transmit high impedance to global data lines.

The present invention is a bi-CMOS having a pair of complementary bit lines associated with each column of memory cells, each of said bit lines having a bipolar transistor for a pull-up device.
Incorporated into SRAM read / write memory. A pull-up circuit is provided that operates as a noise depletion filter on the power supply line so that the positive noise of the power supply does not raise the bit line voltage above the equalization value. Providing another pull-up circuit for controlling the base drive of the pull-up transistor during a write cycle, reducing the base drive of the pull-up transistor associated with the higher bit line of the bit line pair, To provide a shorter crossing time for the read cycle.

FIG. 1 is a block diagram of a static random access memory (SRAM). The SRAM 1 according to the present embodiment has a single input / output terminal I / O of 256 k
It is a bit of memory (ie, SRAM1 is organized as 256k × 1 memory). The storage element of SRAM 1 is included in array 2, but array 2 of this embodiment has 256 rows and 102 rows.
It is organized in four rows. SRAM1 receives the address information of the address input An. In order to individually address each bit in the 256 kbit memory, the number of address inputs An is set to 18. Of course, if more than one bit is accessed at the same time (for example, if the 256k bit SRAM1 is organized as a 32k × 8 memory with 8 inputs and 8 outputs), a smaller number of address inputs An is needed. is there.

The address input An is received by an address buffer 4 which latches and maintains the value of an externally presented address on the address input An, as is well known in the art. Eight of the eighteen address bits received by address buffer 4 are eight bits as corresponding to the row address,
The signal is transmitted to the X decoder 6 to select one of the 256 rows in the array 2. The remaining 10 bits received by the address buffer 4 correspond to the column address and are transmitted to the first stage Y-decoder 8 to be output by one of the 1024 first-stage sense amplifiers 10. Select one of the 1024 columns in array 2 to be detected. Each of the 1024 columns, and thus 1024 first stage sensor amplifiers, is associated with a complementary pair of bit lines and is selected from the 1024 first stage sensor amplifiers, as described below. The other detects the difference voltage between the complementary bit lines. As described in more detail below, the deposited bit line pull-up transistor 21 is
Provide to AM1.

Five of the ten column address bits are likewise transmitted to the second stage Y decoder 12 to select one of the second stage sense amplifiers 14. Although FIG. 1 shows two separate Y decoders 8 and 12, the second stage Y decoder 12 may be incorporated in the same stage Y decoder 8 instead. Such incorporation may be necessary if multiple decoding stages are required in the first stage Y decoder 8, and the break between the decoding stages selects one of the second stage sense amplifiers 14. To do what is necessary to
The output of the second-stage sense amplifier 14 is used to select not only the appropriate second-stage sense amplification decision 14 but also the first-stage sense amplifier 10 during decoding of the column address signal. Select one of The first-stage sense amplifiers 10 on the 1024 side are assembled into 32 groups of 32, and each group has a complementary pair of local data lines 16 as an output. One of the second stage sense amplifiers 14 is associated with each group of 32 first stage sense amplifiers and receives at its input the associated pair of local data lines 16. The data out line 18 of the complementary pair is driven by the second stage sense amplifier 14. In operation, the first stage sense amplifier 10 corresponding to the column address is enabled by the signal from the first stage Y decoder 8, but the other first stage sense amplifier 10 is enabled by the Y decoder 8. Disables detection of the data state of the associated pair of bit lines from array 2. One of the second-stage sense amplifiers 14 corresponding to the group of the first-stage sense amplifiers 10 having the selected column is also enabled, and the other second-stage sense amplifiers 14 are used. Be banned. A selected one of the second stage sense amplifiers 14 is:
On the data out line 18, the input / output circuit presents a differential voltage which is the amplification of the differential voltage of the local data line 16 at its input.
Communicate to 20. The input / output circuit 20 transmits the state of the data out line 18 to the input / output terminal to the A / O.

The input / output circuit 20 of the SRAM 1 of FIG. 1 also receives input data from the input / output terminal I / O, but the determination of whether a read cycle or a write cycle is desired is connected to the input / output circuit 20. Depends on the state of the terminal R / W. During a write cycle, the input / output circuit 20 communicates an externally presented logical state to the input / output terminal I / O to the data-in bus 22, which transmits the true and multiple states of the input data to the first input / output terminal. The signal is transmitted to the first stage sense amplifier 10 and transmitted to the selected memory cell of the array 2. The data-in bus 22 is also connected to a pull-up control circuit 23 to perform a write recovery operation described in more detail below.

The SRAM 1 also has a reference voltage circuit 24 for receiving the power source voltages _Vcc and _Vee (ground potential). Power source voltage V
_{Although cc} and V _ee are carried to the transistors in SRAM1 for biasing, such transmission is the first for clarity.
Not shown in the figure. SRAM1 of the specific embodiment described here
Is a bi-CMOS SRAM with P-channel and N-channel MOS
Not only transistors but also bipolar transistors are used. Certain circuits of the SRAM 1 of the present embodiment are realized by emitter-coupled logic. When using emitter-coupled logic, reference voltage circuit 24 provides a bandgap reference voltage.

Referring now to FIG. 2, there is shown a bi-CMOS SRAM.
Conventional CMOS static memory cell incorporated in 1 2
4 is shown. Although memory cell 24 is configured according to the well-known implementation of a cross-coupled inverter, a CMOS inverter is used in memory cell 24 because both P-channel and N-channel transistors are available. . The first CMOS inverter of the memory cell 24 includes a P-channel transistor 26 and an N-channel transistor 28, and has a source-drain path of _Vcc.
And ground are connected in series, and the gate is tied. Similarly, the second CMOS inverter of memory cell 24 has a P-channel circuit in which the source-drain path is connected in series between _Vcc and ground, and the gate is likewise common.
It comprises a transistor 30 and an N-channel transistor 32. The cross-coupling occurs when the gates of transistors 26 and 28 are connected to the drains of transistors 30 and 32 (node S in FIG. 2).
2) and that the gates of transistors 30 and 32 are connected to the drains of transistors 26 and 28 (node S1 in FIG. 2). The N-channel pass transistor 34 has a source-drain path connected between the node S1 and the first bit line BL, and a gate connected to the word line WL. Similarly, the source-drain path of the N-channel bus transistor 36 is connected between the node S2 and the second bit line BL_, and its gate is similarly connected to the word line WL.

In operation, the voltages at nodes S1 and S2 are
Due to the cross-connectivity of CMOS inverters, they are always logical complements of each other. When word line WL is activated by X-decoder 6 shown in FIG. 1 according to the row address received at address input An, pass transistors 34 and 36 are turned on and nodes S1 and S2 are connected to bit line BL. And BL_ respectively. Accordingly, the state of the bit lines BL and BL_ is changed by utilizing the word line WL.
When 24 is connected to it, it becomes a mutual logical plural.

As described above in this embodiment, the array 2 in FIG.
There are six word lines WL and O1024 pairs of bit lines BL and BL_. For each value of the row address decoded by the X decoder 6, one word line WL is utilized, and 1024 memory cells 24 are connected to 1024 pairs of bit lines BL and BL_. Since the other 255 word lines WL are at a low logic level, only one memory cell 24 associated with the selected word line WL in each column is connected to the bit line pair BL and BL_ at a time. .

Referring now to FIG. 3, one column of array 2 is shown. Two memory cells 24 for clarity
Only two are shown with only word lines WL _n and WL _{n + 1,} but as noted above, each column has 256 memory cells 2
4 are associated with 256 separate word lines WL. In the example shown in FIG. 3, the cell 24 is shown connected to the complementary bit lines BL and BL_. Bit lines BL and BL_ are connected to the sense amplifier 10 of the first stage, also V respectively through the N-P- N pull-up transistors 38a and 38b _cc
It is connected to the. The pull-up transistor 38 is the first
This corresponds to the bit line pull-up 21 shown in the figure. The bases of the pull-up transistors 38a and 38b are driven by the pull-up control circuit 23.
23 receives the clocked input data on the data in bus 22 from the input / output circuit 20.

The first stage sense amplifier 10 has two emitter coupled N-
It comprises PN transistors 42a and 42b, and their bases are connected to bit lines BL and BL_, respectively. The emitters of transistors 42a and 42b are connected to the drain of N-channel transistor 45, whose source is connected to ground and whose gate is connected to line YSEL. Transistor 45 is turned off when the column is not selected (i.e., line YSEL is low) and turned on when the column is selected (i.e., line YSEL is high) to provide a current source. Operate. Line YSEL is also a P channel. Also connected to transistor 47, which serves to equalize bit lines BL and BL_ when transistor 47 is on because line YSEL is low. Line YSEL for a specific column
Is low during the cycle when no column is selected and bit line BL
And BL_ are equalized. The collectors of the transistors 42a and 42b are connected to the local data lines 16_ and 16, respectively. As described above in this embodiment, the 32 first-stage sense amplifiers 10 share the local data lines 16 and 16_. Local data lines 16 and 16_ are pulled up to _Vcc by resistor 44.

Write circuit for specific column is N-channel transistor
The source-drain paths 48a and 48b are connected to paths between the bit lines BL and BL_, respectively, and ground. N-channel transistors 48a and 48b
Are controlled by data-in lines 22_ and 22, respectively, and one data-in line is brought to a high logic level at the same time that a write operation occurs, while the data-in lines 22_ and 22
The choice between _ depends on the input data received at the input / output terminal I / O. During a read cycle, data in line 22 and
Both 22_ remain at a low logic level. N channel
Transistors 46a and 46b, on the other hand,
And 48b, or on the other hand, are connected in series between the bit lines BL and BL_, respectively. Transistors 46a and 46b
Are controlled by the axis YSEL so that the state of the data-in lines 22 and 22_ affects only one of the 1024 columns and is isolated from the other columns.

FIG. 4a shows the equivalent circuit of the selected column of FIG. 3 during a read operation. FIG. 5 is a timing chart showing the operation of the read cycle of the first cycle. During a read cycle, both data-in lines 22 and 22_ of FIG. 3 are at a low logic level. In response, the pull-up control circuit 23 transmits _Vcc to the respective bases (nodes A and B in FIGS. 4a and 5b) of the pull-up transistors 38a and 38b, thereby connecting the emitters of the transistors 38a and 38b. Voltage is V
Although set to be the same as _cc -V _BE, where V _be is the base - a forward-biased diode drop between the emitter connection. Memory cell selected by word line WL
24 represents the difference voltage on the bit lines BL and BL_. This description is for the case where the bit line BL is higher than the bit line BL_. Therefore, since the bit line BL is higher than the bit line BL_, the associated first-stage sense amplifier transistor
42a is turned on higher than transistor 42b associated with bit line BL_. Because transistor 45 is on, acting as a current source and keeping the sum of the currents through transistors 42a and 42b constant, the higher drive of the base of transistor 42a allows most of the current through transistor 45 to be compared to transistor 42b. And flows through the transistor 42a. For pull-up transistors 38a and 38b, the bit line BL becomes remains approximately V _cc -V _BE, as shown in FIG. 5, the bit line BL_ slightly voltage drops.

Transistor 42a conducts most of the current passing through transistor 45 compared to transistor 42b, so local data line 16_ is pulled down, but local data line 16 is for minimal drive through transistor 42b. Remains high. Each transistor of the other first-stage sense amplifier 10 sharing local data lines 16 and 16_
So that the only transistor turning off 45 and pulling down one of the data lines 16 and 16_ is the transistor 42 or 42b driven by the higher bit line BL or BL_ associated with the selected column. Become.

FIG. 4b shows an equivalent circuit during a write operation of the column shown in FIG. 3 constructed in accordance with the present invention. One of the data-in lines 22 or 22_ is pulled high by the input / output circuit 20 depending on the input data received at the input / output terminal I / O, but in the example described here, the data In line 22 is pulled to a high logic level for a write operation. This occurs at time t _w shown in FIG. 5. Therefore, the third
Transistor 48b in the illustrated column is turned on by data-in line 22, but because YSEL is asserted high for the selected column, as shown in FIG. Select the line BL_, pull it low, and execute the write.

In accordance with the present invention, the pull-up control circuit 23, depending on the data state to be written, different transmitted levels of the bias to the base of the pull-up transistors 38a and 38b, begins at time t _w at the start of the write operation. At the node B, that is, at the base of the transistor 38b, the pull-up control circuit
_ee , because the bit line BL_ to which the transistor 38b is associated will be pulled low due to the data-in line 22 being pulled up (rather than the data-in line 22_). . In accordance with the present invention, starting at time t _w, the pull-up control circuit 23 to the node A (base of the transistor 38a), applying a voltage obtained by subtracting from the bias applied during a read cycle. In the present embodiment, this applied voltage is
1 diode drop ( _Vbe ) below _Vcc to bias the base of Thus, on the "high" bit line (as opposed to the bit line pulled low, in this case bit line BL), pull-up transistor 38a is biased and conductive, while pull-up transistor 38a is conducting. The 38a emitter voltage is the reduced voltage for the read cycle. In this case, the voltage of the high bit line BL is during the write operation V _cc -2 V _BE, low bit line BL_ will be pulled up _ee V.

The write is accomplished when transistors 46b and 48b pull bit line BL_ to V _ee and the node of memory cell 24
This is because S2 (see FIG. 2) is set low, causing the cross-engaged inverter in memory cell 24 to latch the desired data state. The low level of the bit line BL_ turns off the transistor 42b of the first stage sense amplifier 10. Transistor 42a is transistor 45
(The base is a sufficient voltage V _cc -2 V _BE to leave you turn on the transistor 42a) is to conduct the entire current was allowed to pass through the, admitted to the base of the transistor 42a current, the bit line BL is limited to remain approximately the voltage V _cc -2V _be. The low level effect of bit line BL_ through transistors 46b and 48b is to disable first stage sense amplifier 10 and write the desired data to memory cell 24. When the parasitic capacitance of the node S2 and the bit line BL_ memory cell 24 is discharged, as shown in FIG. 5, the voltage of the bit line BL_ drops approximately to _ee voltage V.

The full benefit of the reduced bias of transistor 38a on high bit line BL during a write operation is asserted during the time after the write operation and before the read operation (ie, the write recovery time). While describing FIG. 5, the write cycle ending at time t _r, one of the data-in line 22 or 22_ (in this case line 22) starts made from a high logic level to a low logic level. Thus the transistor 48a is turned off, in this example, it is possible to bit line BL_ responds to the pull-up transistor 38b is separated from _ee V. Similarly, in response to data-in line 22 returning low,
The pull-up control circuit 23 returns the bias of the bases of the transistors 38a and 38b (nodes A and B, respectively) to _Vcc .
For bit lines that were low prior to the write cycle, e.g., bit line BL_, this biasing of pull-up transistor 38b causes the bit line BL_ to return to its original V Raise to _cc- Vbe. For bit lines that were high prior to the write cycle, e.g., bit line BL, biasing of pull-up transistor 38a causes bit line BL to be pulled from _Vcc -2V _be , as in the read cycle described earlier. And pull towards Vcc-V _be .

If the data state of the selected memory cell 24 is the same as that written by the write cycle,
The two bit lines BL and BL_ return to the difference voltage as shown in the first read cycle of FIG. No speed improvement has been demonstrated in this example, but this is due to bit lines BL and BL.
This is because the _ voltage does not cross before it locks in the read state. However, if the data read by the second read cycle is the opposite of the data written by the write cycle, the bit line will have a reduced bias due to the reduced bias of the base of the high side pull-up transistor 38 during the write cycle. voltage of BL and BL_ intersects the time immediately after t _r. In this case, shown in the second read cycle of FIG. 5, memory cells 24 in a different row than those written in the write cycle are read in the second read cycle (to read different data). It will be clear that

The high side bit line, in this case bit line BL, is pulled to a lower voltage (V _cc) by pull-up transistor 38a.
−2 V _be ) to the higher voltage (V _cc −V _be −dV, dV is the delta voltage because it is the low side bit line in reading), so the voltage on bit line BL and bit line BL The intersection with the voltage of _ occurs at the time t _s shown in FIG.
At the time of the crossing (t _s ), the first stage sense amplifier 10 flips to the appropriate data state as described above, which means that the high side bit line (in this case, bit line BL_) has its associated transistor This is because 42 is driven harder than the low-side bit line (BL) to drive to achieve reading. Before the high side of the bit line from the write (e.g., bit line BL) is, when falls from the same voltage V _cc -V _BE and the voltage during a read cycle, the intersection of the bit line BL_ to increase after t _s Time Does not occur until. Waveform shown in Fig. 5
BL ′ is the bit line BL when the write bias of the transistor 38a is the same during the write cycle and during the read cycle.
The latter intersection is shown as time t _s ′ in FIG. The improvement in access time by varying the bias of the high side pull-up transistor is the time difference between time t _s ' and time t _s .

Referring now to FIG. 6, there is shown the interconnection of a group of first stage sense amplifiers 10 with local data lines 16 and associated second stage sense amplifiers 14. As described above, the sense amplifier 10 ₀ through 10 ₁₀₂₃ 1024 First stage
Are collected into 32 groups, the sense amplifiers 10 ₀ through 10 ₃₁ of the first stage to the first group, ₃₂ to sense amplifier 10 of the first stage, is 10 ₆₃ collected in Fu that the second group Have been. Each group of first stage sense amplifiers
The outputs of 10 are wire-AND connected to a common pair of complementary local data lines 16 and 16_. First stage sense amplifier 1
Each pair of whereabouts data lines 16 and 16_ from one group of 0
The signal is transmitted to the input of the second stage sense amplifier 14 associated with the group. For example, the second stage sense amplifier 14 ₀
Receives local data lines 16 and 16_ from the sense amplifier 10 ₀ through 10 ₃₁ of the first stage.

One of the 1024 first-stage sense amplifiers 10 is selected according to the 10 bits of the column address, and the detection of the memory cell in the associated column in the selected row is performed. This selection involves transmitting only one select line YSEL (not shown in FIG. 6) to each first stage sense amplifier 10.
The address input An of FIG.
Depends on the value of the 10-bit column address received at.
The unselected first-stage sense amplifiers 10 are not enabled and pass high impedance to both corrected local data lines 16 and 16_. The sensing operation performed by a selected one of the first stage sense amplifiers 10 appears on local data line pairs 16 and 16_ by one of the pairs of lines being pulled low, which will be described below. This will be described in more detail.

The second stage sense amplifiers 14 corresponding to the group of the first stage sense amplifiers 10 including the first stage sense amplifiers 10 selected by the column address are enabled to use the local data lines 16 and 16_ Amplify the difference voltage transmitted there, and the amplified complementary data out lines 18 and 18_
To the difference voltage. This selection is performed by the second stage Y decoder 12.
Which in this example receives the five most significant bits of the column address, and one of the select lines SSL ₀ through SSL _{31 to} the second stage sense amplifier 14 allows it. To argue. Second stage sense amplifier
The output of 14 is both data-out lines 18 and 18_
R is connected. Unselected ones of the second stage sense amplifier 14 are disabled and a high impedance is transmitted to both data out lines 18 and 18_, causing the selected one of the second stage sense amplifier 14 to be selected. Are data out lines
It is possible to determine the states of 18 and 18_. As shown in FIG. 1, data out lines 18 and 18_ are received by input / output circuit 20 and transmitted to input / output terminals I / O.

Referring now to FIG. 7, the SRAM of this embodiment will be described with reference to FIG.
One column decoding and detection mechanism will be described. In accordance with this embodiment of the present invention and as described above with reference to FIG. 1, one first stage sense amplifier 10 is associated with each of the 1024 columns of array 2. These first-stage sense amplifiers 10 are composed of 32 first-stage sense amplifiers.
Gathered in 32 groups of 10. Referring to FIG. 7, the interconnection of the 32 first-stage sense amplifiers 10 in one group and the driving of the complementary local data lines 16 will be described.

The sense amplifier 10 ₀ through 10 ₃₁ of the first stage is shown schematically in Figure 7. Each of the first-stage sense amplifiers 10 includes a third
As shown, there are transistors 42a and 42b whose bases are connected to bit lines BL and BL_, respectively, and whose collectors are connected to location data lines 16_ and 16, respectively. The emitters of transistor 42a and transistor 42b are tied together and connected through transistor 45 to _Vee . Each first stage sense amplifier 10 has its transistor 45
Receive the only selection signal on the line YSEL from the first stage Y decoder 8. For example, the sense amplifier 10 ₀ of the first stage receives a line YSEL _0, it becomes Fu that sense amplifier 10 ₁ of the first stage receives a line YSEL _1. As described above, each of the 1024 first-stage sense amplifiers receives its own select signal on the associated line YSEL _n , but the SRAM 11 described herein is configured as a 256k × 1 memory. Here, n ranges from 0 to 1023. Therefore, only one of the first-stage sense amplifiers 10 is enabled to perform a predetermined read operation with the high logic level of the associated select line YSEL, and the other unselected first-stage sense amplifiers 10 are enabled. Amplifiers 10 receive the low logic level on their select line YSEL.

The group shown in FIG. 7, if not claimed by the Y decoder 8 none of the first stage of the line YSEL ₀ to YSEL _31, transistor 45 all of the first stage of the sense amplifier 10 ₀ through 10 ₃₁ Turn off. In this case, the resistor 44 is pulling the both local data lines 16 and 16_ in V _cc, which is any line be low not enabled anything the first stage of the sense amplifier 10 ₀ through 10 ₃₁ Because it is not reduced to

The first stage sense amplifier 10 of the group shown in FIG.
₀ to the case where one of the 10 ₃₁ is selected, the first stage sense amplifier 10 that are not selected for the group is still receiving a low logic level of the select line YSEL with which they are associated, the unselected Each of the transistors 45 of the first stage sense amplifier 10 is kept off. But,
For the selected one of the first stage sense amplifiers 10, a high logic level is received on its select line YSEL, transistor 45 is turned on, and the associated pair of bit lines BL
And the difference voltage between BL_ and BL_ can be detected.

For example, when a line YSEL ₁ for the first stage of the sense amplifier 10 ₁ selected becomes a high logic level, the first stage sense amplifier 10 ₁ of the transistor 45 is turned on. Therefore, as described above, one of the transistors 42a and 42b associated with the higher of _ the bit lines BL ₁ and BL ₁ are
Although the large turn-on than transistor 42a or 42b associated with the lower of _ the bit lines BL ₁ and BL _1, the data state polarity stored course memory cells 24 in the selected row of the differential voltage Dependent. If, for example, a memory cell 24 that is selected and compared to _ the bit lines BL ₁ stores data to a the bit lines BL ₁ to high, the first stage of the sense amplifier portion 10 ₁ of the transistor 42a Is turned on much more strongly than the transistor 42b there, and governs the conduction of current through the transistor 45, which acts as a current source. Transistor 42a is thus operates to lower the local data line 16_ but the sense amplifiers 10 ₀ and 1 of the cuts is the first stage that has not been selected local data line 16_
It is not strongly affected by 0 _{2 to} 10 _{31 because} these transistors 45 are off. Conductive through the first stage of the sense amplifier 10 ₁ of the transistor 42b becomes reduced due to the effect of the transistor 45, the local data line 16
Remains high, the first stage sense amplifier 10 ₁
Transmitting the result of the detecting operation in the second stage of the sense amplifier 14 ₀ by.

Referring now to FIG. 8, the configuration and operation of the second stage sense amplifier 14 will be described in detail. On the input side of the second stage sense amplifier 14, the local data line 16
Although connected to the base of the PN transistor 78a,
The transistor 78a has a collector connected to _Vcc , and an emitter connected to the base of the NPN transistor 867a and the drain of the N-channel transistor 70. Transistor 76a has a collector connected to _Vcc through pull-up resistor 80, and an emitter connected to the drain of N-channel transistor 72. Similarly, the local data line 16_ is connected to the base of an NPN transistor 78b, the collector of which is connected to _Vcc and the emitter of which is connected to the base of the NPN transistor 76b. It is connected to the drain of the channel transistor 74. Transistor 76b has a collector connected to _Vcc through another pull-up resistor 80, and an emitter
Connected to the drain of channel transistor 72. Transistors 70, 72 and 74 have their sources connected to _Vee . The line SSL from the second stage Y decoder 12 is connected to the gates of N-channel transistors 70, 72 and 74.

In operation, if the second stage sense amplifier 14 is not selected by the second stage Y decoder 12, line SSL will be low. Transistors 70, 72 and 74 are turned
It is turned off and none of the NPN transistors 78 and 76 conduct, regardless of the state of local data lines 16 and 16_. Therefore, nodes SA and SB, that is, transistor 76a
And 76b are each pulled to _Vcc through resistor 80 in an unselected state.

When the second stage sense amplifier 14 is selected, line SSL goes to a high logic state, turning on transistors 70, 72 and 74. In the selected state, the input of the second stage sense amplifier 14 is enabled to detect the difference voltage between the local data lines 16 and 16_. Transistors 78a and 7
8b transmits the respective voltages of local data lines 16 and 16_ reduced by the base-emitter diode drop (V _be ) to the bases of transistors 76a and 76b, respectively. The input side of the second stage sense amplifier 14 is thus
Operating similarly to the first stage sense amplifier 10, transistor 72 acts as a current source for emitter junction transistors 76a and 76b. In the above example, the local data line 16 is at a higher voltage than the local data line 16_,
Most of the current passing through 2 passes through transistor 76a rather than transistor 76b. Therefore, in this example, the node S
A is a voltage lower than the node SB.

Next, the output side of the second stage sense amplifier 14 will be described. In the P-channel transistor 88a, the node SA is connected to the drain, and the source is connected to the base of the NPN transistor 86a. I have. Similarly, node SB is P
It is connected to the drain of channel transistor 88b, the source of which is connected to the base of NPN transistor 86b. Transistors 86a and
86b has a collector connected to _Vcc and an emitter connected to the data out lines 18_ and 18, respectively. The bases of transistors 86a and 86 are also connected to the drains of N-channel transistors 92a and 92b, respectively, and the sources of transistors 92a and 92b are each connected to V _ee . Line SSL is inverted by inverter 82 and connected to the gates of transistors 88a and 88b. line
SSL is also connected to the gate of transistor 92. Each of the second-stage sense amplifiers 14 has a pair of N
There are channel transistors 94a and 94b, the source - drain path is connected between a respective and V _ee of data-out lines 18_ and 18. The output of inverter 82 is passed through an inverting delay stage 90 through a transistor
The gates of 94a and 94b are driven. Inverting delay stage 90 comprises a CMOS inverter having relatively small P-channel pull-up transistors and relatively large N-channel pull-down transistors. This allows the inverting delay stage 90 to have a substantial delay of only one transition, and the output of the inverting delay stage 90 will quickly transition from high to low for reasons explained below. , But the transition from low to high occurs relatively slowly.

During operation, if the second stage sense amplifier 14 is not selected, the output of inverter 82 will be at a high logic level. Therefore, transistor 88 is turned off and transistor
92 is turned on and _connects the base of transistor 86 to V _ee
To turn off. Accordingly, the second stage sense amplifier 14 applies a high impedance to the data out line 18.
And 18_, but note that the other three
The two second-stage sense amplifiers 14 have the data-out lines 18 and the same as the second-stage sense amplifiers 14 shown in FIG.
18_ is connected to. Transistor 9
4a and 94b are similarly turned off (in a steady state), and the unselected second stage sense amplifiers 14 pass a high impedance to the data out lines 18 and 18_. The connection of the 32 second-stage sense amplifiers 14 to the data-out lines 18 and 18_ is therefore of the wired-OR nature, with one of the second-stage sense amplifiers having one data line. The out-line 18 or 18_ can be pulled up, and the unselected one of the second stage sense amplifiers 14 essentially transmits a high impedance thereto.

When the second stage sense amplifier 14 is selected, the output of inverter 82 goes to a low logic level, turning on transistors 88a and 88b. Transistors 92a and 82b are turned off, allowing the full difference voltage at nodes SA and SB to be transmitted to the gates of transistors 88a and 88b, respectively. The voltages at nodes SA and SB are then subsequently connected to the bases of transistors 86a and 86b.

When line SSL goes high, the output of inverter 82 goes low and the output of inverting delay stage 90 eventually goes to a high logic level, turning transistors 94a and 94b on. However, as described above, the inverting delay stage 90 is configured to make a low-to-high transition at its output slowly. Inverter with delay stage 90
This delay between the output of 82 and the gates of transistors 94a and 94b causes transistors 86a and 86b to
The delay such that transistors 94a and 94b turn on at a time after starting to drive _ and 18 respectively. Delaying the turn-on of transistors 94a and 94b provides an improved access time if the data state communicated on data out lines 18 and 18_ is the same as the data communicated thereto during a previous read cycle. If, for example, the data out line 18 is driven high by another second stage sense amplifier 14 compared to the previous cycle data out line 18_, the data out line 18 is turned on before the transistor 94b is turned on. Need only maintain the same level already on data out line 18 to provide a fast output response. If transistor 94b turns on prior to transistor 86b turning on,
Data out line 18 is discharged to V _ee and transistor 86b must pull data out line 18 all the way back to its final output level, slowing the access time efficiency of SRAM1. Inverting delay stage 90 turns
When turned on, transistors 94a and 94b act as current sources, causing the voltages on data out lines 18 and 18_ to be at nodes SA and S.
It becomes possible to reflect the difference voltage of R. The voltages transmitted to data out lines 18_ and 18 are substantially the voltages at nodes SA and SB, respectively, shifted by the base-emitter diode drop of transistors 86a and 86b.

In the example described above, since the node SB has a higher voltage than the node SA, the data out line 18 has a higher voltage than the data out line 18_. Accordingly, the second stage sense amplifier 14 transmits the output of the selected first stage sense amplifier 10 to the input / output circuit 20 by detecting the data state of the selected memory cell 24. .

In the next cycle when a particular second stage sense amplifier 14 goes from a selected state to a non-selected state, line SSL goes low and transistors 70, 72, 74, 84a and 8
By turning off 4b and turning on transistors 92a and 92b, the bases of transistors 84a and 84b are pulled down. Inverting delay stage 90 will quickly turn off transistors 94a and 94b, which causes the output of inverting delay stage 90 to make a rapid high-to-low transition in response to the output of inverter 82. Can be inverted delay stage 90
Is configured.

Thus, while the present invention described above provides a reduced load on the first stage sense amplifier 10, it reduces the number of first stage sense amplifiers 10 into groups to form a pair of local data lines 16a. And by driving global data out lines 18 and 18_ with a second stage sense amplifier for each group selected by the most significant bit of the column address. I do.
This reduced drive makes it possible to provide a single first stage sense amplifier 10 for each column without the need for large drive transistors that can fit within the array column pitch. Become.

As described above in connection with FIG.
And 38b are biased to _Vcc during a read operation, whether or not a particular column is selected. Each of the pull-up transistors 38 is connected to a bit line BL or BL
Represents a diode between _ and the voltage at the base of transistor 38. When the base of the transistor 38 is connected to V _cc, a negative voltage bump V _cc is not connected to the bit lines BL and BL_, this is when the base voltage drops below the bit line voltage, Base of NPN transistor 38
This is because the emitter diode is reverse-biased.
However, if the power source _Vcc bumps upward, the base-
Since the voltage between the emitter junction remains at V _BE, the bit lines BL and BL_ follows the level V _cc of the higher. During a read operation, the low bit line BL or BL_, since the memory cell 24 that is selected keep it low, but not tend to be pulled up by the noise, higher bit line V _cc
Tends to follow the positive noise. Thus, the positive noise of the _Vcc power source produces a higher differential voltage between the bit lines than without such noise. If this noise is sufficiently high, the bit line difference voltage becomes very large, and the equalizing transistor 47 cannot equalize the bit line,
In the next cycle, the state of the selected memory cell 24 may be erroneously detected.

Referring now to FIG. 9, there is shown an equivalent circuit of another representation of the column of FIG. 3 during a read operation, wherein the pull-up control associated with each of the pull-up transistors 38a and 38b is shown. Other parts of the circuit 23 are also included. The pull-up control circuit 23 shown in FIG. 9 functions as a filter so that relatively high-frequency noise on the _Vcc power line does not reverse the equalization of the bit lines BL and BL_. Perform a low-pass filter operation.

During a read operation as described above in connection with FIG. 4a, depending on the data state of the selected memory cell 24, one bit line BL or BL_ will be high compared to the other. In the example shown in FIG. 9, the bit line BL is higher than the bit line BL_. The operation of the memory cell 24 and the first stage sense amplifier 10 depends on the selected transistor 4 acting as a current source.
5, and also including transistors 42a and 42b share the current passing through the transistor 45, the first current source through the current I _HI connected to the bit line BL of the higher and lower towards the bit line BL_ It can be made like a second current source passing through the connected current I _LO , but of course, if the opposite data state is stored in the selected memory cell 24, the equalization current sources I _HI and I _{H LO} is connected to the opposite bit lines BL and BL_. I
_HI is the transistor 42 in this example where the bit line BL is high.
It corresponds to the base current of a. I _LO corresponds to the current drawn from bit line BL_ (in this example) that a low logic state is conveyed by memory cell 24.

Included in pull-up control circuit 23 to bias the bases of transistors 38a and 38b to Vcc is
This is a low-pass filter including a resistor 50 and a capacitor 52.
This low pass filter allows nodes A and B to be biased for read operations, but filters out the higher frequency noise of the _Vcc power source and the noise at the _Vcc positive pole reduces to transistors 38a and 38a. Bit line BL through 38b
And BL_. The values of the resistor 50 and the capacitor 52 are such that the maximum rate of change of the voltage at the nodes A and B after filtering is such that the bit lines BL and BL_ are at the voltage displacement there via the equalizing current sources I _HI and I _LO. You must choose to be slower than responding. In this example, resistor 50 is 10
With a value of k ohms, the capacitor 52 is a MOS capacitor ranging from 15 pF to 20 pF.

FIG. 10 is a block diagram of a configuration of the pull-up control circuit 23. The pull-up control circuit 23 has two blocks 55a and 55
5b, and each of blocks 55a and 55b includes substantially identical circuitry therein. Block 55a is for driving node A, the base of pull-up transistor 38a, while block 55b is for driving node B, the base of pull-up transistor 38b. Block 55a is input and data in line 2
2_, and as described below, line INVB goes to block 55b
Generated by Block 55b similarly receives data-in line 22, and line INVA is
Generated by a.

Now, a detailed configuration diagram of the block 55a will be described with reference to FIG. Block 55b is similarly configured as described above. The data-in line 22_ is set to N by the block 55a.
At the gate of channel transistor 60 and also at the inverter
Received by 62 and 64. Inverters 62 and 64 are preferably implemented with a well-known pull-up CMOS
An inverter is good. The output of the inverter 62 is connected to the base of an NPN transistor 66,
Is connected to the base of an NPN transistor 68. Transistors 66 and 68 have their collectors biased by _{Vcc and} are tied together in a known Darlington configuration, with the emitter of transistor 66 driving the base of transistor 68. The emitter of transistor 68 is connected to the output of block 55a, node A. The combination of inverters 62 and 64, and Darlington transistors 66 and 68, serve as fast pull-up circuits and are described in U.S. Patent Application No. 158,004, filed February 16,1988. This pull-up circuit presents the logical complement of the state of data-in line 22_ at node A.

On the pull-down side, the source-drain path of transistor 60 is connected between node A and V _{ee in} series with the source-drain path of N-channel transistor 70. The gate of transistor 70 is connected to node A. The junction between transistors 60 and 70 is an N-P with an collector connected to node A and an emitter connected to _Vee.
-N Connected to transistor 72. Transistor 6
The pull-down circuits of 0, 70, and 72 serve to quickly pull node A down when the logic state of data-in line 22 switches from a low logic level to a high logic level.

The output of inverter 64 is also connected to a first input of NAND gate 74, while the other input of NAND gate 74 receives line INVB from block 55b of pull-up control circuit 23. The output of inverter 62 is connected to line
Block 55b in the NIVA logic state pull-up control circuit
Tell Line INVA is connected to the input of a NAND gate in block 55b, which is located similarly to NAND gate 74 in block 55a, and line INVB is located, like inverter 62 in block 55a. Note that it is driven by the inverter in block 55b. Such an interconnect helps cross-coupling blocks 55a and 55b control various read and write states as described below.

NAND gate 74 drives the gate of P-channel transistor 76, the gate of P-channel transistor 78, and the gate of small N-channel transistor 80. Transistor 76 has a source-drain path connected between _Vcc and node A, and transistor 78 has a source-drain path connected between _Vcc and node A in series with filter resistor 50. ing. The transistor 80 has a source-drain path connected between the node A and _Vee . Further provided in connection with the reduction filter of the resistor 50 and the capacitor 52 is an N- diode connected in a diode configuration.
PN transistors 82 and 84. Transistor 82 has its collector and base connected to _Vcc and its emitter connected to the source of transistor 80, while transistor 84 has its collector connected to the source of transistor 80 and its base and emitter connected to _Vcc. Connected to _cc . Thus, if transistor 78 is on during a read operation (as described below), transistors 82 and
84 acts as a reverse diode between _Vcc and node A,
The difference voltage between them is prevented from rising to an influential one.

In operation, block 55a, depending on the type of cycle performed by SRAM1, performs a 4a by a low pass filter provided during a read cycle as shown in FIG.
And serves to exhibit the voltage node A described above with respect to FIG. 4b. During a read cycle, data-in lines 22 and 22_ are both at a low logic level, as described above. With respect to block 55a, the low data-in line 22_ turns off transistor 60 and subsequently turns off transistor 72. Inverters 62 and 64 both represent a high logic level at the output, turning off both transistors 66 and 68. As described in the aforementioned U.S. Patent Application No. 158,004, a transistor 66 in Darlington configuration
And the operation of 68, such that node A quickly begins to charge to the full _Vcc level, ie, the full level due to bootstrapping from the parasitic junction capacitance of the base-emitter junction of transistor 68. Inverter 64
Also outputs a high level to NAND gate 74, and the output of inverter 62, after being delayed by delay stage 63,
Tell INVA.

Since the data-in line 22 is also low,
Since block 55b is configured similarly to block 55a, line INVB from block 55b is also high at the second input to NAND gate 74. The output of NAND gate 74 is therefore low, turning on P-channel transistors 76 and 78. P-channel transistor
76 therefore helped raise node A to _Vcc , NAND
Node A is held at this level until a change in the output of gate 74 occurs. Transistor 78 is connected to V as described in FIG.
_In order to filter out the high frequency noise of the _cc power source line, the reduction filter of the resistor 50 and the capacitor 52 is connected to the node A.
Help to connect to. Diodes 82 and 84 limit the potential difference between _Vcc and node A when transistor 78 is on, as described above. Transistor 80 is of course kept off during the read cycle by the output of NAND gate 74. Resistor 50 and capacitor 52
To gate A is gated by transistor 78 in block 55a, so if multiple pull-up control blocks are provided to other bit line pairs of SRAM1, block 5
The filter circuit of 5a is shared with block 55b or with additional blocks 55a and 55b. This sharing is transistor 78
Can be achieved by connecting the source node of this to the source of a transistor similarly located in another block.

Bit line BL is such that the low level, i.e., in the write cycle, such as the data lines 22_ goes high as shown in FIG. 3, the node A will be biased to _ee V. In the circuit of the block 55a shown in FIG. 11, this is achieved by turning on the transistor 60 on the data-in line 22_ which goes high. Transistors 70 and 72 are quickly turned on by bipolar transistor 72, such that if node A was initially high, node A would be quickly discharged through bipolar transistor 72. be able to. In addition, the outputs of inverters 62 and 64 go low, turning off transistors 66 and 68 and, via NAND gate 74, ensuring that transistors 76 and 78 are off. Thus, node A is pulled to V _ee by block 55a if data-in line 22_ goes high, causing bit line BL associated with transistor 38a (driven by node A) to be in a write operation. Means being lowered. The output of inverter 62 is transmitted to the input of the NAND gate of block 55b, as well as to NAND gate 74, and is coupled to node B in the manner described below for block 55a.
To achieve a bias.

As bit line BL_ is pulled low, i.e. data line 2
In the case of a write cycle where 2 goes high, node A will be in accordance with the invention as described above in connection with FIG. 4b.
It will _be biased to _Vcc- Vbe. In this case, the data-in line 22_ goes low, turning on transistors 66 and 68 and turning off transistors 60, 70 and 72, as in the read cycle described above.
However, since data-in line 22 is at a high level, block 55b carries the low logic level of line INVB to the second input of NAND gate 74, which is arranged similarly to inverter 62 of block 55a. Have a low output due to the data-in line 22 being at a high logic level. Thus, in block 55a, the output of NAND gate 74 goes high (one of its inputs is low), thereby turning off transistors 76 and 78 but turning on transistor 80, through which node Connect A to _Vee .

However, as described above, transistor 80 is a relatively small transistor and tends to result in a resistive load on the Darlington pair of transistors 66 and 68. This resistive load causes the circuit of transistors 68 and 80 with node A at the junction between them to operate as an emitter follower. After any bootstrapping decay of the base of transistor 68, the base of transistor 68 is at the _Vcc potential driven by CMOS inverter 64. Thus, the emitter of transistor 68 is at node A because transistor 80 acts as a pull-down load on it,
It becomes V _cc -V _be. Thus, the block 55a is a node A, i.e. the base of transistor 38a of FIG. 4b operates to bias voltage of V _cc -V _BE, than this voltage, the voltage to node A which is biased during read cycle Is also low. Thus, the intersection reaches an early time when the read cycle begins following the write operation, as shown in FIG.

The delay of delay stage 63 is used to allow the intersection of bit lines BL and BL_ to occur early during a read cycle following a write cycle. Line INV to block 55a
(Conversely, the lines INVA to the block 55b) to B by the delay imparted, P-channel transistors 76 and 78, the data state associated pull-up transistor 38 is driven to V _cc -V _BE Following a write cycle, it can be left off. For example, if (block 55a and is configured in the same manner) blocks 55a to bias the node A to V _cc -V _BE during a write cycle, and the line 22 to the block 55b is reliably read back to the low state If possible, leave transistor 76 and 78 off, preferably during a period while bit line BL_ is being charged during a read operation, node A immediately goes from V _cc −V _be to full V _cc level. It is preferable to prevent it from being pulled. As shown in FIG. 5, if the node A becomes V _cc prior to the node B, the bit lines BL reaches its final level in the early time after t _r. However, the fast intersection according to the present invention is the bit line BL
At the lower voltage during a write cycle than during a read (in the case of the present invention), which allows an intersection to occur while both bit lines BL and BL_ are being charged. . Crossing at time t _s, the bit line BL is if it occurs after the fully charged to its final level by the memory cell 24 is delayed. The longer the delay, the lower the voltage on the bit line BL at the intersection, and therefore the sooner the bit line BL_ reaches the voltage on the bit line BL. Of course, the delay amount of the delay stage 63, when the reading of the opposite data state to that shown in FIG. 5, namely the bit line BL is V _cc after the bit line BL_ is charged to "zero" detection level - If the delay is long enough to _be kept at 2V _be , it cannot be long enough to produce a pseudo-crossing. Note that the delay of delay stage 63 can alternatively be configured in various ways other than that shown in FIG. 11, such as by deriving a signal from node A.

As described herein, block 55a is 1024 of SRAM1
For the entire column, it can operate to control the bias of the pull-up transistor 38a and block
55b can operate to control the bias of pull-up transistor 38b for all 1024 columns of SRAM1. Alternatively, the 1024 columns may be divided into column groups where a pair of blocks 55a and 55b are provided for each group of columns. If providing multiple blocks 55a and 55b, each serving only one group of columns of SRAM1, decoding and selecting circuits may be provided in each of blocks 55a and 55b to provide a column group including the selected column and All blocks 55 except the related block pair 55a and 55b
a and 55b are selectively disabled. Block 55a whose use has been banned if possible due to such bans
And 55b may be placed such that the base of pull-up transistor 38 is biased to _Vcc during a write operation to another group of columns.

As described above, the present invention provides a pull-up control circuit that improves the reliability of data storage in a memory device and improves its performance. The increased reliability is particularly provided for memory devices in environments where the _Vcc power source is noisy, but such increased reliability is due to the film included in the pull-up control circuit 23. The improved performance provides for improved read access time of the cycle following the write operation, because the pull-up control circuit biases the pull-up transistor during the write cycle to a lower voltage than during the read cycle. Things.

Further, it should be noted that the embodiments described above are for structures where each column has its own first stage sense amplifier. The benefit of the present invention of reducing the effect of power source noise on bit line voltage and biasing the bit line during a write operation to provide improved write recovery is when the multiple columns share a single sense amplifier. Can be adapted to the structure.

Although the present invention has been described in connection with a preferred embodiment thereof, it is to be understood that this description is by way of example only and not by way of limitation. Furthermore, it is to be understood that many changes in detail of embodiments of the present invention, and additional embodiments of the present invention, will be apparent to those skilled in the art upon reference to this description. These modifications and additional embodiments are intended to be included within the spirit and true scope of the invention as set forth in the appended claims.

 In connection with the above description, the following items are further disclosed.

(1) A read / write memory, comprising an array of memory cells arranged in rows and columns, an address buffer for receiving an address signal, and a row address of the address signal connected to the address buffer. A row decoder for selecting a row of the array in response to a plurality of first stage sense amplifiers assembled in a first group and a second group; An amplifier associated with a column of the array; a first location data bus connected to each first stage sense amplifier of the first group; and A second local data bus connected to the first stage sense amplifier, a data out bus, and a first second data bus connected to the first local data bus and the data out bus. Stage A second second-stage sense amplifier connected to the second local data bus and the data-out bus; and a column of the address signal, the column being connected to the address buffer. Column decoding means for selecting a first stage sense amplifier in response to an address portion, wherein the column address portion of the address signal used by the column decode means to select a first stage sense amplifier. And the second stage sense amplifier is selected in response to the column address portion of the address signal. Column decode means for transmitting the output of the first stage sense amplifier selected by the column decode means to the data out bus.
Write memory.

(2) In the memory described in the item (1), the column decoding means receives a predetermined number of most significant bits of a column address portion of the address signal from the address buffer, and responds to the second stage in response to the reception. A second-stage column decoder for selecting a sense amplifier; and a column address portion of the address signal received by the second-stage column decoder from the address buffer. A first-stage column decoder that receives a predetermined number of most significant bits and selects a first-stage sense amplifier in response thereto;

(3) an array of memory cells arranged in rows and columns, each column of the array being associated with a true and a plurality of bit line pairs; an address buffer for receiving address signals; A row decoder connected to the address buffer for selecting a row of the array in response to a row address portion of the address signal; and a column for selecting a column of the array in response to a column address portion of the address signal In a read / write memory of the type having a decoder, the improvement comprises a plurality of first stage sense amplifiers assembled in a first group and a second group, each said first stage sense amplifier. An amplifier connected to the true and complement bit lines associated with the columns of the array; and an amplifier connected to each of the first stage sense amplifiers of the first and second groups, respectively. First and second local data buses, a data out bus, and a first second stage sense amplifier connected to the first local data bus and the data out bus A read / write memory including a second second stage sense amplifier connected to the second local data bus and the data out bus, wherein the column decoder is configured to store a column address of the address signal. Responsive to a predetermined number of most significant bits of the column address portion of the address signal used to select the first stage sense amplifier. The second stage sense amplifier is also selected and the selected second stage sense amplifier applies a voltage corresponding to the polarity of the difference voltage of the true and complement bit lines associated with the selected column to the data out bus. Read to tell / Write memory.

(4) In the improved memory described in (3), the column decoder receives a predetermined number of most significant bits of a column address portion of the address signal from the address buffer, and responds to the second stage. A second stage column decoder for selecting a sense amplifier, and a column address portion of the address signal received by the second stage column decoder from the address buffer. A first stage column decoder for receiving, including the most significant bits of the number, and selecting a first stage sense amplifier in response.

(5) an array of memory cells arranged in rows and columns;
A row decoder receiving a row address signal and responsively selecting a row of the array of memory cells; and a column decoder receiving a column address signal and responsively selecting a column of the array of memory cells. Read / write memory of the type having the data of the memory cells of the selected column in the selected row during the read operation, and the memory of the selected column in the selected row during the write operation The read / write memory device operable to write input data to a cell, wherein each column of memory cells of the array shares true and complement bit lines, and the memory device further comprises: In communication with a bit line in a column of the array selected by a decoder and stored in a memory cell of the selected column in the selected row. A sense amplifier for detecting the data that has been sensed in response to input data in a first logic state during a write operation, biasing a true bit line of a selected column to a predetermined voltage, A write circuit responsive to input data in a logic state to bias a complemented bit line of a selected column to the predetermined voltage; and a first pull-up transistor for each true bit line in each column. Wherein each said first pull-up transistor has an emitter connected to its associated true bit line, a collector connected to a power source contact, and has a base; and A second pull-up transistor for each complement bit line, wherein each said second pull-up transistor is an emitter connected to its associated complement bit line and a collector connected to the power source contact. And a motor,
And a base connected to the first and second pull-up transistors, wherein both the first and second pull-up transistors are biased on during a read operation; and One of the first and second pull-up transistors of a selected column during a write operation is biased to a lower voltage than the on state during a read operation, and the other is turned off during a write operation. A read / write memory device including a biased pull-up control circuit.

(6) The read / write memory described in (5)
In the device, the write circuit is responsive to input data of a first logic state during a write operation to bias the true bit line of a selected column to a low voltage, and a second logic state during a write operation. A read / write memory device for biasing said complement bit lines of a selected column to a low voltage in response to input data of a selected column.

(7) The read / write memory described in (6)
In the device, the pull-up control circuit biases the first pull-up transistor of the selected column off, such that the first pull-up transistor is in response to input data of the first logic state than in an on state during a read operation. Biasing the second pull-up transistor of the selected column to a low voltage, and the pull-up control circuit biasing off the second pull-up transistor of the selected column, A read / write memory device for biasing the first pull-up transistor of the selected column to a lower voltage than an on state during a read operation in response to input data of a second logic state.

(8) The read / write memory described in (5)
In the device, the pull-up control circuit may also include:
During a write operation, depending on the logic state of the input data, the first and second pull-up transistors of the unselected columns that are biased on to a lower voltage than an on state during a read operation. Read / write memory device, one of which is biased and the other is biased off.

(9) an array of memory cells arranged in rows and columns;
A row decoder for receiving a row address signal and responsively selecting a row of the array of memory cells; and a column decoder for recognizing a column address signal and selecting a column of the array of memory cells in response. Detection and output circuitry for presenting data of a selected column of memory cells in a selected row during a read operation, and input data to a selected column of memory cells in a selected row of a write operation during a write operation In a read / write memory of the type having a write circuit for writing the data, each column of the memory cells of the array shares a true and complement bit line, the improvement is that each true A first pull-up transistor for each bit line, each said first pull-up transistor having an emitter connected to its associated true bit line And a collector connected to the power source contact and having a base; and a second pull-up transistor for each complement bit line of each column, wherein each said second pull-up transistor A transistor having an emitter connected to its associated complement bit line and a collector connected to the power source contact;
A pull-up control circuit connected to the first and second pull-up transistors, the pull-up control circuit being connected to the bases of the first and second pull-up transistors; A bias circuit in which both first and second pull-up transistors are biased on during a read operation; and a connection between the power source contact and the base of the first and second pull-up transistors. And a pull-up control circuit including a low-pass filter.

(10) an array of memory cells arranged in rows and columns;
A row decoder receiving a row address signal and responsively selecting a row of the array of memory cells; and a column decoder receiving a column address signal and responsively selecting a column of the array of memory cells. Read / write memory of the type having the data of the memory cells of the selected column in the selected row during the read operation, and the memory of the selected column in the selected row during the write operation The read / write memory device operable to write input data to a cell, wherein each column of memory cells of the array shares true and complement bit lines; and wherein the memory device further comprises: In communication with a bit line in a column of the array selected by a decoder and stored in a memory cell of the selected column in the selected row. A sensor amplifier for detecting the data that has been detected, and responsive to input data of a first logic state during a write operation, biasing a true bit line of a selected column to a predetermined voltage, and A write circuit responsive to input data in a logic state to bias a complemented bit line of a selected column to the predetermined voltage; and a first pull-up transistor for each true bit line in each column. Wherein each said first pull-up transistor has an emitter connected to its associated true bit line, a collector connected to a power source contact, and has a base; and A second pull-up transistor for each complement bit line, wherein each said second pull-up transistor is an emitter connected to its associated complement bit line and a collector connected to the power source contact. And a motor,
And a base connected to the first and second pull-up transistors, wherein both the first and second pull-up transistors are biased on during a read operation; and One of the first and second pull-up transistors of a selected column during a write operation is biased to a lower voltage than the on state during a read operation, and the other is turned off during a write operation. A biased pull-up control circuit, wherein the pull-up control circuit biases a base of the first pull-up transistor and receives a first data-in signal; a feedback input; A delayed feedback output presenting a delayed signal corresponding to the logic state of the IN signal; A first block having a bias output coupled to the first block, a data input for biasing the base of the second pull-up transistor and receiving a second data-in signal, and a feedback of the first block. A feedback input connected to the output, a delayed feedback output connected to the feedback input of the first block, the delayed feedback output presenting a delayed signal corresponding to a logic state of the second data-in signal, and the second pull-up. And a second block having a bias output connected to the base of the transistor.
Write memory device.

(11) BiCMOS static random access
A memory (SRAM) is disclosed, which has first and second stage sense amplifiers. Each column of the memory array 2 is associated with a first stage sense amplifier 10, the first stage sense amplifiers being arranged in groups, each group being wired to a pair of local data lines 16. Connected by AND method. Using the column address, one of the first stage sense amplifiers is selected to detect the state of the memory cells 24 in the selected column. One second stage sense amplifier is associated with each group of first stage sense amplifiers and a second stage sense amplifier associated with the group including the selected first stage sense amplifier. Are selected according to the most significant bit of the column address. The second stage sense amplifier is connected to the data out bus 18 in a wired-OR fashion, and the output of the selected second stage sense amplifier drives the data out bus. The disclosed memory further comprises:
There is a pull-up control circuit 23 responsive to the input data bus 22. This control circuit is provided to control the bias of the base of the pull-up transistor 38 so that during a read cycle, the base of the pull-up device associated with the low side bit line is biased for reading. Biased to a voltage lower than the voltage to the base of the bit line, thereby reducing the time the bit line voltage crosses for reading the opposite data state. The pull-up control circuit further includes low-pass filters 50 and 52 to reduce the influence of power supply noise on the bit line difference voltage.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a static random access memory (SRAM) incorporating the present invention. FIG. 2 is a schematic circuit diagram of a conventional CMOS memory cell such as can be used for the SRAM of FIG. FIG. 3 is a schematic circuit diagram of a bit line pull-up circuit and a bit line pair associated with a first stage sense amplifier. 4a and 4b are schematic circuit diagrams illustrating the biasing of the pull-up transistors for read and write cycles according to the present invention. FIG. 5 is a timing diagram illustrating the operation of the column of FIG. 3 during a read and write cycle. FIG. 6 is a block circuit diagram illustrating the interconnection of the first and second stage sense amplifiers. FIG. 7 is a schematic circuit diagram of the interconnection of a group of first stage sense amplifiers to a pair of local data lines. FIG. 8 is a schematic circuit diagram of the second stage sense amplifier. FIG. 9 is a schematic circuit diagram of a circuit configured in accordance with the present invention to reduce the effect of power supply noise on the bit lines of FIG. FIG. 10 is a block circuit diagram illustrating the configuration of the pull-up control circuit of the present invention. FIG. 11 is a schematic circuit diagram of one of the blocks of the pull-up control circuit configured according to the present invention. Explanation of main symbols 2: Memory array 10: First stage sense amplifier 14: Second stage sense amplifier 16: A pair of local data lines 18: Data out bus 22: Input data bus 23: Pull Up control circuit 24: Memory cell 38: Pull-up transistor 50, 52: Low-pass filter

Claims (1)

(57) [Claims] 1. A memory device having a sense amplifier in communication with a bit line of a column of a memory array selected by a column decoder to sense data stored in a memory cell of a selected row. Biasing the true bit line of the selected column to a predetermined voltage in response to the input data of the first logic state of the write operation, and setting the complementary bit line of the selected column to the write operation. A write circuit for biasing to the predetermined voltage in response to input data of a second logic state; and a first pull-up transistor for each true bit line in each column. Each of the first pull-up transistors has an emitter connected to its associated true bit line, a collector connected to a power supply node, and a base;
And a second pull-up transistor for each complementary bit line in each column, each of the second pull-up transistors being connected to an emitter connected to its associated complementary bit line and to a power supply node. With a collector and a base,
And a pull-up control circuit connected to the bases of the first and second pull-up transistors, whereby the first and second pull-up transistors are biased to a read operation ON state, and further selected. The first of the
And a second pull-up transistor, one of which is biased on to a lower voltage than the on state in the read operation and the other is biased off according to the logic state of the input data.