JP2838156B2 - Self-tuning direct coupling data limiter for battery saver paging receiver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a battery saver type paging receiver and its data limiter section, and more particularly, to its mode control operation, digital words of acquired peak and minimum amplitude values. An improved peak and minimum amplitude detection data limiter section with storage and self-tuning capabilities.

In a paging system, the paging signal is transmitted from the paging transmitter, for example, to serial digitally encoded synchronization, address, and message data.
It is transmitted from a paging transmitter to a number of portable, battery-operated paging receivers according to a pre-specified modulation format including words. Each paging receiver includes an input stage that receives and demodulates the paging signal and serially couples the paging signal with a DC bias level that depends on characteristics of both receiver circuitry and modulation. Convert to an analog signal with changing AC content representing digitally coded modulation data.

The next stage of the paging receiver, commonly referred to as a data limiter section, compares the recovered analog signal in time with a threshold signal, each of which has a magnitude of the analog signal. A DC component of the analog signal to generate first and second amplitude signals representing one and the other binary states during periods above and below a set threshold level. The serially generated binary state is intended to be set to a magnitude and represents bits of a digitally encoded word of the paging signal.

Since it is not possible to perform the ideal superheterodyne and demodulation functions at the input stage, the DC level cannot be considered fixed, but rather recognized as relative to the recovered paging signal. Was done. As a result, it has been recognized that the threshold level of the data limiter cannot be simply set to a fixed value, but rather must be obtained dynamically from the direct paging signal. Previously, interface circuits using coupling capacitance were used to convert instantaneous DC signals from restored analog signals.
Used to remove the component, whereby the remaining AC component could be compared with a fixed level in time to convert the recovered analog signal into a serial stream of binary bits of data .

However, these capacitively coupled circuits have been found to be incompatible with the operation of battery saving techniques commonly used in battery operated paging receivers. For a more detailed understanding of the disadvantages of capacitively coupled data limiter circuits, see Walter
1986 against Walter L. Davis and others
See U.S. Patent No. 4,631,737 issued February 23 and assigned to the same assignee as the present invention. No. 4,631,737 to Davis et al. Uses dynamically as an instantaneous DC level of a reconstructed analog signal for use as a threshold level when converting the AC component to its corresponding binary bit serial form. Directly coupled data limiter circuits that use peak and minimum amplitude detectors. By removing the coupling capacitance, Davis et al.'S direct coupling circuit can be operationally compatible with the paging receiver's battery saving cycle, even though it requires significant time to obtain the threshold level. .

More specifically, most paging transmission formats use digitally encoded words to synchronize the operation of the various paging receivers with subsequently transmitted digitally encoded addresses in the transmission cycle. (Sync word). The paging receiver is customarily pre-programmed with a slot of the synchronization word and a slot in which the corresponding address for the synchronization word is expected to be transmitted. For example, as shown in time waveform A of FIG. 1, the synchronization word is transmitted in slot 0 of the transmission cycle and the selective call address of our hypothetical paging receiver is pre-programmed to appear in slot 5 accordingly. I have. Ideally, in this case, the selection circuitry of the paging receiver would be disabled or put into "sleep" when not needed and only activated or "awake" during the expected slot of the sync word and corresponding address. "
Such an example is shown in the time waveform B of FIG.

The battery saving technique of the paging receiver is to match the sleep and awake periods as closely as practically possible to the ideal case as shown in time waveform B of FIG. 1 to provide battery power to the selected circuit. Explore optimizing control. One practical limitation on this desired optimization results from the use of the peak and minimum amplitude detection data limiter circuit, where it is necessary for subsequent binary conversion. A significant amount before the binary conversion to statistically ensure that at least one peak and at least one minimum occur in the recovered analog signal during the acquisition of the instantaneous threshold level Time is needed.

Another limitation stems from the use of capacitance in the data limiter circuit to store the peak and minimum signals obtained for subsequent binary conversion. Since it is a well-known phenomenon that the signal stored in the capacitance decays with time due to leakage of the capacitance, and because the time between binary conversions is not predictable in all situations, it has been transmitted until now. It was considered prudent to re-reserve new peak and minimum signals and corresponding new threshold levels just before each possible synchronization and address word slot in the cycle. This method is shown by the shaded period in the time waveform C in FIG. Thus, in most battery saver paging receivers today, a significant amount of battery energy is consumed for this purpose, rendering their battery saving performance less than optimal.

Thus, the intent of the present invention is to achieve a longer operating life of the paging receiver over the useful life of the paging receiver's battery source, with a peak and a minimum to approach operationally ideal battery energy conservation practices. An object of the present invention is to improve the above-mentioned limitation of the amplitude detection data limiter circuit.

A battery saver paging receiver receives a paging signal, modulated by a digitally coded data word and transmitted from an external source, and is digitally coded by demodulating the received paging signal. Includes an input section for recovering an analog signal representing a data word. The data limiter section of the paging receiver converts the recovered analog signal into a corresponding binary bit stream representing the coded data words of the paging signal. The battery saver section of the paging receiver physically activates and deactivates the input and data limiter sections from battery power during the awake and sleep periods, respectively.

According to the invention, the data limiter section operates in a first mode to obtain a peak amplitude from the recovered analog signal and to generate a first digitally encoded word representing it. A second means operable in said first mode to obtain a minimum amplitude from the reconstructed analog signal and to generate a second digitally coded word representative thereof. The first and second means each include a first storage means for storing a first digital word and a second storage means for storing a second digital word. The first and second means operate in a second mode for storing their respective storage means in their respective digital words.

Further, the first and second means may each further include a third
And the first and second digital words can be changed by a predetermined count. In one embodiment, the first digital word is decremented by a single count and the second digital word is incremented by a single count in the third mode.

Further, the data limiter section may include control means for controlling transfer of operation of the first and second means during the first, second, and third modes in response to at least one command signal. it can. In one embodiment, the control means is managed by a reference clock signal when controlling the transfer between the modes of the first and second means. In yet another embodiment, the control means can control the first and second means to a third mode of operation during the transfer from the second mode to the operation of the first mode. .

Further, the first and second modes can be operatively correlated with the awake and sleep periods of the battery saver section. In another embodiment, the first and second storage means of the data limiter section are activated during a sleep period of the battery saver section to hold the first and second digital words stored therein, respectively. Be left standing.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 includes time waveforms A, B and C illustrating the battery saving operation of a paging receiver including a direct coupling data limiter section.

FIG. 2 is a block circuit diagram of a paging receiver suitable for implementing the principles of the present invention.

FIG. 3 is a block circuit diagram of a peak and minimum detection type data limiter suitable for use in the embodiment of FIG.

FIG. 4 is a logic circuit diagram of an oscillator and controller suitable for use in the embodiment of FIG.

FIG. 5 is a state diagram showing the various operating modes of the embodiment of the data limiter of FIG. 3 and the logic states for performing transitions between them.

FIG. 6 is a time waveform chart for explaining the management in the case of controlling transfer between various operation modes of the data limiter by the reference clock signal of the controller shown in FIG.

Description of the Preferred Embodiment Referring to FIG. 2, a traditional paging receiver antenna 10 is coupled to a receiver / demodulator input stage 12 using a signal line 14. Input section 12 is coupled to a peak and minimum detectable data limiter, indicated by dash-dot line 16, using signal line 18. The data limiter 16 is coupled to the decoder section 20 using a signal line 22. Battery power is indirectly input to switch 1 through switch S1, shown as B +.
2, and to a selected one of the data limiters 16 and decoders 20 using the signal lines 24 and also directly through the signal lines 26 to the data limiters 16 and the decoders 20.
Is coupled to other circuits. A traditional battery saver circuit 28 is coupled to switch S1 by signal line 30 for its power interruption control according to the awake and sleep periods of the battery saving cycle indicated by time waveform B in FIG.

More specifically, the data limiter section 16 includes a peak detection circuit 32, a minimum detection circuit 34, and a comparison circuit 36. Signal line 18 is coupled to one input of comparison circuit 36 and to the inputs of detection circuits 32 and 34. The outputs of the peak and minimum detection circuits 32 and 34 are coupled to respective ends of a resistor divider network with resistors R1 and R2. The connection node 38 between the resistors R1 and R2 is a comparison circuit
36 are tied to the other inputs. The output of comparison circuit 36 is coupled to decoder 20 by signal line 22.

Circuit family used in constructing the paging receiver, i.e. the type of circuit, for example either a bipolar circuit as if I ² L is a CMOS, depending on the battery power source B + is a voltage or current source Is done. For example, CMOS
If the circuit type of the voltage driving transistor is used, the power supply B + is a voltage source, and conversely, for example,
If a circuit type of the current driving transistor is used, such as the integrated injection logic I ² L, B + is a current source. further,
If power supply B + is depicted as being directly coupled to certain circuits of data limiter 16 and decoder 20 via signal line 26, current and / or current to these circuits during certain periods of battery saver control The voltage supply is considerably reduced but not completely interrupted. In a typical operation, a paging signal containing modulated digitally coded and digital words transmitted from an external source is received by antenna 10 and directed via signal line 14 to input section 12; There, the analog signal is reconstructed, adjusted by the traditional receiver and demodulation circuit, which is directed by signal 18 to data limiter section 16. The reconstructed analog signal includes a DC component representing the modulation reference level and an AC component that depends on the characteristics of the receiver circuit 12 and the modulated digitally encoded data word.

As described with respect to the time waveforms A and B of FIG. 1 in the previous background section, the battery saver circuit 28 cycles the input section 12 and selected circuits of the data limiter 16 and decoder 20 during the awake and sleep periods, respectively. The switch S1 is closed and opened for the purpose of energizing and de-energizing. Therefore, input section 12
Operates to output a restored analog signal that is directed to the data limiter 16 via the signal line 18 only during the awake period of the battery saver 28. In addition, the awake and sleep periods of the battery saver controller 28 are strongly correlated with the expected time slots of the sync word and pager addresses shown in FIG.

During the energized awake period, peak detector 32 generates an analog signal Vp that obtains and represents the peak amplitude from the recovered analog signal. At the same time, a minimum detection circuit obtains a minimum amplitude signal from the activated and restored analog signal and generates an analog signal Vv representative thereof. Signals Vp and Vv
Is averaged by resistor divider networks R1 and R2 to produce a threshold analog level Vth at node 38, which is compared in time with a reference analog signal in comparison circuit 36 and activated. Generating a serial binary bit data stream representing a modulated data word corresponding to a time slot. The converted binary bit data stream is directed to decoder 20 by signal line 22. For a more detailed description of the operation of traditional paging receivers with power conservation, see Walter L. Davis et al., May 1985.
"Universal Paging Device with Power Cons, issued on March 21 and assigned to the same assignee as the present application.
No. 4,518,961 entitled "ervation".

The peak and minimum detection circuits 32 and 34 of the data limiter embodiment of the present invention are shown in the block diagram of FIG. Referring to FIG. 3, the signal line 18 carrying the recovered analog signal is routed to the inverting input (-) of one comparator circuit 40 and to the non-inverting (+) input of another comparator circuit 42. A traditional reference oscillator circuit 44 is coupled via a signal line 45 to the input of an I ² L gate 46. I ² L gate
One output of 46 is coupled to the clock input of up / down counter 50 via signal line 48. Another output of the I ² L gate 46 is coupled via signal line 52 to the clock input of another up / down counter 54.

In this embodiment, up / down counters 50 and 54 are generated by controller circuit 56 and signal lines 58.
And 60 comprise a plurality of flip-flop register circuits arranged in a traditional manner in a counter stage controlled to count up or down in response to a control signal UP / DN directed to counters 50 and 54. More specifically, in the present embodiment, counters 50 and 54 include five traditional binary flip-flop stages configured to count up and count down, and the Q output Q of the flip-flop of counter 50. ₀ −Q ₄
Respectively correspond to binary signals 2 ⁰ -2 ^4, and conversely, the counter 54, flip-flop outputs Q ₀ bar -Q ₄
Bars, respectively, corresponding to the binary signal 2 ⁰ bar - ²⁴ bar. Therefore, when the counter 50 is instructed to count up the signal 58, the signal Q ₀ -Q ₄ will increase in binary steps rate corresponding to the clock signal of the signal line 48. Conversely, when it is commanded to counter 54 counts up the signal 60 decrements at a rate signal Q ₀ bar -Q ₄ bars corresponding to the clock signal of the signal line 52, i.e. countdown binary manner I do. Each of the counters 50 and 54 further includes traditional rollover and rollunder protection circuits to prevent such a condition from occurring.

The signal lines Q ₀ -Q ₄ of the counter 50 are led to the corresponding binary inputs of a digital-to-analog (D / A) converter 62 and the signal lines Q ₀ -Q _{4 of the} counter 54 are connected to the other D / A
It is coupled to the binary input of converter 64. The output of converter 62 is coupled by signal line 66 to the non-inverting (+) input of comparator circuit 40, and the output of D / A converter 64 is coupled by signal line 68 to the inverting (-) input of comparator circuit 42. ing. In addition, the outputs of D / A converters 62 and 64 are respectively connected to resistor divider networks R1 and R2 as peak and minimum amplitude analog signals Vp and Vv, respectively, as described in connection with the embodiment of FIG. Is joined to the end. Further, the output of the comparator 40 is connected to the I ² L gate 7 by a signal line 70.
It is tied to two inputs. Similarly, the output of converter 42 is coupled by signal line 74 to the input of another I ² L gate 76. The outputs of I ² L gates 72 and 76 are coupled to clock signal lines 48 and 52, respectively, for control thereof.

In this embodiment, two command signals, labeled RESET and ENABLE, are coupled to controller 56 by lines 78 and 80. Further, another clock signal output of the I ² L gate 46 is coupled to the controller 56 via a signal line 82. In response to the command signals "reset" and "enable" and managed by the clock signal on signal line 82, the controller 56 controls the peak and minimum detection circuits in a plurality of operating modes as described in more detail below. Generate multiple control signals. One control signal is coupled to signal line 70 by signal line 84. Other control signals are signal lines by signal line 86
Combined with 74. Other control signals are coupled to signal lines 48 and 52 by signal lines 88 and 90, respectively.

A suitable embodiment for oscillator circuit 44 and controller circuit 56 is shown in the logic diagram of FIG. Referring to FIG. 4, an exemplary oscillator circuit 44 is shown,
The circuit 44 comprises fifteen I ² L gates C1-C15 whose outputs are cascaded to the inputs, forming a complete ring and the I ² L gates.
One of the outputs of C15 has been used as a reference clock signal being coupled to an input of the I ² L gate 46 via a signal line 45. When energized, oscillator 44 generates a square wave reference clock signal, which is provided through inverting gate 46 and simultaneously through signal lines 48, 52, and 82. The clock signals on signal lines 48 and 52 are the clock signals that manage the coefficients of counters 50 and 54, respectively.
PCK and VCK. The reference clock signal guided through signal line 82 is the NC of two D-type flip-flops 100 and 102 of control circuit 56, shown as dashed lines.
Is tied to the input.

Command signal "Reset" and "Enable" is coupled to an input of each of the I ² L gate B7 and B5 through signal lines 78 and 80, respectively outputs of the I ² L gate B7 and B5 are I ² L gate B8 and It is tied to the input of B6. Another output of the I ² L gate B7 via the signal line 112 is coupled to other I ² L gate B13. Further, the outputs of I ² L gates B6 and B8 are connected to signal lines 114 and 1 respectively.
It is coupled to I ² L gates B14 and B15 via 16. I
The other output of the ² L gate B8 passes through signal line 118 and the I ² L gate
It is tied to the input of B16. In addition, each I ² L gate
B13 and the output of B15 is coupled to the input of the other I ² L gate B17 to the common output flip-flop 102 of the I ² L gate B17
D input. Furthermore, I ² L gate B13-B1
The output of the output of each of the 6 is coupled to the input of the other I ² L gate B18 in common I ² L gate B18 is coupled to the D input of flip-flop 100.

Flip-flop 10 shown as Q1 and Q2
The zero output is coupled to signal lines 116 and 112, respectively. Outputs Q1-Q3 of flip-flop 102 are coupled together and commonly to signal lines 58 and 60 and
It is coupled to an input of the I ² L gate B9. Shown as NQ2, the inverted output of the flip-flop 100 is the other I ² L gate B1
Connected to zero input. The inverted outputs of flip-flop 102, shown as NQ1, NQ2, and NQ3, are coupled to signal lines 118, 114, and 112, respectively. The output of the I ² L gate B9 is coupled to other I ² L gate B3, the I ² L gate
The output of B3 is coupled to signal lines 70 and 74 via signal lines 84 and 86, respectively.

The operation of the data limiter 16 will be described with reference to the preferred embodiment shown in FIGS. 3 and 4 and the operation mode state diagram shown in FIG. In order to better understand the state diagram of FIG. 5 in connection with the embodiment of FIGS. 3 and 4, it is necessary to explain the correlation of the signal labeling. For example, the signal CLKS is correlated to the output of the I ² L gate B10 derived via signal lines 88 and 90. In addition, the signal UPNDWN
S is an I ² L gate B3 led by signal lines 84 and 86
Correlates to the output of Furthermore, in the present embodiment, the fifth
The operating mode state indicated by block 130 in the figure is an unstable state. Thus, the state of the control circuit 56 is automatically transferred to that of the other blocks depending on the command signal reset and enable states. In a particular embodiment, there are three stable operating mode states, a first mode is referred to as a track mode and indicated by block 132, a second mode is referred to as a hold mode indicated by block 134, and The third mode of operation is referred to as the DOWN1 mode indicated by block 136. In brief, the track mode is a mode for acquiring or reacquiring a sample, and the hold mode is a mode for storing or saving a previously acquired sample.

If both the command signal reset and the enable are at logic one, the controller 56
Respond by maintaining 16 in the track operating mode, indicated by block 132, where the logic states of the control signals on lines 84, 86, 88 and 90 are all logic ones. In this track state, the oscillator circuit 44
The reference clock signal generated by the
And via an I ² L gate 46 to a clock input of a counter 50 by a signal line 48. If the up / down signal on signal line 58 is a logic one state (see block 132), counter 50 responds with a count up which increases the output analog signal of D / A converter 62 (line 66). The generated analog signal 66 of the converter 62 is compared with the recovered analog signal 18 of the comparator 40 and the output of the comparator 40 if the amplitude of the generated analog signal exceeds that of the recovered analog signal. signal PDONE is this is a logic 1 and a logic 0 output of the I ² L gate 72, which prohibits the driving virtually reference clock signal is further counter 50. The digital words Q0-Q4 generated by the counter 50 are maintained in that register until the recovered analog signal 18 again exceeds the amplitude of the analog signal 66 generated during the track mode. While maintained, in track mode, digital words Q0-Q4 stored in counter 50 cause fixed analog peak amplitude signal Vp to be output from converter 62.

At the same time, in the track mode, the counter 54 is driven by the reference clock signal by the signal line 52 via the signal line 45 and the I ² L gate 46 and controlled by the up / down (UP / DN) signal of the line 60. Count up. However, the inverted output of the flip-flop of the counter 54, Q0-Q4, is coupled to the converter 64 so that its output analog signal (signal line 6
8) Decrease the amplitude when the counter 54 is counted up. Once the magnitude of the generated analog signal 68 drops below the amplitude of the recovered analog signal 18, counter 42 generates a logic one signal VDONE, which is I ² L
Gate 76 produces a logic zero at its output, which effectively
The VCK clock signal inhibits further driving of the counter 54. The generated digital word Q0-Q4 of the counter 54 is the recovered analog signal in its register.
18 remains below the amplitude of the analog signal 68 generated during the track mode. While being maintained, the converter 64 outputs the analog minimum signal Vv in which the digital words Q0-Q4 stored in the counter 54 are fixed in the track mode.

When either command signal RESET or ENABLE changes the logic state to a logic zero, controller 56 responds by changing the mode of operation of data limiter 16 to the hold state shown in block 134. However, in order to stabilize and maintain the operation in the hold mode, both the command signals RESET and ENABLE
Must be logic 0. Under these conditions, the control signals on signal lines 84, 86, 88 and 90 are at logic zero,
This inhibits further tracking operations of the peak and minimum detection circuits. The peak and minimum digital words are held in the registers of counters 50 and 54, respectively, during the hold mode of block 134.

In order for the controller 56 to move the data limiter 16 to the third mode of operation of block 136, either the reset signal or the enable signal must be forced to a logic 1 in this embodiment, but the third mode , The reset and enable signals should be logic 1 and logic 0, respectively. In the mode of operation of block 136, the digital words of counters 50 and 54 are modified by a predetermined count providing their self-tuning. More specifically, in this embodiment, the counter 50
Is decremented by one count and the digital word of counter 54 is not actually decremented by one count, but is effectively incremented by one count by using the inverted output of the register. After changing the digital word count of counters 50 and 54 up and down, the operating mode is moved to track mode 132 by command signal reset and enable.

Counting greater than one is performed by operating mode 136 and alters the digital word of counters 50 and 54 simply by extending its duration. This can be more completely understood by referring to the time waveform diagram of the reference clock signal in FIG.

As mentioned above, controller 56 is governed by signal line 45 and a reference clock signal guided thereto by signal line 82 via I ² L gate 46 and controls the transfer of the operating mode to one of its signal waveforms. Synchronize to the edge. More specifically, in this embodiment, since the reference clock signal is directed to the NC inputs of bistable registers 100 and 102, its output can only change state on the falling edge of the reference clock signal. Referring to FIG. 6, if it is before the time t1, the controller 56 controls the data limiter 16 to the hold operation state,
And at time t1, the command signal reset and enable change state to transfer to the DOWN1 operating state. However, the transfer to DOWN1 will not occur until the next falling edge of the reference clock signal triggers the bistable registers 100 and 102 at time t2.

In the DOWN1 mode, signal lines 88 and 90 are in a state that allows the reference clock signal derived via signal lines 48 and 52 to drive counters 50 and 54, respectively. Thus, at the next rising edge of the reference clock signal at time t3, counters 50 and 54 are decremented by one count. Assuming that at some time after t3, but before the next falling edge of the reference clock signal, the command signal reset and enable have changed state to cause a transfer to track mode, such a transfer takes place at time t4. At the next falling edge of the reference clock signal. Thus, if a change in digital words of more than one count is desired, the duration of the DOWN1 mode of operation is increased by as many rising edges of the reference clock signal as necessary before causing a transfer of control to the track mode of operation. It can be extended by command signal reset and enable.

Accordingly, during the track mode, if the state of the command signal is changed to perform a transfer to the hold mode of block 134, for example, at time t5, the next falling of the clock reference signal at t6. Transfer occurs at the edge. In this manner, the control circuit 56 can control the transfer between each operation mode of the data limiter 16 in response to the command signal reset and enable and managed by the clock reference signal of the oscillator 44.

In a typical operation, the track and hold mode of operation of the data limiter 16 may be related in time to the awake and sleep periods of the battery saver cycle as shown by the exemplary time waveform B of FIG. Initial peak and minimum amplitude acquisition, requiring an extended awake period as indicated by the shaded portion of the awake period in time waveform C of FIG. 1, can be commanded by turning on the power of the paging receiver. . However, re-acquisition of a new peak and minimum amplitude for each awake period is not required unless the power to the paging receiver is turned off and turned on again.

Once obtained, the peak and minimum amplitude values are stored as digital words in counters 50 and 54 and are maintained therein during the sleep period of the battery saver cycle. More specifically, in this embodiment, battery power B + is used to maintain its power to maintain the digital state of the peak and minimum digital words during the sleep or de-energization period of the battery saver controller 28. B + can be connected directly to counters 50 and 54 and via line 26 to selected circuitry of controller 56.

As described in connection with the state diagram of FIG. 5, the self-tuning of the peak and minimum amplitude digital words
g) can be achieved by a transfer to the DOWN1 mode during a controlled transfer from the hold mode 134 to the track mode 132. If the peak and minimum amplitudes of the recovered analog signal do not change over the battery saver cycle, the count-up change caused by the DOWN1 operating mode will be quickly restored in the next track mode. However, if inadvertently wrong peaks and / or minimum amplitudes are obtained,
Or DOWN if the peak and / or minimum amplitude of the recovered analog signal changes over the battery saver cycle due to temperature changes, changes in the input signal, etc.
Changes made by one mode result in digital words being incorrectly or incorrectly generated and incrementally converging to the correct amplitude value with each battery saver cycle to fine tune it. This self-tuning operation also causes the peak and minimum amplitudes generated by counters 50 and 54 to follow the current peak and minimum amplitude of the recovered analog signal, correcting for small fluctuations over time and temperature.

Although the invention has been described above with reference to specific embodiments,
It is understood that additions and changes can be made without departing from the principles of the invention. Therefore, the present invention should not be limited to any single embodiment, but rather construed in breadth and scope in accordance with the description in the appended claims.

 ──────────────────────────────────────────────────続 き Continuing the front page (72) Inventor Davis Walter Lee, Northwest Third Street, Coral Springs, 33071, Florida, USA 10948 (56) Reference US Patent 4631737 (US, A)

Claims (9)

(57) [Claims] 1. A digitally encoded data word, comprising: receiving a paging signal including a modulated digitally encoded data word transmitted from an external source; and demodulating the received paging signal. An input section for restoring an analog signal representative of the paging signal and a data limiter section for converting the restored analog signal into a corresponding binary bit stream representing the coded data words of the paging signal. And a power supply coupled to the input section and the data limiter section and a battery powered power supply for periodically energizing and deactivating the input and data limiter sections from the battery powered power supply during awake and sleep periods, respectively. Battery saver section (28), including A data saver-type paging receiver, wherein the data limiter section operates in a first mode to obtain a peak amplitude from a recovered analog signal and generate a first digital word representative thereof. (72,50,62,40), wherein the first means includes first storage means (50) for storing the first digital word, wherein the first means comprises a second storage means (50). Operating in a first mode to cause the first storage means to hold the first digital word, and further operating in a third mode to store the first digital word in the first storage means in a predetermined manner. The first means for decrementing by a count, the second means operating in the first mode to obtain a minimum amplitude from the recovered analog signal and to generate a second digital word representative thereof (76, 54,64,42)
The second means includes second storage means (54) for storing a second digital word, wherein the second means comprises the second digital word.
Operating in the second mode, causing the second storage means to hold a second digital word, and further operating in the third mode, incrementing the second digital word in the second storage means by a predetermined count. Control means (56) for controlling a transition of an operation of the first and second means between the first, second and third modes in response to at least one command signal; Third means (36) for converting the reconstructed analog signal (Vp, Vv) into a corresponding binary bit stream based on the first and second digital words, and Means (4) for generating a reference clock signal (CLKS) managed by a reference clock signal in controlling transition between each mode of the first and second means
4) A battery saver type paging receiver comprising: 2. The invention of claim 1 wherein said first and second means each operate in a third mode to decrement said first word by a single count and increment the second word. The battery saver type paging receiver as described. 3. The control means further responsive to at least one command signal and managed by the reference clock signal during a transition from a second operating mode to a first operating mode. The battery saver type paging receiver according to claim 1, wherein said means is controlled to a third operation mode. 4. The first means for generating a first digital word during said first mode.
A down-counter (50), a digital-to-analog converter (62) controlled by the first digital word to generate a first analog signal, and comparing the first analog signal with the recovered analog signal. And the first
Instantaneous peak amplitude is the first
Means for generating a first output signal when reaching the time to control the up / down counter of said second means, said second means for generating a second digital word during said first mode. Second up / down counter (5
4) a digital signal for generating a second analog signal managed by and representative of said second digital word;
An analog converter (64), and comparing the second analog signal with the reconstructed analog signal and until an instantaneous minimum amplitude controls a second up / down counter in generating the second digital word; And means for generating a second output when the first and second counters are reached, and said control means (56) controls said first and second up / down counters in response to said at least one command signal. Enabling and generating its respective first and second digital words during a first mode;
Inhibiting the generation of the up / down counter of the first and second up / down counters and holding the respective first and second digital words during the second mode in the first and second up / down counters; and 2. The battery saver type paging receiver of claim 1, wherein the first and second digital words of the first and second up / down counters are respectively incremented or decremented by a predetermined count. 5. The data limiter includes means (44) for generating a reference clock signal, and the control means controls the transition between the first, second, and third modes of operation. The battery saver type paging receiver according to claim 4, wherein the paging receiver is managed by a reference clock signal. 6. The first and second up / down counters have their respective first and second counters during a first mode of operation.
And generating the second digital word is driven by the reference clock signal, the clock signal being inhibited from driving the first and second up / down counters during its second mode of operation. And the control means causes the predetermined number of clock pulses of the reference clock signal to decrement the first digital word and increment the second digital word, respectively, during a third mode of operation. The battery saver type paging receiver according to claim 5, wherein the paging receiver drives the first and second up / down counters. 7. The battery saver type paging according to claim 6, wherein said control means controls a transition to a third operation mode during a transfer from the second mode to the first operation mode. Receiving machine. 8. The battery saver-type paging receiver of claim 1, wherein said first and second modes are correlated with awake and sleeve periods of a battery saver section. 9. The data limiter section first and second storage means extend during a sleep period of the battery saver section to hold first and second digital words stored therein, respectively. 9. The battery saver paging receiver of claim 8, wherein the paging receiver remains energized.