JP2836101B2 - Prober attachment board - Google Patents

Description

The present invention relates to a mechanism for performing a continuity check when inspecting a wafer with an LSI tester.

[Conventional technology]

Conventionally, in order to confirm that signal lines are conducted from the LSI tester to the probe card through the prober attachment board, probing a wafer whose surface is covered with a conductor, and conducting each signal terminal and ground terminal. It was confirmed that the signal terminal of the LSI tester was electrically connected to the probe of the probe card.

In FIG. 3, 10 is an LSI tester, 11 is a load board, 12 is a prober, 1c is an attachment board of the prober, 13 is a probe card, and 14 is a wafer.

[Problems to be solved by the invention]

In the conventional continuity check described above, if the continuity is not achieved, as shown in FIG. 3, (1) poor contact between the LSI tester 10 and the load board 11, and (2) between the load board 11 and the prober attachment board 1c. Poor contact, (3) Poor contact between prober attachment board 1c and probe card 13, (4) Probe of probe card 13 and wafer 14
It is possible to judge which of the following causes is defective: (5) defective LSI tester 10, (6) defective load board 11, (7) defective prober attachment board 1c, or (8) defective probe card 13. Did not.

For this reason, when a conduction failure occurs, the above-described eight locations must be checked one by one, and there is a disadvantage that it takes time to eliminate the conduction failure.

An object of the present invention is to provide a prober attachment board that solves the above-mentioned problems.

[Differences of the Invention from the Prior Art]

In contrast to the above-described conventional device, the prober of the present invention has a continuity failure by short-circuiting the signal line from the LSI tester on the prober attachment board and the ground line, or by detecting the voltage level of the aforementioned signal line. If it occurs, it has the difference that it can be checked whether it is a defect from the LSI tester to the prober attachment board or a defect from the prober attachment board to the wafer.

[Means for solving the problem]

In order to achieve the above object, in an attachment board of a prober according to the present invention, a short circuit between a signal terminal and a ground terminal of an LSI tester, or a detection of a voltage level of the signal terminal, causes a connection between an LSI tester and a wafer. It has means for enabling continuity check.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

In the figure, 1a is a prober attachment board,
2 is a relay circuit, 3a to 3i are conductor pads to be connected to the load board (note that pad 3b is electrically connected to the ground line of the LSI tester), 4a to 4h are pads to be connected to the probe card, and 5a is a conductor. is there.

Normally, the relay of the relay circuit 2 is open, and the conductive pads 3a, 3b, 3e, 3g, 3i are not conducting.

If a failure occurs in the continuity check between the LSI tester and the wafer, applying a voltage to the pad 3c closes the relay of the relay circuit 2. Therefore, if the ground terminal (pad 3b) and the signal terminal (pads 3a, 3b, 3e, 3g, 3i) conduct, and the continuity check, that is, the current flows through the signal line, and the voltage between the signal line and the ground line is measured, You can check whether there is continuity between the LSI tester and the attachment board. Therefore, it becomes clear whether the failure is between the LSI tester and the prober attachment board or the failure between the prober attachment board and the wafer. As a result, defective portions can be quickly narrowed down, and preparation time for inspecting a wafer with an LSI tester can be greatly reduced.

Embodiment 2 FIG. 2 is a configuration diagram showing Embodiment 2 of the present invention.

In the figure, 1b is a prober attachment board,
3j-3r are the conductor pads connected to the load board, 4i-4p are the conductor pads connected to the probe card, 5b is the conductor, 6 is the semiconductor integrated circuit, 7a-7d is the input buffer circuit, 8 is the output buffer circuit, 9 is It is a 4-input AND circuit.

In FIG. 2, all the potentials of the pads 3j, 3l, 3o, 3q are set to H.
If the level is set to the igh level, the potential level of the pad 3k is also set to the high level. Therefore, for example, when conduction failure occurs between the pad 3j on the prober attachment board and the signal terminal of the LSI tester, the potential level of the pad 3j does not become the high level even if the signal of the LSI tester is set to the high level.
The 3k potential level becomes Low level. Therefore, a conduction failure between the LSI tester and the attachment board can be detected.

〔The invention's effect〕

As described above, the prober of the present invention short-circuits the signal line and the ground line on the attachment board, or has a means for detecting the potential of the signal line, thereby checking the continuity between the LSI tester and the wafer. When a defect occurs, a defect between the LSI tester and the attachment board of the prober and a defect between the attachment board and the wafer can be easily measured. As a result, the defective portion can be quickly determined, and the preparation time for inspecting the wafer with the LSI tester can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a block diagram showing a second embodiment of the present invention, and FIG. 3 is a diagram showing a signal path from an LSI tester to a wafer. 1a, 1a, 1c… Prober attachment board 2… Relay circuit 3a∼3r… Conductor pads connected to load board 4a∼4p …… Conductor pads connected to probe card 5a, 5b… Conductors, 6… Semiconductor integrated circuits 7a to 7d: input buffer circuit 8: output buffer circuit, 9: 4-input AND circuit 10: LSI tester, 11: load board 12: prober, 13: probe card 14: wafer

Claims (1)

(57) [Claims] 1. A circuit for short-circuiting between a signal terminal and a ground terminal of an LSI tester or detecting a voltage level of the signal terminal to enable a continuity check between the LSI tester and a wafer. Attachment board for prober.