JP2834009B2 - Multi-mode phase modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-mode phase modulator suitable for a digital radio communication apparatus capable of transmitting a plurality of phase-modulated waves having different numbers of modulation phases, and more particularly to a multi-mode phase modulator which promotes digital circuit. .

[0002]

2. Description of the Related Art Conventionally, a multi-mode phase modulator as shown in the block diagram of FIG.
No. 3743 (title of the invention: multimode modulator). This type of multi-mode modulator always provides good communication quality by changing the number of modulation phases of a phase-modulated wave, that is, by changing the transmission capacity, even when the transmission conditions of a transmission line change in a wireless communication system or the like. It is possible to obtain. This multi-mode modulator has up to 8 phase PS
Explaining only K (phase shift keying) modulation, the modulation mode control signal S101 input to the data processing unit 101 controls the modulation phase number of the PSK modulation wave T101 transmitted from the mixer unit 106 to two phases. The mode is set to either the 4-phase or 8-phase mode.

When the modulation mode control signal S101 sets the 2PSK mode, the data processing unit 101 outputs the first data d101 to the roll-off filter unit 102A as valid data D101. At this time, the valid data D10
3 is fixed to “0” and the roll-off filter unit 102B
Is turned off by the modulation mode control signal S101. When the modulation mode control signal S101 sets the 4PSK mode, the data processing unit 101 sets the first data d
101 is output to the roll-off filter unit 102A as valid data D101, and the second data d102 is output to the roll-off filter unit 102B as valid data D102. At this time, the valid data D103 and the valid data D
104 is fixed to “0”. Further, when the modulation mode control signal S101 sets the 8PSK mode, the data processing unit 101 converts the first data d101 into the valid data D
101, the third data d103 is output to the roll-off filter unit 102A as valid data D103, the second data d102 is output to the roll-off filter unit 102B as valid data D102, and the inverted data of the second data d102 is output to the roll-off filter unit 102B as valid data D104. I do.

[0004] Roll-off filter units 102A and 102
2B operates as a binary roll-off filter that does not take an intermediate value of an analog signal in the 2PSK mode or the 4PSK mode, and operates as a 4-value roll-off filter that takes an intermediate value of the analog signal in the 8PSK mode. It is working. The phase and amplitude modulation unit 104A converts the analog signal from the roll-off filter 102A into a signal wave,
The carrier wave from carrier wave oscillator 103 is converted to PSK by this signal wave.
The PSK is modulated and supplied to the mixer 106. Further, the phase and amplitude modulation section 104B uses the analog signal from the roll-off filter 102B as a signal wave, and the 0-90 degree hybrid 105 uses the signal wave to make the phase 90
Carrier from carrier oscillator 103 shifted by PSK
The PSK is modulated and supplied to the mixer 106.

[0005] The mixer section 106 includes a phase and amplitude modulating section 104.
A and 104B are respectively combined with the PSK modulated waves, and the 2PSK modulated waves, the 4PSK modulated waves, and the 8P
One of the SK modulated waves is output as a PSK modulated wave T101.

[0006]

In the conventional multimode modulator described above, the carrier oscillator 103, the phase and amplitude modulators 104A and 104B, the 0-90 degree hybrid 105, and the mixer 106 are analog circuits.

For this reason, the multimode modulator has a problem that the circuit scale is large and the multimode modulator is easily affected by the surrounding electromagnetic environment.

Further, since the multi-mode modulator uses an analog circuit as a main part for performing a phase modulation process, it is difficult to avoid deterioration from ideal modulation characteristics due to existence of frequency characteristics, impedance mismatch and nonlinear distortion. There was a problem.

Further, this multi-mode modulator has a problem that it requires circuit adjustments associated with the analog circuit, such as adjustments for equalizing the amplitudes of two PSK modulation waves supplied to the mixer section 106. Was.

[0010]

According to the present invention, there is provided a multimode phase modulator comprising: a clock oscillator for generating a clock signal whose clock frequency is 2 ^N (N is an integer of 1 or more) times the carrier frequency of a PSK modulated wave; And the clock signal is 2 ^N
A frequency divider that generates a frequency-divided signal by dividing the frequency; and 2 ^N kinds of phase shift components having a period equal to the frequency-divided signal and different in phase from each other by 2π / 2 ^N in response to the frequency-divided signal and the clock signal. A shift register that generates a peripheral signal and 2 ^M types (M
, Which is controlled by a selection signal of 1 to N) and selects the phase shift frequency-divided signal corresponding to each of the selection signals to generate the ^2M- phase PSK modulated wave.

The multi-mode phase modulator responds to 2 ^M kinds of data signals and a control signal for setting the M,
Ru preparative structure further comprising a data processing unit for causing said selection signals corresponding to each respective of the data signal.

In the multimode phase modulator, N is 3 and M can be any one of 1 to 3,
Wherein the data signal is a signal of M bits having a to the M data is 2 ^(M-1) 2 ⁰ digit bits from the first data is a significant bit, the selection signal is a signal of 3 bits,
Wherein the data processing unit, wherein the first data as a 2 ^2-digit bits of the selection signal and the control signal and the control signal receives the second data of the first data and the data signal and the first data and A ROM for generating a predetermined logic signal according to the second data at a first output terminal and a second output terminal, respectively, the control signal and the second signal;
Receiving data and the logic signal from the first output end, if M is 1, select the logic signal and
A first control unit selector produce 2 ¹ digit bit of the selection signal selects the second data if it is but 2 and 3, the control signal and the third data and said second data signal Receiving the logic signal from the output end of the M, and when M is 1 and 2, selects the logic signal and
If but a 3 Ru preparative configuration and a second controller selector to produce 2 ⁰ digit bits of the selection signal selects the third data.

[0013]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

[0015] The clock oscillator 1 of the multi-mode phase modulator generates a PSK modulated wave T2 transmitted by the phase modulator.
Generates a clock signal C1 having a clock frequency that is 2 ^N (N is an integer of 1 or more) times the carrier frequency. This clock signal C1 is frequency-divided by 2 ^N by the frequency divider 2 to become a frequency-divided signal C2. The frequency-divided signal C2 and the clock signal C1 are supplied to the shift register 3, and the shift register 3 generates ^2N kinds of phase-shifted frequency-divided signals C3 whose periods are equal to the frequency-divided signal C2 and whose phases are different from each other by 2π / ^2N. .

The data processing unit 6 has 2 ^M types (M is 1
(An integer of N) PSK modulated wave T2, which is the source of the signal wave, and its M value, that is, a control signal S1 for setting the number of modulation phases 2 ^M (modulation mode) is supplied, and data processing is performed. The unit 6 includes 2 corresponding to each of the data signals d.
^M types of selection signals D are generated. Phase shift frequency-divided signal C3
And the selection signal D are supplied to the selector 4. Selector 4
Selects the phase shift frequency-divided signal C3 corresponding to each of the selection signals D to generate a ^2M- phase PSK modulated wave T1. The PSK modulated wave T1 is roll-off shaped into a waveform having a roll-off spectrum by a band-pass filter type roll-off filter 5 using a SAW filter or the like, and becomes a PSK modulated wave T2. This PSK modulated wave T2
Is supplied to a transmission device that is connected to a subsequent stage and performs frequency conversion, amplification, and the like.

Next, referring to FIG. 1, the operation of the multi-mode phase modulator in which N is set to 3 and M is selectable from 1 to 3 will be described in detail.

The clock oscillator 1 is composed of a ring counter or the like and generates a TTL level or C-MOS level clock signal C1. The frequency divider 2 can be composed of three flip-flops (for example, HD74LS93 type 4
-Bit binary counter, manufactured by Hitachi, Ltd.) to generate a frequency-divided signal C2 obtained by dividing the clock signal C1 by eight. The shift register 3 shifts the frequency-divided signal C2 one bit at a time of the clock signal C1 and shifts the phase of the clock signal C1 by eight kinds of phase-shifted frequency-divided signals C3 (C31, C32,.
37 and C38). The phases of the eight types of phase-shifted frequency-divided signals C31, C32,..., C37 and C38 are as follows.
The signal C38 is delayed from the signal C31 by 315 degrees (14π /
8) Delayed signal. Note that the shift register 3 can be constituted by an 8-bit shift register (for example, HD74L
S164 8-bit parallel-out serial shift register, manufactured by Hitachi, Ltd.).

Meanwhile, the data signal d supplied to the data processing unit 6, 2 ^(M-1) first is significant bits = 2 ² digit bits
A signal M = 3 (bits) having a a second data d2 and 2 ⁰ digit bit is data d1,2 ¹ digit bit to the M data = 3 data d3. Data processing unit 6
Performs signal processing on the data signal d according to the control signal S1,
A 3-bit selection signal D, that is, selection signals D1, D2 and D3 is generated. The M value is set by an automatic instruction from a propagation state detection circuit (not shown) or a manual operation.

Hereinafter, the detailed operation of the data processing unit 6 is shown in Table 1.
This will be described with reference to the operation table of FIG.

[0021]

[Table 1]

First, the control signal S1 sets M = 1, that is, the modulation mode of this multi-mode phase modulator is set to 2PSK.
When the mode is set (the PSK modulation wave T1 is a 2PSK modulation wave, and so on), the data processing unit 6 performs the first processing.
The data d1 as a selection signal D1 remains intact 2 ^2-digit bit selection signal D. Also, when the selection signal D2 indicating a 2 ¹ digit bit selection signal D first data d1 is "0", "0", and "1" when the "1" indicates 2 ⁰ digit bit selection signal D The selection signal D3 is fixedly set to “0”.

Next, when the control signal S1 sets M = 2,
In the case of the PSK mode, the data processing unit 6
The data d1 and the second data d2 are directly used as selection signals D1 and D2, respectively. Further, the selection signal D3 is
As shown in Table 1, the value is obtained by performing an exclusive OR operation on the first data d1 and the second data d2.

Further, when the control signal S1 sets M = 3 to perform the 8PSK mode, the data processing section 6 converts the first data d1, the second data d2 and the third data into selection signals D1 and D2, respectively. And D3.

The selector 4 is controlled by a selection signal D (= D1, D2 and D3) from the data processing unit 6, and outputs eight kinds of phase shift frequency-divided signals C output from the shift register 3.
3 (C31, C32,..., C37, C38) to generate a modulated wave T1. The operation of the selector 4 will be described in detail with reference to the operation table in Table 2.

[0026]

[Table 2]

When the control signal S1 sets the 2PSK mode, the selection signal D output from the data processing unit 6 becomes "0, 0,
0 "and" 1,1,0 ". The selector 4 selects the phase shift frequency-divided signal C31 having a phase of 0 degree according to the selection signal D = "0, 0, 0".
A phase shift frequency-divided signal C35 having a phase of 180 degrees is selected according to "1, 1, 0". Therefore, the selector 4 has 2PS
In the case of the K mode, a PSK modulated wave T1 subjected to two-phase PSK modulation having phases different from each other by 180 degrees (π) is output.

When the control signal S1 sets the 4PSK mode, the selection signal D output from the data processing unit 6 is "0,0,0", "0,1,1" and "1,1,0". There are four types, "1, 0, 1". Select signal D = “0,
“0,0” is a phase shift frequency-divided signal C31 having a phase of 0 degrees, a selection signal D = “0,1,1” is a phase shift frequency-divided signal C33 having a phase of 90 degrees, and a selection signal D = “1,1,2”. "0" is phase 1
The 80-degree phase shift frequency-divided signal C35 is changed to the selection signal D =
"1, 0, 1" is a phase shift frequency-divided signal C having a phase of 270 degrees.
37, the selector 4 outputs a 4-phase PSK modulated PSK modulated wave T1 having a phase difference of 90 degrees (π / 2) from each other in the 4PSK mode.

Further, when the control signal S1 sets the 8PSK mode, the data processing section 6 outputs eight kinds of selection signals D using all bits of the selection signals D1, D2 and D3. The selector assigns these eight kinds of selection signals D to all of the eight kinds of phase shift frequency-divided signals C3. Therefore, in the 8PSK mode, the selector 4 selects eight kinds of phase shift frequency-divided signals C3 having phases different from each other by 45 degrees (π / 4) according to the selection signal D, and
It outputs a PSK modulated wave T1 that has been subjected to phase PSK modulation.

Here, the phase shift frequency-divided signal C3 is represented by PS
The selection signal D is selected so that the K modulated wave T1 is gray-coded.
Note that this is selected by That is,
The data processing unit 6 controls the selection signal D for controlling the gray-coded PSK modulated wave T1 to be generated from the selector 4.
Next, the data signal d is signal-processed.

FIG. 2 is an example of a waveform diagram of main waveforms in this embodiment. This figure shows a multimode phase modulator with N =
3 and M = 1, that is, a waveform diagram when the 2PSK mode is set.

The phase shift frequency-divided signal C31 is a frequency-divided signal C2 obtained by dividing the frequency of the clock signal C1 from the clock oscillator 1 by 8 by the frequency divider 2, and the shift register 3 generates the clock signal C1.
Is a signal having a reference phase of 0 degree. Further, the phase shift frequency-divided signal C
35 is output from the shift register 3 and the divided signal C3
1 is a signal having a phase difference of 180 degrees (π). Clock signal C1, frequency-divided signal C2, and phase-shift frequency-divided signal C
31 and C35 generally use a TTL level or C-MOS level rectangular wave signal.

The data signal d supplied to the data processing section 6, that is, the first data d1 or the like generally has a cycle of several clocks of the phase shift frequency-divided signal C3. The selector 4 switches the selection of the phase shift frequency-divided signal C3 at the logical conversion point of the selection signal D, that is, almost at the logical conversion point of the data signal d. In this figure, the selector 4 switches to the PSK modulation wave T1 at the logical conversion point of the data signal d. This indicates that a phase switch of 180 degrees occurs. The modulated wave T1 is shaped into a waveform by the roll-off filter 5, and the modulated wave T1 is converted into a two-phase PSK-modulated PSK modulated wave T2 exhibiting a roll-off amplitude characteristic and a smooth phase change.

FIG. 3 is a detailed block diagram of the data processing section 6 used in this embodiment.

The data processing section 6 implements the operation shown in Table 1. That is, N is 3 and shift register 3
Outputs eight phase-shifted frequency-divided signals C3 whose phases are different from each other by 45 degrees (π / 4). In addition, M can select any one of 1 to 3, that is, this multi-mode phase modulator has 2PSK mode, 4PSK mode and 8PSK mode.
The mode can be set.

First, the data processing section 6 outputs the first data d1 as it is as the selection signal D1.

ROM 61 stores logical values "1" and "0", receives control signal S1, first data d1 and second data d2, and receives control signal S1, first data d1 and second data d1. A predetermined logical value "1" according to d2
Alternatively, "0" is generated at the first output terminal connected to the selector 62 and the second output terminal connected to the selector 62, respectively. That is, when the control signal S1 sets the 2PSK mode, the ROM 61 is controlled only by the first data d1, and when the first data d1 is “0”, the first and second ROMs are controlled.
And outputs "0" to the first output terminal and the second output terminal when the first data d1 is "1". When the control signal S1 sets the 4PSK mode, the ROM 61 outputs the first data d to the second output terminal.
1 and an output controlled by the second data d2.
That is, the ROM 61 stores the first data d1 and the second data d2.
At the second output terminal. The output logic value to the first output terminal may be arbitrary. Further, when the control signal S1 sets the 8PSK mode, the ROM 61 may take arbitrary logical values at both the first and second output terminals.

The selector 62 selects either the second data d2 or a logical signal from the first output terminal of the ROM 61 according to the control signal S1, and sets the selected signal as the selected data D2. For example, the selector 62 outputs the control signal S1
Sets M to 1 and sets 2PSK mode.
, And set M to 2 or 3 to 4PS
When the K mode or the 8PSK mode is set, the second data d2 is selected and set as the selected data D2.

The selector 63 selects one of the third data d3 and a logic signal from the second output terminal of the ROM 61 according to the control signal S1, and sets the selected signal as selection data D3. For example, the selector 63 outputs the control signal S1
Is 2PSK mode or 4PSK by setting M to 1 or 2.
When the mode is set, the logic signal from the ROM 61 is selected, and when M is set to 3 and the 8PSK mode is set, the third data d3 is selected to be selected data D3.

The multi-mode phase modulator of this embodiment described above is a digital circuit except for the roll-off filter 5 which does not need to be substantially adjusted as a phase modulator circuit. It is possible to avoid an increase in scale, a surrounding electromagnetic environment, frequency characteristics, impedance mismatch, and deterioration due to nonlinear distortion. Further, this multi-mode phase modulator can eliminate the need for adjustment of all circuits such as a phase modulation circuit.

[0041]

As described above, the multi-mode phase modulator of the present invention divides a clock signal whose clock frequency is 2 ^N (N is an integer of 1 or more) times the carrier frequency of the PSK modulated wave by 2 ^N. to produce the divided signal, the period is generated by the divided signal equally addition phase with each other 2 [pi / 2 ^N different 2 ^N types of phase shift divided signal a shift register,
It is controlled by 2 ^M kinds of selection signals (M is an integer of 1 to N) and selects the phase shift frequency-divided signal corresponding to each of the selection signals to generate the 2 ^M- phase PSK modulated wave. All circuits are substantially digital circuits, so that not only can the circuit scale be reduced, but also deterioration due to the surrounding electromagnetic environment, frequency characteristics, impedance mismatch and nonlinear distortion can be avoided.

Further, the multi-mode phase modulator of the present invention has an effect that adjustment of the phase modulation circuit is not required.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multi-mode phase modulator according to one embodiment of the present invention.

FIG. 2 is an example of a waveform diagram of main waveforms in the present embodiment.

FIG. 3 is a detailed block diagram of a data processing unit 6 used in the embodiment.

FIG. 4 is a block diagram of a conventional multimode phase modulator.

[Explanation of symbols]

 Reference Signs List 1 clock oscillator 2 frequency divider 3 shift register 4 selector 5 roll-off filter 6 data processing unit 61 ROM 62, 63 selector

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-58-159046 (JP, A) JP-A-3-283743 (JP, A) JP-A-57-159148 (JP, A) JP-A-50-159 28913 (JP, A) JP-A-57-155856 (JP, A) JP-A-4-133545 (JP, A) JP-A-5-63746 (JP, A) JP-A-59-201596 (JP, A) JP-A-59-161157 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 27/20

Claims (2)

(57) [Claims] 1. A carrier having a clock frequency of a PSK modulated wave.
Frequency 2^N(N is an integer of 1 or more) times the clock signal
A clock oscillator for generating a clock signal;
^NA frequency divider that generates a frequency-divided signal by dividing the frequency;
In response to the clock signal, the period is equal to the frequency-divided signal.
And the phases are 2π / 2^N2 different^NTypes of phase
A shift register for generating a shift-divided signal;^Mtype
(M is an integer from 1 to N).
The phase shift frequency division signals respectively corresponding to each of the selection signals.
Select the issue 2^MSelect that produces the PSK modulated wave of phase
And, 2 ^M Types of data signals and control signals for setting M
And the selection corresponding to each of the data signals.
A data processing unit for generating a selection signal, Said N is 3; M can be any one of 1 to 3, The data signal is 2 ^(M-1) Is the first data being a digit bit?
2 ⁰ M bits having up to Mth data which is a digit bit
Is the signal of The selection signal is a 3-bit signal; The data processing unit selects the first data as it is
Select signal 2 ^Two Digit bits, and the control signal and
Before receiving the first data and the second data of the data signal
Control signal and said first data and said second data
A first output terminal and a second output terminal
At each end, the control signal and the second
Receiving data and the logic signal from the first output end
If the M is 1, the logic signal is selected and the M
Is 2 and 3, select the second data
2 of the selection signal ¹ A first control cell selector for producing digit bits
And the control signal and third data of the data signal.
Receiving the logic signal from the second output end and the M
In the case of 1 and 2, the logic signal is selected and the M signal is selected.
If is 3, select the third data and select
Signal 2 ⁰ A second control unit selector for generating digit bits
Characterized by having Multimode phase modulator. 2. The method according to claim 1, wherein the selection signal is before gray coding.
The phase-shifted frequency-divided signal to produce a PSK-modulated wave.
2. The signal according to claim 1 , wherein the signal selects
Multimode phase modulator.