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JP2829102B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2829102B2
JP2829102B2 JP19312490A JP19312490A JP2829102B2 JP 2829102 B2 JP2829102 B2 JP 2829102B2 JP 19312490 A JP19312490 A JP 19312490A JP 19312490 A JP19312490 A JP 19312490A JP 2829102 B2 JP2829102 B2 JP 2829102B2
Authority
JP
Japan
Prior art keywords
film
polysilicon film
gas
forming
sih
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP19312490A
Other languages
Japanese (ja)
Other versions
JPH0479314A (en
Inventor
良夫 笠井
裕一 見方
孝彦 守屋
勝弥 奥村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19312490A priority Critical patent/JP2829102B2/en
Publication of JPH0479314A publication Critical patent/JPH0479314A/en
Application granted granted Critical
Publication of JP2829102B2 publication Critical patent/JP2829102B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device.

(従来の技術) 半導体装置の製造の際、半導体基板上に半導体膜、例
えば、ポリシリコン膜をCVD法により形成し、このポリ
シリコン膜にリン等の不純物を添加し、電極,配線とし
て利用することが多い。不純物を含んだポリシリコン膜
を形成する方法として、現在、半導体基板上に不純物を
含まないシリコン膜を形成後、このシリコン膜表面に不
純物を吸着・拡散させる工程からなり、必要があればこ
の工程を繰り返すイン・シトウュー・ドープド・ポリシ
リコン堆積法が検討されている。この形成方法を以下説
明する。
(Prior Art) In manufacturing a semiconductor device, a semiconductor film, for example, a polysilicon film is formed on a semiconductor substrate by a CVD method, and an impurity such as phosphorus is added to the polysilicon film to be used as an electrode and a wiring. Often. Currently, a method of forming a polysilicon film containing impurities includes a step of forming a silicon film containing no impurities on a semiconductor substrate and then adsorbing and diffusing impurities on the surface of the silicon film. An in-situ doped polysilicon deposition method that repeats the above is being studied. This forming method will be described below.

減圧CVD装置中に半導体基板を配置し、まずSiH4ガス
を熱分解し、アンドープド・ポリシリコン膜(不純物を
含まないポリシリコン膜)を形成する。次に、連続して
半導体基板を外気にさらすことなく、pH3ガス等の不純
物ガスを熱分解してアンドープド・ポリシリコン膜上に
不純物を被覆させる。そして、連続してアンドープド・
ポリシリコン膜上にSiH4ガスを熱分解し、アンドープド
・ポリシコン膜を形成させ、アンドープド・ポリシリコ
ン膜の間に、不純物層がはさまった構造を形成すること
ができる。以上の工程を必要があれば繰り返し、アニー
ルして配線・電極としてのドープド・ポリシリコン膜
(不純物を含んだポリシリコン膜)を形成する。
A semiconductor substrate is placed in a low-pressure CVD apparatus, and first, an SiH 4 gas is thermally decomposed to form an undoped polysilicon film (a polysilicon film containing no impurities). Next, without continuously exposing the semiconductor substrate to the outside air, an impurity gas such as a pH 3 gas is thermally decomposed to coat the impurity on the undoped polysilicon film. And continuously undoped
The SiH 4 gas is thermally decomposed on the polysilicon film to form an undoped polysilicon film, and a structure in which an impurity layer is sandwiched between the undoped polysilicon films can be formed. The above steps are repeated if necessary, and annealing is performed to form a doped polysilicon film (polysilicon film containing impurities) as wiring and electrodes.

この製造方法を用いた場合、たとえば添加される不純
物としてP等を用い、アンドープド・ポリシリコン膜上
への不純物被覆工程に引き続いて行われるアンドープド
・ポリシリコン膜を形成する工程において、SiH4ガス供
給開始より10分間程度シリコン膜が不純物の被覆したシ
リコン膜上にほとんど形成されないインダクションタイ
ムが発生するという欠点があった。これは不純物被覆層
(P層等)中の不純物吸着種(PH3分子またはP原子
等)に対し、SiH4分子の吸着確率が小さくなり、半導体
基板表面でのSiH4分子の解離反応における中間生成物で
あるSiH2分子の発生が抑制されるためであると考えられ
ている。このようなインダクションタイムの存在によ
り、ドープド・ポリシリコン膜の実効的堆積速度は、工
程繰り返し回数の増加に伴い著しく減少してしまう。
When this manufacturing method is used, for example, P is used as an impurity to be added, and in the step of forming an undoped polysilicon film subsequent to the step of coating an impurity on the undoped polysilicon film, the supply of SiH 4 gas is performed. There is a disadvantage that an induction time occurs in which a silicon film is hardly formed on a silicon film covered with impurities for about 10 minutes from the start. This impurity coating layer (P layer) impurities adsorbed species in respect (PH 3 molecule or P atom), the adsorption probability of SiH 4 molecules is reduced, an intermediate in the dissociation reaction of the SiH 4 molecules in the semiconductor substrate surface It is believed that this is because the generation of the product SiH 2 molecules is suppressed. Due to the existence of such an induction time, the effective deposition rate of the doped polysilicon film is significantly reduced as the number of process repetitions increases.

(発明が解決しようとする課題) 従来の製造方法では、不純物を添加していない膜上へ
の不純物被覆工程に引き続いてその上から不純物を添加
していない半導体膜を形成する際、インダクションタイ
ムが発生することによって実効的堆積速度が著しく減少
するという問題があった。本発明は、以上の点に鑑み、
インダクションタイムを短縮させ半導体膜の実効的堆積
速度を向上する半導体装置の製造方法を提供する。
(Problems to be Solved by the Invention) According to the conventional manufacturing method, when an impurity-doped semiconductor film is formed on a film not doped with an impurity following the step of coating the impurity-doped film on the film, the induction time is reduced. There is a problem that the effective deposition rate is significantly reduced by the occurrence. The present invention has been made in view of the above points,
Provided is a method for manufacturing a semiconductor device, which shortens an induction time and improves an effective deposition rate of a semiconductor film.

[発明の構成] (課題を解決するための手段) 本発明に係わる半導体装置の製造方法は、半導体基板
上に不純物を含まない第1の半導体膜を形成する工程
と、前記第1の半導体膜表面に不純物を吸着・拡散させ
不純物層を形成する工程と、Si2H6およびSi3H8の内少な
くとも1つを含む反応ガスの熱分解により前記不純物層
上に第2の半導体膜を形成する工程を備えたことを特徴
とする。
[Structure of the Invention] (Means for Solving the Problems) In a method for manufacturing a semiconductor device according to the present invention, a step of forming a first semiconductor film containing no impurities on a semiconductor substrate, and a step of forming the first semiconductor film Forming an impurity layer by adsorbing and diffusing impurities on the surface, and forming a second semiconductor film on the impurity layer by thermal decomposition of a reaction gas containing at least one of Si 2 H 6 and Si 3 H 8 And a step of performing

(作 用) 本発明では、不純物を含まない第1の半導体膜を形成
し、前記第1の半導体膜表面に不純物を吸着,拡散させ
た後、Si2H6およびSi3H8の内少なくとも1つを含む反応
ガスの熱分解によりSiH4分子を発生させることによっ
て、その上から形成する第2の半導体膜のインダクショ
ンタイムを減少させる。
(Operation) In the present invention, after forming a first semiconductor film containing no impurities and adsorbing and diffusing impurities on the surface of the first semiconductor film, at least one of Si 2 H 6 and Si 3 H 8 is used. By generating SiH 4 molecules by thermal decomposition of a reaction gas containing one, the induction time of the second semiconductor film formed thereon is reduced.

(実施例) 以下、本発明の実施例を説明する。(Example) Hereinafter, an example of the present invention will be described.

減圧CVD装置中に半導体基板を配置する。半導体基板
は水平に置かれガス流は下から導入され上から排気され
る。反応温度580℃,反応圧力0.5Torr,SiH4ガス200sccm
でSiH4ガスを熱分解し、第1のアンドープド・ポリシリ
コン膜を半導体基板上に形成する。次に、この工程に連
続して半導体基板を外気にさらすことなく、反応温度58
0℃,反応圧力0.5Torr,pH3ガス流量50sccmでPH3ガスを
熱分解して、アンドープド・ポリシリコン膜上にPを被
覆させる。引き続き連続して外気にさらすことなく、反
応温度580℃,反応圧力0.5Torr,Si2H6ガス流量200sccm
を装置内に供給し、Pを被覆した第1のアンドープド・
ポリシリコン膜上に、第2のアンドープド・ポリシリコ
ン膜を形成する。このようにして、アンドープド・ポリ
シリコン膜の間に、P層が存在する構造を形成できる。
以上の工程を必要があれば繰り返し、アニールして配線
・電極としてのドープド・ポリシリコン膜を形成する。
A semiconductor substrate is placed in a low pressure CVD apparatus. The semiconductor substrate is placed horizontally and the gas flow is introduced from below and exhausted from above. Reaction temperature 580 ° C, reaction pressure 0.5 Torr, SiH 4 gas 200sccm
Thermally decomposes the SiH 4 gas to form a first undoped polysilicon film on the semiconductor substrate. Next, without exposing the semiconductor substrate to the outside air, the reaction temperature is 58%.
PH 3 gas is thermally decomposed at 0 ° C., reaction pressure 0.5 Torr, pH 3 gas flow rate 50 sccm, and P is coated on the undoped polysilicon film. Reaction temperature 580 ° C, reaction pressure 0.5 Torr, Si 2 H 6 gas flow rate 200sccm without continuous exposure to outside air.
Is supplied into the apparatus, and the first undoped
A second undoped polysilicon film is formed on the polysilicon film. Thus, a structure in which the P layer exists between the undoped polysilicon films can be formed.
The above steps are repeated if necessary, and annealing is performed to form a doped polysilicon film as a wiring / electrode.

この場合のガスの流出パターンを第3図に示した。T1
はSiH4,T2はpH3,T3はSi2H6とSiH4の流出時間をあらわし
ている。この方法を用いると、不純物の被服した第1の
アンドープド・ポリシリコン膜上に第2のアンドープド
・ポリシリコン膜を形成する際のインダクションタイム
を短縮することができ(第1図),ドープド・ポリシリ
コン膜の堆積速度は向上する(第2図)。
FIG. 3 shows the gas outflow pattern in this case. T 1
Represents the outflow time of SiH 4 , T 2 represents pH 3 and T 3 represents the outflow time of Si 2 H 6 and SiH 4 . By using this method, the induction time for forming the second undoped polysilicon film on the first undoped polysilicon film covered with impurities can be shortened (FIG. 1), and the doped polysilicon can be reduced. The deposition rate of the silicon film increases (FIG. 2).

なお、第3図の第2のアンドープド・ポリシリコン膜
を形成する際のガスの流出時間T3において、Si2H6ガス,
SiH4ガスを順次流入させたが、第4図のように並行して
流出される場合も同様な結果が得られる。また、本実施
例は、反応温度580℃におけるドープド・ポリシリコン
膜の堆積に関するものであるが、反応温度580℃以外の
場合でもよい。さらに、堆積する膜がアモルファスシリ
コン膜の場合でもよい。また反応圧力は本実施例以外の
値をとっても良い。
In addition, in the gas outflow time T3 when forming the second undoped polysilicon film of FIG. 3 , the Si 2 H 6 gas,
Although the SiH 4 gas is sequentially introduced, the same result can be obtained when the SiH 4 gas is discharged in parallel as shown in FIG. Although the present embodiment relates to the deposition of a doped polysilicon film at a reaction temperature of 580 ° C., a case other than the reaction temperature of 580 ° C. may be used. Further, the film to be deposited may be an amorphous silicon film. In addition, the reaction pressure may take a value other than that of this embodiment.

[発明の効果] 以上の結果から、本発明を用いることによって、イン
ダクションタイムを短縮させ半導体膜の実効的堆積速度
を向上することができる。
[Effects of the Invention] From the above results, it is possible to shorten the induction time and improve the effective deposition rate of the semiconductor film by using the present invention.

【図面の簡単な説明】[Brief description of the drawings]

第1図は、ガス流出時間T3に対するアンドープド・ポリ
シリコン膜厚の関係を示した図,第2図はドープド・ポ
リシリコン膜堆積時間に対するドープド・ポリシリコン
膜厚の関係を示した図,第3図および第4図は本発明の
実施例に係わるガス流出時間に対するSiH4,pH3,Si2H6
流出のパターン図である。
Figure 1 is a diagram showing the relationship of undoped polysilicon thickness for gas outflow time T 3, FIG. 2 shows the relationship between the doped polysilicon film thickness for doped polysilicon film deposition time diagram, the 3 and 4 are pattern diagrams of the outflow of SiH 4 , pH 3 and Si 2 H 6 with respect to the outflow time of the gas according to the embodiment of the present invention.

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板上に不純物を含まない第1の半
導体膜を形成する工程と、前記第1の半導体膜表面に不
純物を吸着・拡散させ不純物層を形成する工程と、Si2H
6およびSi3H8の内少なくとも1つを含む反応ガスの熱分
解により前記不純物層上に第2の半導体膜を形成する工
程とを備えたことを特徴とする半導体装置の製造方法。
Forming a first semiconductor film 1. A no impurities on a semiconductor substrate, forming a first semiconductor film impurity layer is adsorbed and diffused impurities on the surface, Si 2 H
Forming a second semiconductor film on the impurity layer by thermal decomposition of a reaction gas containing at least one of Si 6 and Si 3 H 8 .
【請求項2】Si2H6およびSi3H8の内少なくとも1つを含
む反応ガスがSiH4を含んでいることを特徴とする請求項
(1)記載の半導体装置の製造方法。
2. A method according to claim 1, wherein the reaction gas containing at least one of Si 2 H 6 and Si 3 H 8 contains SiH 4 .
【請求項3】不純物層の不純物がP,As,Sb,B,Al,Gaのう
ち少なくとも1つであることを特徴とする請求項(1)
記載の半導体装置の製造方法。
3. The semiconductor device according to claim 1, wherein the impurity in the impurity layer is at least one of P, As, Sb, B, Al, and Ga.
The manufacturing method of the semiconductor device described in the above.
JP19312490A 1990-07-23 1990-07-23 Method for manufacturing semiconductor device Expired - Lifetime JP2829102B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19312490A JP2829102B2 (en) 1990-07-23 1990-07-23 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19312490A JP2829102B2 (en) 1990-07-23 1990-07-23 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0479314A JPH0479314A (en) 1992-03-12
JP2829102B2 true JP2829102B2 (en) 1998-11-25

Family

ID=16302663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19312490A Expired - Lifetime JP2829102B2 (en) 1990-07-23 1990-07-23 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2829102B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101572228B (en) 2008-04-28 2011-03-23 中芯国际集成电路制造(北京)有限公司 Methods for forming polysilicon thin film and gate

Also Published As

Publication number Publication date
JPH0479314A (en) 1992-03-12

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