JP2827246B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device including a capacitor.

[Conventional technology]

Conventionally, when a capacitive element is incorporated in a semiconductor integrated circuit, a method of forming a PN junction inside a semiconductor substrate and using a junction capacitor, or forming an insulating film on the surface of the semiconductor substrate and forming a polycrystalline silicon on the insulating film Or MOS with metal electrodes
A method using a capacity is known.

[Problems to be solved by the invention]

However, producing a capacitive element by the above-described method involves problems such as limitations in the manufacturing process and a small capacitance value. In the junction capacitance, the impurity concentration and the shape of the PN junction are restricted by the impurity concentration of the semiconductor layer forming the PN junction, that is, the semiconductor substrate (silicon substrate) used for forming the circuit and the manufacturing process for forming the peripheral elements. Is done. In addition, since the capacity per unit area of the MOS capacitor is small, when a large-capacity element is incorporated in a semiconductor device, the area occupied by the capacity increases, which hinders integration. Therefore, it is difficult to incorporate a large-capacity capacitive element into a semiconductor integrated circuit without hindering integration in the conventional technology.

An object of the present invention is to provide a semiconductor device in which a large-capacity element is incorporated without hindering integration, and a method for manufacturing the same.

[Means for solving the problem]

In order to achieve the above object, in a method of manufacturing a semiconductor device according to the present invention, a step of forming a selective oxide film on one surface of a silicon substrate on which a semiconductor element is to be formed; Forming a mortar-shaped dug portion in contact with a film, forming polycrystalline silicon in contact with a side surface of the dug portion and the selective oxide film, and forming a capacitor using the polycrystalline silicon as one electrode. And forming a device.

[Action]

In the manufacture of a semiconductor integrated circuit, each element is usually formed on one surface of a silicon substrate. On the other side, a semiconductor device incorporating a large-capacity element can be obtained without hindering the degree of integration.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps. In this embodiment, a case will be described in which a capacitor and an N-channel MOS transistor are formed as semiconductor elements using a P-type silicon substrate.

First, in FIG. 1A, a selective oxide film 11 is formed on a P-type silicon substrate 1 by using a selective oxidation method. As the selective oxidation method, LOCOS (Local Oxidation of Sillico
n) Oxidation method is common.

Next, as shown in FIG. 1 (b), after forming a gate oxide film 12 in the semiconductor element region, polycrystalline silicon 13 for a gate electrode is grown. On the other hand, on the back surface of the silicon substrate 1,
A photoresist 21 is formed by a photolithography technique, and using the mask as a mask, a dug portion 22 is formed by, for example, a sputter etching method so that the side surface has a mortar shape.

Next, as shown in FIG. 1C, after introducing P ^<+> diffusion region 23 by introducing boron into the dug portion 22, an oxide film 24 is formed, for example, to 100 nm.

Subsequently, as shown in FIG. 1 (d), polycrystalline silicon 31 for electrodes is formed, and phosphorus diffusion is performed to impart conductivity.

Subsequently, as shown in FIG. 1 (e), a photoresist 32 for forming an electrode is dug into
Is applied to the back surface of the silicon substrate 1 so as to be completely buried, and then the electrode 33 is formed by performing etch-back.

Subsequently, as shown in FIG. 1 (f), a gate electrode 42, a source region 43, and a drain region 44 are formed in the semiconductor element region, and then the electrode 33 is oxidized to form a dielectric 34.

Finally, as shown in FIG. 1 (g), after forming an interlayer insulating film 51, in a semiconductor element, a hole for extracting an electrode is formed to form an Al electrode 45. On the other hand, in the capacitive element, an upper Al electrode 53 is formed by forming a hole for taking out an electrode in the interlayer insulating film 51 and the selective oxide film 11, and a lower Al electrode 52 is formed.

In such a structure, since the side surface of the dug portion mainly constitutes the capacity, the surface area is increased, and a large capacity is obtained.
Moreover, in the configuration of the semiconductor device, the element area occupying the surface of the silicon substrate does not increase, so that the integration is not hindered.

In this embodiment, an oxide film obtained by thermally oxidizing polycrystalline silicon is used as a dielectric, but a high-dielectric material may be grown or vapor-deposited instead. In addition, although the plasma etching is used to form the dug portion, it may be formed by anisotropic etching using, for example, a hydrazine aqueous solution.

〔The invention's effect〕

As described in detail above, according to the present invention, since the capacitive element is formed using the side surface of the dug portion formed from the back surface of the silicon substrate, a large capacity can be easily obtained, and further, in the configuration of the semiconductor device, Since the element area occupying the silicon substrate surface does not increase, it does not hinder integration.

Further, in the case where two semiconductor elements are arranged with the capacitive element according to the present invention interposed therebetween, at least the insulator is formed in an island shape from the front surface to the rear surface of the silicon substrate. There is no current path at that point, and some but not complete isolation is possible. For example, in a case where a capacitor according to the present invention is formed between a PMOS and an NMOS in a CMOS, there is an effect that a latch-up phenomenon can be reduced.

[Brief description of the drawings]

1 (a) to 1 (g) are sectional views showing the structure of each step of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 11 ... Selective oxide film 13 ... Polycrystalline silicon for gate electrode 21 ... Photoresist, 23 ... P ⁺ diffusion region 24 ... Oxide film, 31 ... Polycrystalline silicon for electrode 32 ... Photoresist for electrode formation, 33 ... Electrode 34 ... Dielectric, 42 ... Gate electrode 43 ... Source region, 44 ... Drain region 45 ... Al electrode, 51 ... Interlayer insulating film 52 ... Lower Al electrode, 53 ... Upper Al electrode

Claims (1)

(57) [Claims] A step of forming a selective oxide film on one surface of a silicon substrate on which a semiconductor element is to be formed; and a step of forming a dug portion in contact with the selective oxide film on another surface of the silicon substrate. A step of forming polycrystalline silicon in contact with a side surface of the dug portion and the selective oxide film; and a step of forming a capacitive element using the polycrystalline silicon as one electrode. Production method.