JP2822281B2 - Accompaniment information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an accompaniment information processing apparatus used for, for example, an electronic musical instrument, and more particularly, to detecting a pitch specified by a pitch specifying means such as a keyboard and performing predetermined processing on the accompaniment information. The present invention relates to an accompaniment information processing device that stores as an accompaniment.

[0002]

2. Description of the Related Art Conventionally, as an accompaniment information processing apparatus used for an electronic musical instrument or the like, there is an electronic musical instrument with an automatic performance device disclosed in Japanese Patent Application Laid-Open No. 62-187388, for example. According to the present invention, the chord type and chord root of a chord are stored only when a chord is established by the key depression state of the keyboard.

As another accompaniment information processing apparatus, there is, for example, an automatic performance apparatus disclosed in Japanese Patent Application Laid-Open No. 1-179087. According to the present invention, when a chord is formed, the chord type and chord root of the chord are stored, and when the chord is not formed, the constituent sounds at that time are stored, for example, up to several tones.

The invention disclosed in the above publication has a certain effect from the viewpoint of efficiently storing chord information, but has the following disadvantages.

[0005] When a chord is formed, only the chord type and chord root of the chord are stored, so that it is impossible to determine the lowest note on the keyboard. Also, it is impossible to determine in which octave the chord is pressed. Therefore, at the time of reproduction, only fixed processing such as, for example, setting the chord root to the lowest tone and reproducing at a specific octave can be performed, and faithful reproduction of accompaniment cannot be performed.

When a chord is not established, the constituent sound at that time is stored by a note name, so that when the chord is not established, the amount of information to be stored increases.

When a chord is not established, Major or original information for chord unsuccess is stored and reproduced as an accompaniment pattern, so that the flow of performance does not come to life.

Although the formation as a chord is memorized carefully, it is not possible to detect whether or not there is a key-on in the accompaniment area and memorize it.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned drawbacks, and by adding specific sound information to chord information when a chord is established, the contents at the time of recording can be faithfully reproduced. It is an object of the present invention to provide an accompaniment information processing device capable of reproducing.

It is another object of the present invention to provide an accompaniment information processing apparatus capable of reducing the amount of information to be stored while utilizing the flow of performance even when chords are not established.

[0011]

[0012]

According to the present invention, there is provided an accompaniment information processing apparatus comprising: a pitch designation unit for designating a pitch; and a specific tone including octave identification information based on the pitch information designated by the pitch designation unit. Specific sound information generating means for generating information; constituent sound detecting means for detecting constituent sounds of the pitch information specified by the pitch specifying means; and detecting presence or absence of constituent sounds detected by the constituent sound detecting means Key-on detecting means, chord information generating means for detecting chords from the constituent sounds detected by the constituent sound detecting means to generate chord information, and identification including octave identification information generated by the specific sound information generating means. Sound information, presence or absence of a constituent sound detected by the key-on detecting means,
And storage means for storing the chord information generated by the chord information generation means in a time-series manner in association with each other.

Further, the accompaniment information processing apparatus according to the present invention comprises a pitch specifying means for specifying a pitch, a constituent sound detecting means for detecting a constituent sound of the pitch information specified by the pitch specifying means,
When it is determined that a chord is formed by the constituent sounds detected by the constituent sound detection means, chord information is generated, and when it is determined that the chord is not formed, correction information for the immediately preceding constituent sound information is generated. And a storage means for storing the chord information or the correction information generated by the chord / correction information generating means in a time-series manner. In the above configuration, the correction information generated by the chord / correction information generating means is information relating to a pitch relative to a chord.

[0014]

[0015]

The first accompaniment information processing apparatus according to the present invention associates the detected chord information with specific sound information relating to the chord information, for example, information relating to the lowest or highest note of the chord component, octave information, and the like. It is intended to be memorized.

Thus, even if the chords have the same constituent tone, the chords can be reproduced in a predetermined variation by developing the chords with reference to the lowest or highest chord. Can reproduce the chord, and the accompaniment at the time of recording can be faithfully reproduced.

A second accompaniment information processing apparatus according to the present invention
Unsuccessful chords are made by paying attention to the characteristic that they often occur due to extra keys being pressed or released in the process of shifting from a predetermined chord to the next chord. Is detected, the change from the chord information stored immediately before is stored as correction information.

This makes it possible to greatly reduce the amount of information to be stored when a chord is not established. Further, when a chord is not established, the chord information immediately preceding is regarded as important, and for example, at least the chord information used at least for the chord type is used, so that the flow of the performance is natural.

[0019]

[0020]

[0021]

FIG. 1 is a schematic block diagram showing the overall configuration of an electronic musical instrument including an accompaniment information processing apparatus according to the present invention.

In FIG. 1, reference numeral 10 denotes an interface circuit for performing serial input / output. This interface circuit 1
0 indicates MIDI (Musical) between the device and an external device.
It sends and receives In-strument Digital Interface (Information) information.

The interface circuit 10 has a "MIDI IN" terminal and a "MIDI OUT" terminal on the external device side. The CPU side is the system bus 30
Is to be connected to. The external device uses a standardized MIDI interface to control the CP.
The U side transmits and receives information by a key code (key number).

Here, the key number is a number assigned to each key of the keyboard and conforms to the MIDI standard. C _-1 = 0, C ₀ = 12, C ₁ = 24, C ₂ = 3.
6,... Are values that increase by “12” in one octave.

The interface circuit 10 outputs an interrupt request signal. This interrupt request signal is supplied to the interrupt terminal INT2 of the CPU 16. By activating this interrupt signal, the interface circuit 10 interrupts the CPU 16 and sends the interrupt signal from the interface circuit 10 to the RAM 18.
Request for information transfer to the MIDI buffer in the.

Reference numeral 11 denotes a key switch. The key switch 11 is provided corresponding to each key of the keyboard, and is a switch that is turned on / off by key press / key release. The output of the key switch 11 is the key scan circuit 1
2 is supplied.

The key scan circuit 12 includes the key switch 1
1 for detecting the on / off state. The ON / OFF state of the key switch 11 detected by the key scan circuit 12
The OFF state is output to the system bus 30 as a key code (key number). Also, this key scan circuit 1
2 outputs an interrupt request signal. This interrupt request signal is supplied to the interrupt terminal INT3 of the CPU 16. The key scan circuit 12
By activating this interrupt request signal,
The CPU 16 is interrupted, and the key scan circuit 12
Requesting transfer of the key number to the manual buffer in the RAM 18.

Reference numeral 13 denotes a panel switch, which comprises a tone switch, a volume switch, and the like provided on a panel (not shown). The output of the panel switch 13 is supplied to a panel scan circuit 14.

The panel scan circuit 14 detects the on / off state of the panel switch 13. The panel switch 13 detected by the panel scan circuit 14
Is output to the system bus 30 as a number (tone number) corresponding to the panel switch 13.

Reference numeral 15 denotes a timer. This timer 15
Used to control tempo speed. An arbitrary count value is set in the timer 15 by the CPU 16. The timer 15 generates an interrupt request signal when the counting of the set count value is completed. The interrupt request signal output from the timer 15 is supplied to an interrupt terminal INT1 of the CPU 16. The CPU 16 synchronizes with the interval of the interrupt request signal generated by the timer 15.
Control tempo speed.

The CPU 16 controls the entire electronic musical instrument of this embodiment and implements various functions as an accompaniment information processing device.

That is, when the key number as the pitch information is received, in order to produce the tone selected at that time,
The tone generator 21 is driven. Further, based on the key number, chord information and correction information are detected, and an automatic performance is performed. Further, control for storing and reproducing the chord information and the correction information detected above is performed. The processing contents of the CPU 16 will be described later in detail.

Reference numeral 17 denotes a read only memory (hereinafter referred to as "RO").
M ”. ). This ROM 17 contains the CP
A program for operating the U16, a chord table for detecting a chord (details will be described later), and the like are stored.

Reference numeral 18 denotes a random access memory (hereinafter referred to as "R
AM ". ). The RAM 18 has a CPU
Sixteen work registers, a code sequencer storage area, a MIDI buffer, a manual buffer, a disk buffer, a new key area, an old key area, and the like are defined. Details of these will be described later.

Numeral 19 denotes a disk drive circuit for controlling the disk drive 20. The disk drive circuit 19 performs a process of writing performance information to a disk device 20 as storage means and reading performance information from the disk device 20 in the same manner as MIDI input / output. At this time, in order to use the disk device 20 efficiently, RA
Data is transferred in block units (for example, 256 to 1024 bytes) via a disk buffer provided on the M18.

Also, from the disk drive circuit 19,
An interrupt request signal is output. This interrupt request signal is sent to the interrupt terminal INT of the CPU 16.
4 is supplied. By activating this interrupt request signal, the disk drive circuit 19
To request the transfer of data from the disk device 20 to the disk buffer in the RAM 18.

Reference numeral 21 denotes a tone generator circuit. This sound source circuit 21
Generates a digital tone signal in a time-division manner on the basis of the key number and tone number of 32 channels assigned by the CPU 16. The digital tone signal generated by the tone generator 21 is supplied to a D / A converter 22.

The D / A converter 22 converts an input digital tone signal into an analog tone signal. The analog tone signal converted by the D / A converter 22 is
The sound is supplied to the sound system 23.

The sound system 23 converts an analog tone signal as an input electric signal into an acoustic signal. That is, the sound system 23 is a sound generating unit represented by, for example, a speaker or a headphone, and emits sound.

The above interface circuit 10, key scan circuit 12, panel scan circuit 14, timer 15, C
The PU 16, the ROM 17, the RAM 18, the disk drive circuit 19, and the tone generator 21 are connected to each other via a system bus 30.

Next, the operation of the above configuration will be described. FIG. 2 shows a main flowchart of the accompaniment information processing apparatus according to the embodiment of the present invention.

First, when a power-on or reset operation is performed, initialization is performed (step S10).
0). In the initialization processing, initialization of various hardware, initial value setting, initialization of the contents of the RAM 18, and the like are performed.

Next, it is checked whether or not there is an ON event of the REC switch (step S101). This R
The EC switch is one of the panel switches 13. The REC switch converts the chord information detected in the chord detection processing (step S112) performed later into RA
This is a switch for instructing whether or not to store in the code sequencer in M18.

If it is determined in step S101 that an REC switch ON event has occurred, the REC flag is set to "1" and the PLY flag is set to "0" (step S102). The REC flag and the PLY flag are flags defined in a predetermined area in the RAM 18. On the other hand, when it is determined that there is no REC switch ON event, the above step S102 is skipped.

Next, it is checked whether or not there is an ON event of the PLY switch (step S103). This P
The LY switch is also one of the panel switches 13. The PLY switch is a switch for instructing whether or not the chord information stored in the chord sequencer in the RAM 18 is reproduced according to the tempo speed.

If it is determined in step S103 that the PLY switch has been turned on, the PLY flag is set to "1" and the REC flag is set to "0" (step S104). On the other hand, if it is determined that there is no PLY switch ON event, the process proceeds to step S10
4 is skipped.

As can be understood from the above processing, PLY
The flag and the REC flag do not become "1" at the same time, and therefore, the storage of the detected chord information and the reproduction of the stored chord information cannot be performed at the same time.

Next, it is checked whether there is an ON event of the START switch (step S105). This START switch is one of the panel switches 13.
Switch. The START switch is a switch for instructing whether or not to start processing for detecting and storing chords (REC processing) or processing for reproducing stored chord information (PLY processing).

If it is determined in step S105 that the start switch ON event has occurred, the RU
The N flag is set to "1" (step S106).
This RUN flag is a flag defined in a predetermined area in the RAM 18.

Further, the pointer PNT of the code sequencer and the timer counter TIMN in the RAM 18 are cleared to zero (step S107). The pointer PNT indicates the data position of the code sequencer currently being read or recorded. The timer counter TIMN responds to the interrupt request signal from the timer 15 during RUN (R
This counter is incremented on condition that the UN flag is “1”) (see FIG. 15A). These are all provided in the RAM 18.

On the other hand, if it is determined that there is no ON event of the START switch, the process proceeds to step S10.
6, S107 is skipped.

Next, key data mixing processing is performed (step S108). The key data mixing process is a process of calculating the logical sum of the MIDI input key number, the manual input key number, and the disk reproduction key number. The MIDI input key number, manual input key number, and disc playback key number are respectively
It is stored in the MIDI buffer, manual buffer and disk buffer of the RAM 18. By this mixing process, new key information for the key numbers 0 to 127 is created in the new key area in the RAM 18.

Next, the presence or absence of a key event is checked (step S109). This is performed by taking the exclusive OR of the contents of the new key area and the contents of the old key area in the RAM 18 and checking whether or not the result is zero. Therefore, the presence / absence of key events of the MIDI input key number, the manual input key number, and the disc reproduction key number can be commonly checked.

Here, when it is determined that there is no key event, the processing sequence proceeds to step S116. That is, chord detection processing, REC processing, and the like are not performed.
On the other hand, if it is determined that a key event has occurred, it is checked whether the key number of the key having the key event is equal to or less than the key number of the split point (SP) (step S110).

Here, the split point (SP) is a key number indicating a boundary of a keyboard for performing chord detection. Normally, an area having a key number equal to or smaller than the split point is a key of the chord area and is a target of chord detection. Therefore, when performing chord detection, it is necessary to determine whether the key number is above or below the split point. Of course, a chord may be detected in all key areas. In this case, SP may be set to 127. This split point is usually configured to be variable.

In step S110, the key number of the key having the key event is changed to the split point (S
If it is determined that the key number is larger than the key number of P), the key is out of the chord detection target, so that the following chord detection processing, R
The EC processing is not performed, and the processing sequence is step S1.
Move to 15. Therefore, a sound generation process (step S115) by a normal key press is performed.

On the other hand, if it is determined that the key number is equal to or less than the key number of the split point (SP), note channel assignment processing is executed (step S111). Here, note channel assignment is a process in which a chord has an extra sounding channel corresponding to each of the special 12 notes, and only one sound can be sounded for the same note name (note). This note channel assignment is used for automatic accompaniment (auto accompaniment, auto arpeggio) and is carved at appropriate timing.

Next, chord detection processing is executed (step S112). For details of this chord detection process,
It will be described later.

Next, it is checked whether or not "REC = 1 and RUN = 1" (step S113). That is, it is checked whether or not it is specified that chord information should be stored. If it is determined that the chord information should be stored, REC processing is performed (step S114). That is, a process of storing the detected chord information in the chord sequencer in the RAM 18 is performed. Details of this REC processing will be described later. On the other hand, if it is determined in step S113 that it is not specified that chord information should be stored, this REC
Processing is skipped.

Next, a tone generation control process is performed (step S115). In this sound generation control process, an upper tone or a lower tone is selected depending on whether a key number having a key event is above or below a split point, and sound is generated according to the key event. That is, if the event is a key on event, the key is assigned to one of the channels to start sounding. If the event is an off event, the channel with the corresponding key number is searched for and the sounding is shifted to the release state.

Next, it is checked whether "PLY = 1 and RUN = 1" (step S116). That is, it is checked whether or not reproduction of chord information is designated. When it is determined that the reproduction of the chord information is designated, the PLY processing is performed, and the chord information stored in the chord sequencer in the RAM 18 is reproduced (step S117). Details of the PLY processing will be described later.

In this PLY processing, the above-mentioned step S111
When the same processing as the note channel assignment processing performed in step S115 is performed, then the same tone generation control as performed in step S115 is performed (step S118).

On the other hand, if it is determined in step S116 that reproduction of chord information has not been designated, this PLY
The process (step S117) and the tone generation control process (step S118) are skipped.

Next, "other processing" is performed (step S119). In this "other processing", processing other than those described above, which is not directly related to the present invention, such as panel processing, MIDI output processing, disk device writing processing, and other automatic performance processing (auto-base processing, etc.) are performed. Thereafter, the process returns to step S101, and the same processing is repeatedly executed.

The automatic performance process is performed by a CO
This is performed by referring to the contents of the DO register and the ROTO register and the contents of the note channel assignment.

Next, step S1 of the main routine is executed.
The details of the chord detection processing performed in Step 12 will be described.

FIGS. 3 and 4 are flowcharts showing a first embodiment of the chord detection process.

First, of the key numbers in the chord area, the note number of the highest note is put in the HIGB register and the note number of the lowest note is put in the LOWB register (step S2).
00). Here, the HIGB register and the LOWB register are registers defined in the RAM 18. These H
An octave number is also stored in the IGB register and the LOWB register at the same time.

Here, the note number is C = 000.
0 _B , C♯ = 0001 _B , D = 0010 _B , D♯ = 0
_{011 B, E = 0100 B,} F = 0101 B, F♯
= 0110 _B , G = 0111 _B , G♯ = 1000 _B ,
_{A = 1001 B, A♯ = 1010} B, B = 1011
_B. Here, the suffix “ _B ” indicates a binary number, and is used in the same meaning hereinafter.

The octave number is B ₁ or less =
_{00 B, C 2 ~B 2 =} 01 B, C 3 ~B 3 = 10 B, C
₄ or more = 11 _B.

Next, for the on / off state of the key in the chord area, a logical sum is calculated for each octave, and the result is stored in the BITB register as a bit string (step S201). The BITB register is as shown in FIG.
This is a 12-bit register defined in the RAM 18.

Next, it is checked whether or not the contents of the BITB register are all zero, that is, whether or not there is any key turned on in the chord area (step S).
202).

When it is determined that all the bits are zero, the CODB register is set to "0" and the ROTB register is set to "F _H " (the subscript " _H " indicates a hexadecimal number. Hereinafter, the same applies). .), The POSB register is set to “00 _B ”, the BITO register is set to “0” (step S203), and thereafter, the process returns from the main chord detection routine.

Here, the CODB register, the ROTB register, the POSB register, and the BITO register are registers defined in the RAM 18.

The CODB register is a register for storing a code type. There are seven code types shown on the right side of Table 1, each of which is represented by a code value of “0 to 7”. Putting “0” in this CODB register means that there is no key-on in the chord area.

[0076]

[Table 1] The ROTB register is a register that stores a code route. The chord root is represented by the same code as the note number, C = 0000 _B , C♯ = 0001 _B , D = 00
There are 12 types of 10 _B ,..., B = 1011 _B. This R
Putting "F _H " in the OTB register means that there is no corresponding code root.

The POSB register is a register for storing a correction sound. Putting “00 _B ” in the POSB register means that there is no corrected sound described later.

The BITO register stores the bit string obtained in the current chord detection processing, that is, the contents of BITB, and is referred to in the next chord detection processing.

If it is determined in step S202 that the contents of the BITB register are not all zero, that is, that there is any key-on in the chord area, the RTAT register is cleared (step S204). This RTAT
The register is a register defined in the RAM 18,
The number of times the bit string has been rotated and shifted is stored.

Next, the contents of the BITB register are
It is stored in the A register (step S205). This BIT
The A register is a register defined in the RAM 18, and is a working register for rotating and shifting a bit string.

Then, it is checked whether or not the lower three bits of this BITA register are "001 _B " (step S).
206). This focuses on the fact that, as shown in Table 1, when the code is established, the lower three bits become "001 _B ". If all are zero, it has been checked in step S202 and has already been excluded.

If it is determined in step S206 that the lower 3 bits of the BITA register are not "001 _B ", the contents of the RTAT register are incremented (step S207), and then the BITA register is rotated by one bit. (Step S208). The direction of the rotate shift may be either left or right.

Next, when the content of the RTAT register is "1"
2 ”, that is, the BITA register is set to 12
It is checked whether or not the rotation shift has been performed one time (step S209). If it is not "12", the process returns to step S206, and the operations of steps S206 to S209 are repeated.

In this repetitive execution process, if it is determined in step S209 that the number has become "12", it is determined that the chord chord has not been established, and step S2 is performed.
The processing in the case where 10 or less codes are not established is executed.

That is, first, the CODB register and the ROT
Put “F _H ” into each of the B registers (step S
210). Here, the content of the CODB register is “F _H ”.
Means that there was a key-on in the chord area, but the chord was not established.

Next, the contents of the BITB register and the contents of the BITO register containing the bit string obtained in the previous chord detection processing are exclusive ORed (indicated by the symbol “∀” in the figure), and the result is obtained. Is stored in the BITX register.
(Step S211). Here, the BITX register is
This register is defined in the RAM 18 and stores bits that have changed in the current bit string with respect to the previous bit string. By taking the exclusive OR, the changed bit is stored in the BITX register as "1".

Next, step S211a is executed.
This step may be omitted. In other words, when omitted, the contents of the BITO register do not change when the chord is not established, and the information stored in the memory is always the chord chord that was established before (although it is one when all keys are released). ), The current basic chord is easy to understand.

On the other hand, if step S211a is not omitted, the contents of the BITO register indicate that the code
Information that changes regardless of failure and is stored in memory
Since there are always only the changed bits for the bitmap that entered this routine immediately before, the amount of stored information can be kept to a minimum.

Next, data in the format shown in FIG. 6B is created. Each register in which these data are stored is defined in the RAM 18. That is, BI
The bit set to “1” in the TX register is converted into a note number and put in the NOTB register (step S2).
12). The NOTB register is a register that stores a note number.

Next, it is determined whether the bit which has become "1" in the BITX register is newly turned on or off this time by referring to the BITB register, and the result is stored in the ON / OF register. (Step S213).

Next, the NOTB register is compared with the HIGB register and the LOWB register to create a correction sound and put it into the POSB register (step S214). That is, it is checked whether or not the contents of the NOTB register and the contents of the HIGHB register or the contents of the LOWB register are the same.
Store in SB register. If NOTB = HIGB, POSB = 10 _B (highest sound) If NOTB = LOWB, POSB = 01 _B (lowest sound) If none of the above, POSB = 11 _B (intermediate sound) In the case of none, POSB = 00 _B is entered.

Next, the octave number of the LOWB register is taken out and put into the OCTB register (step S215). Next, the contents of the OCTB register are
It is stored in the O register (step S216). Where O
The CTO register is a register defined in the RAM 18 and stores the octave number obtained in the previous chord detection processing. And this step S2
After the end of the process in step 16, the main chord detection routine is returned. Thus, the processing in the case where the code is not established is terminated.

On the other hand, in step S206, BITA
When it is determined that the lower three bits of the register are “001 _B ”, data in the format shown in FIG. 6A is created. That is, a bit string composed of 9 bits excluding the lower 3 bits of the BITA register is created (step S217). For example, if the contents of the BITA register are

BITA = “000001000011”
, A 9-bit bit string of bit string = “000010110” is obtained.

Next, the code string and the quasi-code route read from the corresponding address are put into the CODB register and the ROTB register, respectively, by referring to the code table configured as shown in Table 2 using the bit string as an address (step S1). S218). That is, if the code is not established, "FF _H " is obtained, and if the code is established, code types 0 to 7 and quasi-code routes 0 to B _H are obtained. Put the 4-bit quasi-code route into the ROTB register.

[0096]

[Table 2] Then, CODB register, the contents of ROTB register checks whether or not it is both "F _H" (step S21
9). That is, it is checked whether or not the code is not established.

Here, when it is determined that the contents of both the CODB register and the ROTB register are "F _H ", it is recognized that the code has not been established, and step S2 is executed.
Branch to 11. Since the processing after step S211 is as described above, the description is omitted here.

On the other hand, if it is determined in step S219 that either the content of the CODB register or the content of the ROTB register is not “F _H ”, the quasi-code route of the ROTB register obtained with reference to Table 2 RTA that stores the number of rotation shifts
The contents of the T register are added, and the result is put into the ROTB register (step S220). However, when the addition result becomes a value larger than “12”, “12” is subtracted. As a result, a real code root (primary code root) is obtained in the ROTB register.

Next, the contents of the CODB register are
The contents of the ROTB register are stored in the ROTO register and the contents of the BITB register are stored in the BITO register in the O register (step S221).

Next, a process of representing the lowest note in the key-on of the chord area with a small number of bits (2 bits) is performed (step S222).

That is, in Table 1, the primary code root (R
(Stored in the OTB register) to determine how far the lowest note (LOWB register) exists.

Actually, L is determined from the contents of the ROTB register.
The contents of the OWB register are subtracted, and if the result is equal to or greater than "12", "12" is subtracted. If the result is negative, "12" is added and entered into the SUBT register. Then, the values “0 to 11” obtained in the SUBT register are categorized as follows and put into the MINB register.

When the contents of the SUBT register are 0, 1, and 2, the MINB register ← 00 _B When the contents of the SUBT register are 3, 4, and 5, the MINB register
Register ← 01 _B When the contents of the SUBT register are 6, 7, and 8, MINB
Register ← 10 _B When the contents of the SUBT register are 9, 10, and 11, MINB
Register ← 11 _B As is clear from Table 1, this utilizes the characteristic that when the chord root is divided into three tones into four equal parts, each block has only one key-on.

In order to more reliably obtain the value to be stored in the MINB register, the number of key-ons is counted from the chord root, and the value at the time when it becomes the same as the note in the LOWB register may be used. good.

Next, the octave number of the LOWB register is stored in the OCTB register (step S22).
3).

The contents of the OCTO register and the OCT
By comparing the contents of the B register with the contents of the B register, it is checked whether or not the octave number obtained this time has been changed from the octave number obtained when the previous chord detection processing has been performed (step S224).

If it is determined that the octave has not changed, the flow branches to step S227 to set the content of the POSB register to "11 _B ", and returns that there is no octave change. At this time, the value of the POSB register is not used in the original meaning of indicating an intermediate tone, but is used in a special meaning indicating that there is no octave change.

[0108] On the other hand, when determining that the octave number in step S224 is changed, sets the contents of the POSB register to "00 _B" (step S2
25). This means that there is an octave change and no correction notes.

Next, the content of the OCTB register is
It is stored in the O register (step S226), and thereafter, the chord detection routine is returned.

In the first embodiment of the chord detection processing described above, the bit string pattern is checked by focusing on the lower three bits of the bit string. However, the present invention is not limited to this.
For example, the upper three bits may be used, and any other three bits may be used.

The number of bits to be checked as a bit pattern is not limited to 3 bits. For example, the lower 2 bits are set to “01 _B ”, and when the same bit pattern is found, the other 10 bits are set as an address. It is also possible to check whether or not a code is established by referring to a code table composed of an address one bit larger than that in Table 2.

Further, the state of "1" of the lower 1 bit is detected, and using the other 11 bits as an address, referring to a code table composed of an address two bits larger than in Table 2, it is determined whether or not the code is established. It is also possible to check.

[0113] Further, in the above embodiment, the check was always exists "1" in the bit pattern, the presence or absence of a reference to the code established a code table of the remaining 10-bit check bit pattern of "00 _B" It is also possible.

In summary, by referring to the pattern table in which one or more bits are excluded from the full pattern of 12 bits, the size of the code table can be reduced, and the memory capacity can be reduced. Can be.

Next, a second embodiment of the chord detection routine will be described with reference to the flowcharts of FIGS.

In the figure, steps S250 and S251
Are the same as steps S200 and S201 of the first embodiment. That is, of the key numbers of the chord area, the note number of the highest note is stored in the HIGB register and the note number of the lowest note is stored in the LOWB register (step S2).
50). This HIGB register and LOWB register are
The octave number can also be entered at the same time.

Next, as for the on / off state of the key of the chord area, a logical sum is calculated between the octaves, and the result is stored in the BITB register as a bit string (step S251).

Next, the contents of the BITB register are divided into two, and the upper bit string is put into the BITH register and the lower bit string is put into the BITL register (step S252).
FIG. 9 shows an example of the BITH register and the BITL register.

In the figure, BIT is set as the BITH register.
Upper 4 bits of the B register, B as the BITL register
Although the lower 8 bits of the ITB register are configured to be stored, the division method is arbitrary. That is, the number of bits in the BITH register and the BITL register is arbitrary, and the arrangement of the bits may be arbitrarily configured. Further, the number of divisions is not limited to two, but may be three or more.

Next, by referring to the first code table configured as shown in Table 3, for example, using the contents of the BITL register as an address, the corresponding information is read and stored in the REFA register (step S253).

[0121]

[Table 3] In the first code table, a pattern that can be realized as a code only by the lower bit string stores a head address for referring to the remaining upper bit string.
On the other hand, if there is no possibility that the code is already established even if only the lower bit string is viewed, “FF _H ” is stored as not established.

Next, it is checked whether or not the value is "FF _H " by referring to the contents of the REFA register (step S25).
4). Here, when it is determined that “FF _H ”,
It is determined that the chord chord has not been established, and processing is performed when the chord is not established.

That is, first, the CODB register and the ROT
Put “F _H ” into each of the B registers (step S
255). Here, the content of the CODB register is “F _H ”.
Means that there was a key-on in the chord area, but the chord was not established.

Next, the contents of the BITB register are exclusive-ORed with the BITO register containing the bit string obtained in the previous chord detection processing, and the result is stored in the BITX register (step S256). As a result, the changed bit is stored in the BITX register as "1". Next, step S256a is executed, but this step may be omitted. The respective effects when omitted or not omitted are as described in step S211a in FIG.

Next, data in the format shown in FIG. 11B is created. That is, the number (group number) of the group in which the bit set to "1" in the BITX register exists is entered in the BGRP register (step S).
257). The BGRP register is a register defined in the RAM 18.

The data stored in the BGRP register is defined as follows.

BGRP register = 00 _B : D, C♯, C BGRP register = 01 _B : F, E, D♯ BGRP register = 10 _B : G♯, G, F♯ BGRP register = 11 _B : B, A♯ , A Next, a bit string corresponding to the BGRP group number is selected from the BITB register and stored in the BPTN register (step S258).

Then, "1" is set in the BITX register.
And the HIGB register and LOW
A correction sound is created by comparing the result with the B register and stored in the POSB register (step S259). That is, it checks whether the contents of the BITX register are the same as the contents of the HIGHB register and the contents of the LOWB register, and creates data to be stored in the POSB register under the following conditions.

If α = HIGB, POSB = 10 _B (highest sound). If α = LOWB, POSB = 01 _B (lowest sound). If none of the above, POSB = 11 _B (intermediate sound). In the case where there is no correction note, POSB = 00 _B is entered.

Next, the octave number of the HIGB register is taken out and put into the OCTB register (step S260).

Next, the contents of the OCTB register are
It is stored in the O register (step S261). Then, after the processing of step S261 is completed, the main chord detection routine is returned.

On the other hand, in step S254, REFA
If it is determined that the contents of the register are not “FF _H ”, data in the format shown in FIG. 11A is created. That is, if the contents of the REFA register are not “FF _H ”, a code may be established depending on the pattern of the remaining bit strings. The corresponding data is read out with reference to the second code table configured as shown in Table 4 as the lower address.

[0133]

[Table 4] Then, the upper 4 bits (code type) of the read data are stored in the CODB register, and the lower 4 bits (code root) are stored in the ROTB register (step S26).
2).

Next, it is checked whether the contents of the CODB register and the ROTB register are both "F _H " (step S263). That is, it is checked whether or not the code is not established.

Here, when it is determined that the contents of both the CODB register and the ROTB register are "F _H ", it is recognized that the code is not established, and step S25 is executed.
Branch to 6. Since the processing after step S256 is as described above, the description is omitted here.

On the other hand, if it is determined in step S263 that either the content of the CODB register or the content of the ROTB register is not “F _H ”, the content of the CODB register is stored in the CODO register, and the content of the ROTB register is stored in the ROTO register. Register the contents of the BITB register to BI
Each is stored in the TO register (step S26)
4).

Next, in the key-on of the chord area, the process of representing the lowest note by a small number of bits (2 bits), that is, the chord root (the contents of the ROTB register) and the lowest tone (the contents of the LOWB register) Then, a process of detecting the difference between the two is performed (step S265). This process is the same as step S222 in the first embodiment, and thus the details are omitted.

Next, the octave number of the HIGB register is stored in the OCTB register (step S26).
6).

The contents of the OCTO register and the OCT
By comparing with the contents of the B register, it is checked whether or not the octave number obtained this time has changed from the octave number obtained when the previous chord detection processing has been performed (step S267).

If it is determined that the octave has not changed, the flow branches to step S270 to set the contents of the POSB register to "11 _B ", and returns that there is no octave change. Here, the value of the POSB register is not used in its original meaning to indicate an intermediate tone, but is used in a special meaning to convey that there is no octave change.

If it is determined in step S267 that the octave number has changed, the contents of the POSB register are set to "00 _B " (step S2).
68). This means that there is an octave number correction but no correction notes.

Next, the contents of the OCTB register are changed to OCT.
It is stored in the O register (step S269), and thereafter, this chord detection routine is returned.

In the second embodiment of the above-described chord detection processing, the 12-bit string is divided into high-order 4 bits and low-order 8 bits, and the low-order 8 bits are referred to first. However, the present invention is not limited to this. Absent.

For example, there is a division method as shown in FIG. When referring to the code table, it is optional to refer to the BITH register first or refer to the BITL register.

The division is not limited to two. For example, three divisions such as BITH, BITM, and BITL
It can be divided into two or more.

As described above, in short, out of all the 2 ¹² bit patterns, only a group having a possibility of code establishment is prepared as a table, and by referring to this table a plurality of times, the code table can be made smaller. Reduction can be achieved.

Next, details of the first embodiment of the REC process performed in step S114 of the main routine (FIG. 2) will be described with reference to the flowchart shown in FIG.

This REC processing routine (Embodiment 1)
Is described corresponding to the first embodiment of the chord detection process, but can be realized by substantially the same process in the second embodiment.

First, it is checked whether the contents of the CODB register and the ROTB register are both “F _H ”, that is, whether or not the code is not established (step S 300).

If it is determined that the code is not established, the flow branches to step S307. On the other hand, when it is determined that the code is established, a time difference between the time (TIMO) at which the previous change was made and the current time (TIMN) is obtained and stored in the TIMB register (step S30).
1). Then, the current time TIMN is entered in the TIMO register (step S302).

Next, as shown in FIG.
The contents of the B register and the contents of the TIMB register are stored at the address indicated by the sequence pointer PNT (step S303). Further, the contents of the CODB register and the ROTB register are stored in the sequence pointer P.
It is stored at the address indicated by NT + 1 (step S3
04). Then, the sequence pointer is incremented by "+2" (step S305).

Next, the contents of the POSB register are set to "00".
_B ”, that is, whether or not the octave number has been updated (step S306). When it is determined that there is no update, the process returns from the REC processing routine.

On the other hand, if it is determined that the octave number has been updated (the same applies to the case where the code is not established), the time at which the last change was made (TIMO) and the current time (TIMO) are made.
MN) is obtained and stored in the TIMB register (step S307). And this time TIMN
In the TIMO register (step S308).

Next, as shown in FIG.
The contents of the B register and the contents of the TIMB register are stored in the address indicated by the sequence pointer PNT (step S309). Further, the contents of the POSB register, the contents of the ON / OF register, and the contents of the NOTB register are stored in the address indicated by the sequence pointer PNT + 1 (step S310). Then, the sequence pointer is incremented by "+2" (step S31).
1). Thereafter, the process returns from the REC processing routine. Thus, the REC process ends.

Next, the details of the PLY processing performed in step S117 of the main routine (FIG. 2) will be described with reference to the flowcharts shown in FIGS.

Although the present PLY processing routine is described in association with the first embodiment of the chord detection processing,
The second embodiment can also be realized by substantially the same processing.

First, the pointer PNT currently indicates
The data read from the sequence memory in the RAM 18 is stored in the AREG register (step S400).

Next, the lower 6 bits of the AREG register are extracted and put into the TIMB register (step S40).
1). Then, at the timing (TIMO) at which the PLY processing routine was accessed last time, the TIMB determined above is used.
The value obtained by adding the contents of the register is the current timing (T
IMN) or not (step S40).
2).

Here, if it is determined that the current timing (TIMN) is smaller than "TIMO + TIMB", the process returns from the PLY processing routine as it is too early to read out new sequence data.

On the other hand, if it is determined that the current timing (TIMN) is greater than or equal to "TIMO + TIMB", it is necessary to read out new sequence data, so that the process proceeds to step S403 and subsequent steps.

That is, first, the contents of the TIMN register are set to T
The contents of the TIMO register are updated by placing the contents in the IMO register (step S403). Then, the contents of the address indicated by the sequence pointer PNT + 1 are read and put into the BREG register (step S40).
4). Then, the content of the sequence pointer PNT is changed to "+
2 "(step S405).

Then, it is checked whether or not the MSB of the BREG register is "1" (step S406). This means that the contents of the AREG and BREG registers are
It is checked whether the information is chord information when a chord is established, or octave number and correction note information when a chord is not established.

When it is determined that the MSB is "0", the following processing is performed assuming that the contents of the AREG register and the BREG register are chord information at the time of chord establishment shown in FIG. Run.

First, the upper two bits of the AREG register are extracted and put into the MINB register (step S40).
7). As a result, the lowest note information is stored in the MINB register.

Next, 3 bits are extracted from the next most significant bit of the BREG register, and
The lower 4 bits of the REG register are extracted and put into the ROTO register (step S408).

Next, the 12-tone bit string is read out from the code type stored in the CODO register with reference to the C reference code table in Table 1 and put into the BITA register (step S409).

Next, the value of BINB is
The lowest tone in the TA register is detected (steps S410 and S411). That is, if the content of the MINB register is “00 _B ”, a pattern in which the lower three bits are “1” is generated, and if the content of the MINB register is “01 _B ”, the next three bits are “1”. Is generated, and the content of the MINB register is “1”.
If 0 _B ", three more bits of the next generates a pattern is" 1 ", the contents of MINB register is" 11 _B "
If so, a pattern whose upper three bits are "1" is generated and stored in the KK register (step S410).

Then, the logical product of the value of the KK register and the value of the BITA register obtained as described above is calculated and stored in the LOWB register (step S411).

The lowest tone information MINB is “C, C♯, D”, “D♯, E,
Using the property that there is only one key-on in each of the four blocks “F”, “F♯, G, G♯”, and “A, A♯, B”, a 2-bit code is stored in the MINB register. Is stored.

That is, if MINB = 00 _B , “C, C♯, D” If MINB = 01 _B , “D♯, E, F” If MINB = 10 _B , “F♯, G, G♯ If "MINB = 11 _B," F♯, G, of the three sound of G♯ ", means that was the lowest sound has become the key-on.

Here, the difference between the chord root and the lowest note will be described. Even if the chord type and the chord root are the same, they are divided as shown in Table 5.

[0172]

[Table 5] Chord types and chord roots have been used in the past, but how to use the lowest note varies. Also,
Conventionally, when a chord is established, the lowest note is often not used.

In this embodiment, by detecting, storing and reproducing the lowest chord of the chord, for example, the constituent sound of the backing or the arpeggio can be reproduced more faithfully. It is also possible to use the lowest tone as a bass route for an auto bass performance.

Next, the contents of the BITA register are stored in the ROT
Rotate shift by the value stored in the B register and store it in the BITB register (step S41)
2). As a result, the same 12-bit string as in the REC processing has been generated.

Next, LOWB of the BITB register
Bits higher than the bits of the register are directly converted to note numbers, octave data is added according to the contents of the OCTO register, and the data is entered as key-on to the note channel (step S413). That is, in this step, since a chord is established, there are usually three to four key-on bits in the BITB register except when the chord type is “0”.

LOWB is selected from these key-on bits.
The lowest note in the register and the on-bit higher than the lowest note are detected and used as a note code. The octave number in the OCTO register is added to the note code and assigned as a key-on to the corresponding note channel.

Next, LOWB of the BITB register
Bits lower than the bits of the register are directly converted to note numbers, a value obtained by adding "1" to the contents of the OCTO register is added as octave data, and the result is entered as key-on to the note channel (step S414). That is, in this step, LOW of the BITB register
The key-on bit lower than the note name in the B register is converted to a note code, and an octave number added to the octave number stored in the OCTO register is incremented by "+1". assign.

For example, B A A G G F F D D D C C BITB = 0 0 1 0 0 1 0 0 0 0 0 0 1 CODB = Major (1) ROTB = 2 (D) LOWB = If F♯OCTB = 01 _B , the sound of F♯ is octave number = 2, the note of note number = 6 A is the octave number = 2 and the note number = 9 D is the octave number = 3, the note is octave number = 3 Number = 2.

Next, another note channel is keyed off (step S415). That is, the above step S
The other note channels not allocated in 413 and S414 are cleared, and the process returns from the PLY processing routine. When the chord type is "0", that is, when all keys are turned off, all 12 note channels are cleared.

On the other hand, if it is determined in step S406 that the MSB is "1", the AREG register
The following processing is executed assuming that the content of the BREG register is the information at the time when the code shown in FIG.

First, the upper two bits of the AREG register are extracted and put into the OCTB register (step S41).
6).

Next, the last octave number (OCT
O) and the current octave number (OCTB) are compared (step S417). If it is determined that they are different, the current octave number (OCTB) is changed to OCT.
It is stored in the O register (step S418). Then, the octave numbers O of all the note channels KYEN1 to KYEN12 are set.
The CT is corrected (Step S419).

If the same is determined in step S417, steps S418 and S419 are skipped.

Next, the relative position, on / off and note name of the corrected sound are extracted from the BREG register, and
The data is stored in the SB register, ON / OF register, and NOTB register (step S420).

Next, it is checked whether or not the content of the ON / OF register is "1" (step S42).
1). In other words, it is checked whether the correction sound is added to the current chord (on) or a certain sound is deleted from the current chord (off). When the content of the ON / OF register is "0", that is, when it is determined that a certain tone is deleted from the current chord, the channel of the same note as the content of the NOTB register in the KEYN1 to 12 is keyed off. (Step S422). Thereafter, the process returns from the PLY processing routine.

On the other hand, in step S421, ON / O
F "1" contents of the register, i.e., when adding a certain sound in the current chord is determined, it is checked whether the content of the POSB register is "00 _B" (step S4
23).

Here, the contents of the POSB register are set as follows.

POSB register = 00 _B … No correction (addition) note POSB register = 01 _B … Correction (addition) note (lowest note) POSB register = 10 _B … Correction (addition) note (highest note) POSB register = 11 _B ... Corrected (additional) note exists (intermediate tone) Therefore, if it is determined in step S423 that the content of the POSB register is “00 _B ”, there is no corrected note, and the process returns.

On the other hand, if the contents of the POSB register are "0"
If it is determined that it is not "0 _B ", there is a correction note, so a note number and an octave number are created from the contents of the NOTB register, the POSB register, and the OCTO register, and are entered as key-on in the corresponding channel (step S424).

That is, the note number is obtained from the NOTB register, and it is recognized from the contents of the POSB register whether the correction (addition) sound is to be added to the upper, lower, or middle of the current chord structure. And then OC
With reference to the octave number stored in the TO register, the octave information of the sound is referred to and assigned as a key-on to the corresponding note channel (step S42).
4).

Here, as shown in step S425, the lowest note can be set as the chord root by putting the contents of the NOTB register into the ROTO register. This process is not essential.

Thereafter, the process returns from the PLY processing routine and returns to the main routine.

Next, the interrupt processing will be described. FIG. 15 is a flowchart illustrating four types of interrupt processing of the electronic musical instrument.

FIG. 23A shows a timer interrupt process. When the timer 15 counts a predetermined value (time), an interrupt request signal is supplied to the INT1 terminal of the CPU 16, and the CPU 16 temporarily interrupts the process being executed to perform the interrupt process. That is, first, the RUN flag is set to “1”.
Is checked. This RUN flag is a flag that is set to “1” when the START switch on the panel is pressed. Therefore, it is set to "1" during operation.

Here, if it is determined that the RUN flag is not "1", that is, if it is determined that the RUN flag is not operating, the process returns from the interrupt processing routine without performing any processing.

On the other hand, when it is determined that the RUN flag is "1", the contents of the TIMN register are incremented. As a result, the current time is updated. FIG. 7B shows the MIDI interrupt processing. When the interface circuit 10 receives the data from the MIDI IN terminal, an interrupt request signal is supplied to the INT2 terminal of the CPU 16, and the CPU 16 temporarily interrupts the processing being executed to perform the interrupt processing. In this interrupt processing, the input information from the interface circuit
It is stored in the MIDI buffer of AM18. Thereafter, the process returns from the interrupt processing routine. This MIDI
The information stored in the buffer is used for various processes as described above.

FIG. 19C shows the key switch interrupt processing. When the key scan circuit 12 detects that the key switch 11 has been pressed, the
An interrupt request signal is supplied to the T3 terminal. CPU16
Performs an interrupt process by temporarily suspending the process being executed.
In this interrupt processing, the key switch information from the key scan circuit 12 is stored in the manual buffer of the RAM 18. Thereafter, the process returns from the interrupt processing routine. The information stored in the manual buffer is used for various processes as described above.

FIG. (D) shows the disk input interrupt processing. When a data transfer request occurs in the disk drive circuit 19, an interrupt request signal is supplied to the INT4 terminal of the CPU 16. The CPU 16 temporarily interrupts the process being executed and performs an interrupt process. In this interrupt processing, data supplied from the disk device 20 via the disk drive circuit 19 is stored in the disk buffer of the RAM 18. Thereafter, the process returns from the interrupt processing routine. The information stored in the disk buffer is used for various processes as described above.

Next, a second embodiment of the REC process will be described. FIG. 16 is a flowchart illustrating the processing of the REC processing routine (second embodiment).

This processing is a method of directly storing the timbre bitmap without using the chord detection routine shown in FIGS. 3 and 4 or FIGS. 7 and 8. In this process, FIG.
The chord sequence is stored in the data format shown in FIG.

First, among the key numbers of the chord area, the note number of the lowest note is entered in the LOWB register (step S900). The LOWB register also stores an octave number at the same time.

Next, the note number of the highest note is OCTB.
The data is stored in a register (step S901). Next, regarding the on / off state of the keys in the chord area, a logical sum is calculated between the octaves, and the result is used as a bit string in BITB
It is stored in a register (step S902).

Next, the time when the last change (TIM
O) and the current time (TIMN),
The data is stored in the IMB register (step S903). Then, the current time TIMN is entered in the TIMO register (step S904).

Next, as shown in FIG. 17, the contents of the OCTB register and the contents of the TIMB register are connected and stored at the address indicated by the sequence pointer PNT (step S905). Also, the lower 8 bits of the contents of the BITB register are stored in the address indicated by the sequence pointer PNT + 1 (step S906).

Furthermore, the contents of the LOWB register and BIT
The upper 4 bits of the B register are connected and stored at the address indicated by the sequence pointer PNT + 2 (step S907).

Then, the sequence pointer is set to "+3" (step S908), and the process returns from the REC processing routine.

According to this embodiment, although 3 bytes of data are always required, regardless of whether the code is established or not,
There is an advantage that data can be stored in the same data format.

Further, the note number and octave number of the lowest note are stored together with as few bits as possible, thereby improving the reproducibility in PLY.

According to the above-described embodiments, the CPU
Reduces the amount of rotate shifts and comparisons that are difficult to perform, speeds up the chord detection process, and reduces the size of the memory for storing these programs and chord tables.

Further, even when a chord is formed, specific tone information (highest tone, lowest tone) in the chord is stored together,
At the time of reproduction, a constituent sound pattern close to that at the time of recording can be obtained.

When the octave information changes, the octave information is also stored, so that the accompaniment sound at the time of reproduction can be reproduced in the sound range at the time of recording.

Further, when a chord is not established, information corresponding to a sound corresponding to a change in the previous accompaniment sound pattern is stored as correction information. Therefore, the amount of information to be stored when a chord is not established can be reduced. it can.

When a chord is not established, instead of using the Major pattern or a pattern specific to the non-establishment, emphasis is placed on the chord pattern that was formed immediately before, and at least the chord type using the chord pattern that was formed immediately before is used. Since each constituent sound is stored taking into account the change from the immediately preceding chord pattern, there is an advantage that the flow of the performance comes alive.

By treating the state in which there is no key-on in the chord area as the same pattern as one chord, it is also possible to delete accompaniment sounds instead of always adding accompaniment sounds. Thereby, unified processing can be performed and there is an effect that the processing is simplified.

Further, faithful reproduction is easily realized by a configuration in which a 12-tone bit string is always stored and specific sound information is also stored at the same time, instead of storing chord detection chord types and chord roots as references. It is something that can be done.

[0216]

As described above in detail, according to the present invention, when a chord is formed, specific sound information including octave identification information is added to the chord information and stored, so that the contents at the time of recording are faithfully reproduced. Further, it is possible to provide an accompaniment information processing apparatus capable of reducing the amount of information to be stored while making the most of the performance flow even when chords are not established.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an electronic musical instrument including an accompaniment information processing apparatus of the present invention.

FIG. 2 is a main flowchart showing a main operation of the electronic musical instrument to which the accompaniment information processing apparatus of the present invention is included.

FIG. 3 is a flowchart showing an operation of the first example of the chord detection processing of FIG. 2;

FIG. 4 is a flowchart showing an operation of the first embodiment of the chord detection processing of FIG. 2;

FIG. 5 is a diagram for explaining a format of a BITB register used in the first embodiment of the present invention.

FIG. 6 is a diagram for explaining a data format adopted in the first embodiment of the present invention.

FIG. 7 is a flowchart showing the operation of the second embodiment of the chord detection processing of FIG. 2;

FIG. 8 is a flowchart showing the operation of the second embodiment of the chord detection processing of FIG. 2;

FIG. 9 is a diagram for explaining a format of a BITB register used in a second embodiment of the present invention.

FIG. 10 is a diagram for explaining another embodiment of the present invention.

FIG. 11 is a diagram for explaining a data format adopted in a second embodiment of the present invention.

FIG. 12 is a flowchart showing the REC process (first embodiment) of FIG. 2 in detail.

FIG. 13 is a flowchart showing the PLY processing of FIG. 2 in detail.

FIG. 14 is a flowchart showing the PLY processing of FIG. 2 in detail.

FIG. 15 is a flowchart illustrating an interrupt process according to the first and second embodiments of the present invention.

FIG. 16 is a flowchart showing the REC processing (second embodiment) of FIG. 2 in detail.

FIG. 17 is a diagram showing a data format used in FIG. 16;

[Explanation of symbols]

11 Key switch (pitch specifying means) 13 Panel switch 15 Timer 16 CPU (Constituent sound detecting means, chord information generating means, specific sound information generating means, chord / correction information generating means, sound bit string generating means) 17 ROM 18 RAM ( Storage means) 20 disk device (storage means) 21 sound source circuit

Claims (3)

(57) [Claims] 1. A pitch specifying means for specifying a pitch; a specific pitch information generating means for generating specific pitch information including octave identification information based on the pitch information specified by the pitch specifying means; Constituent sound detecting means for detecting a constituent sound of the pitch information specified by the pitch specifying means; key-on detecting means for detecting the presence or absence of the constituent sound detected by the constituent sound detecting means; detection by the constituent sound detecting means Chord information generating means for detecting chords from the constituent sounds thus generated to generate chord information; specific sound information including octave identification information generated by the specific sound information generating means; constituent sounds detected by the key-on detecting means Storage means for storing the presence / absence and the three pieces of chord information generated by the chord information generation means in a time-series manner in association with each other. 2. A pitch detecting means for specifying a pitch, a constituent sound detecting means for detecting a constituent sound of the pitch information specified by the pitch specifying means, and a structure detected by the constituent sound detecting means. A chord / correction information generating means for generating chord information when it is determined that a chord is established by the sound, and generating correction information for the immediately preceding constituent tone information when it is determined that the chord is not established; Storage means for storing the chord information or the correction information generated by the chord / correction information generation means in a time-series manner. 3. The accompaniment information processing apparatus according to claim 2, wherein the correction information generated by said chord / correction information generating means is information relating to a pitch relative to a chord.