JP2820998B2 - Scroll circuit of light emitting element dot matrix display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a cathode ray tube (hereinafter referred to as CR) such as a cathode ray tube controller.
The present invention relates to a scroll circuit of a light-emitting element dot matrix display such as a light-emitting diode (hereinafter, referred to as an LED) using a timing controller for a light-emitting element (hereinafter referred to as T), and more particularly to a scroll circuit capable of performing a smooth scroll display for each light-emitting element dot.

(Prior art)

The display screen is constructed by combining multiple units of the vertical and horizontal LED dot matrix display.
The timing for transmitting data to the LED display screen is very similar to the data transmission timing when using a CRT display. Therefore, even a general-purpose CRT controller developed for CRT can display an LED dot matrix display screen.

The CRT controller controls the display of the CRT display. This CRT controller can generate various timing signals necessary for CRT display according to the values set by the central processing unit. In addition, the function of operating the display on the CRT display is also possible by setting, and it has a wide responsiveness according to the performance of various CRTs and CRTs having different screen sizes.

FIG. 11 is a block diagram showing an example of a conventional circuit for displaying data on a CRT using a CRT controller. This conventional circuit has a central processing unit (CPU) 12 for outputting an address bus 18 and each address A to the data bus 19 ₀ to A ₁₅ and data D ₀ to D _7, the addresses A ₀ to A _15, data D ₀ ~ D
₇ and CRT controller 7 for outputting a memory address MA ₀ to MA ₁₃ and the read address RA ₀ to RA ₄ receives the output of the dot counter 11, switches the address A ₀ to A ₁₅ by the memory address MA ₀ to MA ₁₃ a multiplexer 13 for outputting a display RAM15 for storing image data to be displayed on the inputs the output of the multiplexer 13 CRT 8, the character for generating a character for displaying the output of this display RAM15 by the read memory RA ₀ to RA ₄ a generator 23, a parallel converts the output of the transmission frequency divider parallel data such as characters (22) into serial data to be displayed - serial converter 16, a bus driver 14 to switch the signal direction of the data D ₀ to D ₇ , A transmission frequency divider 22 for dividing the output of the oscillator 20, a CRT controller frequency divider 11, and a CRT 8 for displaying serial data.

Addresses A _{0 to} A ₁₅ are generated by the central processing unit 12, and the generated addresses A _{0 to} A ₁₅ select the display RAM 15 via the multiplexer 13. The data D _{0 to} D ₇ to be displayed from the data bus 19 via the bus driver 14 are stored in the selected display RAM 15. Displayed RAM 15
, The address of the character generator 23 is selected, the data is output in parallel, converted into serial data by the parallel-serial converter 16, and then serial data such as characters is displayed on the CRT 8.

FIG. 12 is a block diagram of FIG. 11 from which the character generator 23 and the bus driver 14 are omitted.

The CRT controller 7 has a display RAM 15 shown in FIGS.
Can be displayed on the CRT8 screen. In addition, by rewriting the address of the display data in the display RAM 15 by the CRT controller 7, the vertical and horizontal (up, down, left, and right) jump scroll can be temporarily performed.

The CRT controller 7 has a function of performing vertical (up / down) smooth scrolling only by writing a value. However, a function for performing horizontal (left / right) smooth scroll display is not generally provided. As shown in FIG. 13, when the LED display device 24 is driven by using the CRT controller 7, a normal C
By adding and connecting a simple interface, that is, an 8 × dot counter 22 and an LED control unit 25 to the timing of the RT controller 7, the above-described scroll function can be used and operated similarly to the CRT 8.

In order to perform smooth scrolling display using the CRT controller 7 on the LED display device 24, since the CRT controller 7 has only the vertical smooth scrolling function, use this function directly to perform vertical smooth scrolling display, or conversely, use the LED panel. The scanning direction was rotated 90 ° horizontally, and a smooth horizontal scrolling display was performed by the linked configuration.

Until now, it has been a method of performing one of vertical and horizontal (up, down, left and right) smooth scroll displays instead of smooth scroll display of up and down or left and right. There is also a method of designing and displaying a discrete circuit having a scroll function independently without using the CRT controller 7 at all.

[Problems to be solved by the invention]

Originally, the display performed by the CRT is mainly in a fixed display area. If it is necessary to move the fixed display area, one of the functions of the CRT controller 7 is provided, such as a vertical scroll function or a character unit. It uses the horizontal jump scroll function.

Due to the nature of this display, LED dot matrix displays must always perform smooth scrolling up, down, left, and right.

In order to realize the smooth scrolling in the vertical and horizontal directions, the CRT controller 7 has only the function of the vertical scrolling, so that the horizontal smooth scrolling cannot be realized. The challenge is that you have to design and implement a controller, or take a very time-consuming method of creating several screens in which characters are moved little by little like a movie or animation and switching between them in order. there were.

An object of the present invention is to provide a scroll circuit that enables smooth vertical, horizontal, and vertical scrolling of a light emitting element dot matrix display by adding an extremely simple circuit in addition to the vertical scroll function originally provided by a CRT controller. Is what you do.

[Means for solving the problem]

In order to solve the above-mentioned problems and achieve the above object, the circuit of the present invention includes a register 1 for taking in data DA up to N digits in synchronization with a clock CL as shown in FIGS. , A latch circuit 2 for latching the data of the register 1 with a latch signal LA, a first driver circuit 3 for inputting the data latched in the latch circuit 2, and the values of the common driver addresses A, B,. A second driver circuit 4, a light-emitting element dot matrix 6 that emits light from the light-emitting element 5 by the outputs of the driver circuits 3, 4 and the enable signal ▲ to display data DA, and an initial value set by an input. And a first counter 9 which starts counting upon input of a display period signal DPG output from the CRT controller 7 and counts up to the display period, an end value set by the input, and the first counter. It starts counting the clock CL number by an input from the 9, and become more configuration and a second counter 10 for outputting a latch signal LA at terminal count.

(Operation)

The data DA is input to the register 1 in synchronization with the clock CL and is taken up to N digits. The first counter 9 to which the initial value is set starts counting the number of clocks CL in response to the input of the display period signal DPG output from the CRT controller 7, performs counting until the display period, and then sets the end dot number. The second counter 10 counts the number of clocks CL. Each time the second counter 10 counts, it counts the number of remaining clocks by taking in the clock CL and counts.
Is output.

In other words, the total number of displayed characters is counted by the two counters 9 and 10, and the latch signal LA is generated every N digits. The data of the register 1 is latched by the latch circuit 2 with a latch signal LA generated every N digits, and the latched data becomes input data of the segment driver 3.

On the other hand, the second driver circuit 4 is selected by the values of the common driver addresses A, B,..., And the input data DA of the segment driver 3 emits the light emitting elements 5 of the light emitting element dot matrix 6 by inputting the enable signal ▲ ▼. , Will be displayed.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1A is an internal block diagram showing an example of a light emitting element dot matrix display to which the circuit of the present invention is applied, and FIG. 1B is a diagram showing a light emitting element dot matrix 1 shown in FIG. 1A. FIG. 2 is a block diagram showing the configuration of a horizontal smooth scroll circuit in a first embodiment of the circuit of the present invention which can be applied to the matrix display of FIG. 1 (a). FIG. 3 is a block diagram of a circuit that enables smooth scrolling (left and right).

The matrix display shown in FIG. 1 is an LED dot matrix display using a 16 × 16 bit LED dot matrix 6. This LED dot matrix display has a 16-bit shift register 1 for taking in data N up to N digits in synchronization with a clock CL, and a latch circuit 2 for latching data in the shift register 1 with a latch signal LA generated every N digits. A segment driver 3 for inputting data latched in the latch circuit 2, a common driver 4 selected through the 4to16 decoder 17 based on the values of the common driver addresses A to D, and an output of these drivers 3 and 4 being enabled. The LED 5 is turned on by the input of the signal ▲ ▼, and comprises a 16 × 16 dot LED dot matrix 6 for displaying the data DA.

In the first embodiment, in such an LED dot matrix display, the initial value is set to 1 based on the total display dot number M.
The fixed number dot number counter 9 starts counting the number of clocks CL by the input of the signal DPG indicating the display period output from the CRT controller 7 and counts up to the display period. For example, a variable dot number counter 10 that sets 0 to 7 and starts counting the number of clocks CL with the output of the fixed dot number counter 9 and outputs a latch signal LA at the end of counting is provided.

FIG. 3 is a time chart of each input signal to the LED dot matrix display, and FIG. 4 is a time chart for explaining the operation of the circuit of FIG.

The operation of the first embodiment will be described with reference to these drawings.

The data DA is synchronized with the clock CL as shown in FIG.
The data is input to the bit shift register 1 and fetched up to N digits. The fixed number dot number counter 9 in which a value M-1 obtained by subtracting 1 from the total display dot number M is set as an initial value is a CRT.
When the display period signal DPG output from the controller 7 is input, the counting of the number of clocks CL is started, and the counting is performed until the display period, that is, up to M-1 (see FIG. 4). The number of clocks CL is counted by the number counter 10 (see FIG. 4). Each time the variable-number dot counter 10 counts, it counts the number of remaining clocks by taking in the clock CL and outputs a latch signal LA at the end of counting (see FIGS. 3 and 4).

In this case, the CRT controller 7 is initialized so as to display one character more than the total display dot number M (fourth display).
See figure).

For example, if 0 is set in the variable dot number counter 10, the counting by the variable dot number counter 10 ends when the total display dot number M is counted, and if 5 is set, the count is counted to M + 5. The processing is terminated at the point when it is performed (see FIG. 4). From the first transmitted data to the fourth transmitted data are discarded from the shift register 1, and as a result, the data is correctly displayed from the fifth dot from the first.

In other words, the total number of display characters is counted by the two counters 9 and 10, and the latch signal LA is generated every N digits (for each raster) (see FIG. 3). The data of the shift register 1 is latched by the latch circuit 2 with a latch signal LA generated every N digits, and the latched data becomes the input data of the segment driver 3.

On the other hand, the values of the common driver addresses A to D are
The common driver 4 of the LED 5 to be turned on is selected, and the input data DA of the segment driver 3 is supplied to the decoder 17 by the enable signal ▲ ▼
With this input, the LED 5 of the LED dot matrix 6 is turned on and displayed. Normally this cycle (for each raster)
Switching faster than the afterimage characteristics of the human eye
LED5 appears to be lit.

FIG. 5 is a block diagram showing the configuration of a second embodiment of the circuit of the present invention, in which the LED matrix 6 is arranged in one row and a plurality of units are connected. The configuration of monochromatic light emission on a display screen with one horizontal row is a basic screen configuration, and FIG. 5 is an example of a basic scroll circuit having a horizontal smooth scroll circuit.

This second embodiment is a central processing unit 1 outputs the respective addresses A ₀ to A ₁₅ and data D ₀ to D ₇ to the address bus 18 and data bus 19 in the LED dot matrix display of FIG. 1, the fixed cycle pulse Generating an oscillator 20
And the clock to which the output of this oscillator 20 is input and transmitted
A transmission frequency divider 22 that outputs CL, a CRT controller frequency divider 11 that receives the output of the transmission frequency divider 22 and outputs a frequency-divided clock, and an address that is output from the central processing unit 1.
Memory address MA to input A ₁₀ to A ₁₅ and the data D ₀ to D ₇
A CRT controller 7 that outputs _{0 to} MA ₁₃ and a display period signal DPG and a display period signal DPG output from the CRT controller 7 by setting a value M−1 obtained by subtracting 1 from the total display dot number M as an initial value A fixed dot number counter 9 for starting a counter of the number of clock CL and counting until a display period;
The variable dot number counter 10 which sets the end dot number, starts counting the number of clocks CL with the output of the fixed number dot counter 9 and outputs a lag signal LA at the end of the count, and the address A ₀ output from the central processing unit 12 a multiplexer 13 for outputting a memory address MA ₀ to MA ₁₃ for outputting to a ₁₅ from the CRT controller 7, is selected by the address a ₀ to a ₁₅ to output from the multiplexer 13, the central processing unit to the selected address 12 Output data D ₀
Display RA that stores D ₇ in parallel via bus driver 14
M15 and the parallel data stored in the display RAM 15 are input and the serial data DA is synchronized with the output of the transmission frequency divider 22.
And a parallel-serial converter 16 for outputting the same.

Reference numeral 21 denotes a horizontal smooth scroll circuit including a fixed number dot number counter 9 and a variable number dot number counter 10.

FIG. 6 is a diagram showing the relationship between the clock transmitted to the LED dot matrix display in the second embodiment and the clock used for the fluctuating operation timing of the parallel-serial converter, and the clock output from the transmission frequency divider 22. CL
And the clock C output from the CRT controller frequency divider 11
This shows the relationship with LK.

FIG. 7 shows a clock used for the timing of the conversion operation of the parallel-serial converter in the second embodiment.
FIG. 4 is a diagram showing a relationship between a display period signal output from the CRT controller and a clock CLK output from the CRT controller frequency divider 11 and a display period signal DPG output from the CRT controller 7; Divider
Numeral 11 outputs one clock CLK for one character.

 The operation of the second embodiment will be described with reference to these drawings.

The operation of the parts described in the first embodiment is omitted. Occurred address A ₀ to A ₁₅ from the central processing unit 1, select the address of the display RAM15 through the multiplexer 13 by the memory address MA ₀ to MA ₁₃ addresses A ₀ to A ₁₅ that this occurs is to be output from the CRT controller 7 I do. The data to be displayed from the data bus 19 via the bus driver 14
D _{0 to} D ₇ are stored in parallel at the address of the selected display RAM 15. The data in the display RAM 15 stored in parallel is converted into serial data by the clock CL output from the transmission frequency divider 22 and output.

On the other hand, as described in the first embodiment, the horizontal smooth scroll circuit 2 of the display period signal DPG of the CRT controller 7 is used.
The input to 1 causes the latch signal LA to be output. These clock CL, data DA and latch signal L
A is an input to the shift register 1 and the latch circuit 2 of the LED dot matrix display shown in FIG. 1A, and data is displayed.

FIGS. 8A to 8I are explanatory diagrams of the principle of the horizontal smooth scroll circuit in the second embodiment.

FIG. 8A shows an example of data written in the display RAM 15 in advance. FIG. 8 (b) shows the display from the head (first dot) of the data stored in the display RAM 15 using two units of the LED dot matrix display.
FIG. 8 (c) shows the display from the second dot of the display RAM, and FIG. 8 (d) shows the display from the third dot of the display RAM. Hereinafter, if the display is performed as shown in FIGS. 8 (e) to 8 (i), it can be seen that the display has been horizontally scrolled smoothly. FIG. 8 (i) sets the display address of the CRT controller 7 to "B" which is the second character, and FIG.
It can be seen that a series of smooth scrolling of (i) is performed and any character is possible.

FIG. 9 is a block diagram showing the configuration of a third embodiment of the circuit according to the present invention.
5, two sets of the parallel-serial converter 16 and the bus driver 14 are provided, respectively, and one set of the multiplexer 13a and the display RA
M15a, parallel-serial converter 16a and bus driver 14
a is a parallel-serial converter 1 for emitting red light, for example.
The corresponding red data RDA is output from 6a, and the other set of multiplexers 13b, display RAM 15b, parallel-serial converter 16b
In addition, the parallel-serial converter 16b outputs the green data GDA by using the bus driver 14b for emitting green light, for example.

The third embodiment is an example in which the LED dot matrix display emits two colors. In terms of color, the mainstream is that red and green LED chips make up one dot and display yellow by two-color lighting. Display RAM 15a, 1 for each of red and green
Using 5b, the same operation as in FIG. 13 is performed, and multicolor display is performed.

FIG. 10 is a block diagram showing the configuration of a fourth embodiment of the circuit according to the present invention. This fourth embodiment comprises a CRT controller 7, a fixed number of dots counter 9, a variable number of dots counter 10, a multiplexer 13, a display RAM 15, Two sets of the parallel-serial converter 16 and the bus driver 14 are provided. One set of the CRT controller 7a, the fixed number of dots counter 9a, the variable number of dots counter 10a, the multiplexer 13a, the display RAM 15a, and the parallel-serial converter 16a and it outputs the latch signal LA ₁ of the first row from the variable number dot counter 10a for the first line of the bus driver 14a, parallel - 1 from the serial converter 16a
In addition to outputting the data DA ₁ of the row, the other set of CRT controller 7b, fixed number of dots counter 9b, variable number of dots counter 9b, variable number of dots counter 10b, multiplexer 13b, display RAM 15b, parallel-serial conversion vessels 16b and outputs a bus driver 14b of the second line of the latch signal LA ₂ from variable number dot counter 10b for the second line, parallel -
And it has a configuration of outputting the data DA ₁ of the first row from the serial converter 16b.

The fourth embodiment is an example in which the LED dot matrix display extends over two rows. One CRT controller 7 per row, horizontal smooth scroll circuit, 2 CR
In synchronization with one of the T controllers, display operations can be performed independently on one line or simultaneously on two lines.

〔The invention's effect〕

As apparent from the above description, according to the present invention, the CRT
In addition to the vertical (up / down) smooth scroll function originally possessed by the controller 7, a horizontal (left / right) smooth scroll circuit 21 comprising an extremely simple fixed number of dots counter 9 and a variable number of dots counter 10 is provided to provide vertical and horizontal scrolling. The horizontal smooth scroll display can be performed by a light emitting element dot display such as an LED.

[Brief description of the drawings]

FIG. 1A is an internal block diagram showing an example of a light emitting element dot matrix display to which the circuit of the present invention is applied;
FIG. 1B is a detailed connection diagram of one raster constituting the light emitting element dot matrix in FIG. 1A, and FIG.
FIG. 3A is a block diagram showing the configuration of a horizontal smooth scroll circuit in a first embodiment of the circuit of the present invention applicable to the matrix display of FIG. 3A; FIG. 3 is a time chart of each input signal to the LED dot matrix display; FIG. 5 is a time chart for explaining the operation of the circuit of FIG. 2, FIG. 5 is a block diagram showing the configuration of a second embodiment of the circuit of the present invention, and FIG.
The figure shows the relationship between the clock transmitted to the LED dot matrix display in the second embodiment and the clock used for the conversion operation timing of the parallel-serial converter, and FIG. 7 shows the parallel-serial in the second embodiment. FIGS. 8A to 8I show the relationship between the clock used for the conversion operation timing of the converter and the display period signal output from the CRT controller. FIGS. 8A to 8I illustrate the principle of the horizontal smooth scroll circuit in the second embodiment. FIG. 9 is a block diagram showing the configuration of a third embodiment of the circuit of the present invention. FIG. 10 is a block diagram showing the configuration of a fourth embodiment of the circuit of the present invention.
11 is a block diagram showing an example of a conventional circuit for displaying data on a CRT using a CRT controller, FIG. 12 is a block diagram showing another example of a conventional circuit in which the character generator and the bus driver of FIG. 11 are omitted, FIG. 13 is a block diagram of still another example of a conventional circuit for displaying data on an LED display device using a CRT controller. 1 (16-bit) shift register, 2 ... latch circuit, 3 ... segment driver, 4 ... common driver, 5 ... light emitting element (light emitting diode or LED), 6 ...
… Light emitting element (LED) dot matrix, 7,7a, 7b …… CRT
(Cathode ray tube) controller, 9,9a, 9b …… fixed number dot number counter, 10,10a, 10b …… variable number dot number counter,
11: Divider for CRT controller, 12: (Central) processing unit (CPU), 13, 13a, 13b: Multiplexer, 14, 14a,
14b: Bus driver, 15, 15a, 15b: Display RAM, 16, 16
a, 16b ...... parallel - serial converter, CL ...... _{clock, DA, DA 1, DA 2} ...... ( serial) _{data, LA, LA 1, LA 2} ...
… Latch signal, A, B …… Common driver address, ▲
▼: Enable signal, M: Total number of display dots, DP
G: display period signal, A ₀ , A ₁ … address, D ₀ , D ₁ … data, RDA… color (red) data, GDA… other color (green)
Data, MA _{1 to} MA ₁₃ … memory address, 21… horizontal smooth scroll circuit, 22… frequency divider for transmission.

Claims (5)

(57) [Claims] A register for fetching data up to N digits in synchronization with a clock; a latch circuit for latching the data of the register by a latch signal generated every N digits; and a latch circuit for inputting the latched data to the latch circuit. , A second driver circuit selected by the value of the common driver address (A, B...), And the light emitting element emits light by the outputs of these driver circuits and the enable signal to display data. A first counter that starts counting by inputting a display period signal output from the CRT controller and counts up to the display period, and an end value set by the input. And a second counter which starts counting the number of clocks by an input from the first counter and outputs a latch signal when the counting is completed. Become more light-emitting element dot matrix scrolling circuitry of the display. 2. The scroll circuit according to claim 1, wherein the initial value set by the input is a value M-1 obtained by subtracting 1 from the total number M of display dots. 3. A transmission frequency divider (22) for outputting a clock (CL), an address (A ₀ , A ₁ ...) And data (D ₀ , D ₁ ...).
…) And a processing device (12) for outputting the processing device (12)
A multiplexer (13) for outputting from the address (A _0, A ₁ ......) memory address output from the CRT controller _{(7) (MA 0, MA} 1 ......) to more output, outputs from the multiplexer (13) The data (D ₀ , D ₁ ...) Output from the processing device (12) are stored in parallel with the selected address by the address (A ₀ , A ₁ ...) Via the bus driver (14). Display RAM (15) and this display R
A parallel-serial converter (16) for inputting parallel data stored in the AM (15) in synchronization with an output of the transmission frequency divider (22) and outputting serial data (DA). 2. A scroll circuit of the light emitting element dot matrix display according to claim 1. 4. A multiplexer (13), a display RAM (15),
Parallel-serial converter (16) and bus driver (1
4) are provided in two sets, and one set of multiplexers (1
3a), display RAM (15a), parallel-serial converter (16
a) and the bus driver (14a) output one color data from the parallel-serial converter (16a) for one color emission, and the other set of multiplexers (13b) and display RAM (15a).
4. The light-emitting device according to claim 3, wherein the parallel-serial converter (16b) and the bus driver (14b) are configured to output the other color data from the parallel-serial converter (16b) for the other color light emission. Scroll circuit for element dot matrix display. 5. A CRT controller (7), a fixed dot number counter (9), a variable dot number counter (10), a multiplexer (13), a display RAM (15), a parallel-serial converter (16), and a bus. Two sets of drivers (14) are provided. One set of CRT controller (7a), fixed number dot number counter (9a), and variable number dot counter (10
a), a multiplexer (13a), a display RAM (15a), a parallel-serial converter (16a), and a bus driver (14a) for the first row, and 1
The latch signal (LA ₁ ) of the row is output, the data (DA ₁ ) of the first row is output from the parallel-serial converter (16a), and the other set of CRT controllers (17b) and the fixed number of dots are output. Counter (9b), variable dot number counter (10
a), a multiplexer (13b), a display RAM (15b), a parallel-serial converter (16b), and a bus driver (14b) for the second row, from the variable dot number counter (10b).
4. The light emitting element dot matrix display according to claim 3, wherein a latch signal (LA ₂ ) of the row is output, and data (DA ₂ ) of the second row is output from the parallel-serial converter (16b). Scroll circuit.