JP2812246B2 - Digital signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for synthesizing a digital sound waveform signal corresponding to a musical sound or other audible sound and / or for giving various musical sound effects or sound effects to the digital sound waveform signal. The present invention relates to a digital signal processing device.

[0002]

2. Description of the Related Art In recent years, with the progress of digital signal processing technology and integrated circuit technology, predetermined signal arithmetic processing for synthesizing digital musical tone waveform signals and imparting a tone effect or acoustic effect to the musical tone waveform signals has been performed. Dedicated LSI (Large Scale Integrated Circuit) executed by microprogram method
The electronic musical instruments, tone generators, and other musical or sound signal processing devices are also equipped with such devices and used. This type of signal processing device is generally called a digital signal processor (abbreviated as DSP). For example, when a digital musical tone waveform signal is synthesized by adopting the DSP in an electronic musical instrument, in a conventional electronic musical instrument, a specific waveform synthesizing method (for example, a formant sound synthesizing method or FM (frequency modulation)) is used.
A single DSP having a circuit configuration for performing all of a series of arithmetic processing in the synthesis method), and a microprogram describing the series of arithmetic processing is converted to the DSP.
Was stored and executed.

[0003]

SUMMARY OF THE INVENTION Such a conventional DS
In P, a series of arithmetic processing for tone waveform synthesis and processing must be all executed by the single DSP. For this reason, as the number of operation cycles increases, higher-speed processing is required as the number of operation cycles increases in accordance with the sophistication of operation contents, multi-functions, and multi-channel sound sources in today's electronic musical instruments. However, there is a limit to high-speed processing, and it is becoming difficult to satisfy such requirements. Further, when a tone synthesis system is configured by mixing a plurality of types of tone synthesis methods (for example, when an FM synthesized sound and a noise formant sound are generated simultaneously, or when a normal formant synthesized sound and a noise formant sound are simultaneously generated). In such a case, each of the individual tone synthesis methods must be configured to execute the above-described series of independent arithmetic processing, so that the system configuration is inevitably increased in size, and an efficient system is required. It was difficult to configure. Furthermore, 1
Even if the system has only one musical tone synthesis system and the contents of some of the arithmetic processing are to be changed, the entire DSP configuration must be redesigned in accordance with such a change. Is bad. Therefore, the conventional DSP system cannot efficiently respond to a request to change the contents of arithmetic processing for musical tone waveform synthesis or processing. It has also been difficult to efficiently configure a multifunctional tone synthesis DSP system that mixes different types of tone synthesis methods.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to provide an efficient digital signal processing device having high speed of operation, versatility of the device, ease of design / manufacture, and economy. It is assumed that. It is another object of the present invention to provide an efficient sound signal synthesizing device using such a digital signal processing device as a base. It is another object of the present invention to provide an efficient sound signal synthesizing apparatus which enables various sound synthesizing with a simple configuration and easy control.

[0005]

According to a first aspect of the present invention, there is provided a digital signal processing apparatus comprising: a parameter supply unit for supplying a plurality of parameters required for a target sound signal processing; Signal processing means, each one of these digital signal processing means inputs parameters required for arithmetic processing, and performs predetermined arithmetic processing on digital input data in accordance with the input parameters and a set program. The digital signal processing means includes a plurality of digital signal processing means, and a first bus commonly connected to each of the digital signal processing means, and is supplied from the parameter supply means. Distributes and inputs each of the plurality of parameters to predetermined digital signal processing means via the first bus. Parameter input means, and data transmission means including a second bus commonly connected to each of the digital signal processing means, and transmitting output data of each of the digital signal processing means via the second bus. Yes,
The at least one predetermined digital signal processing means captures output data from the other digital signal processing means via the second bus, and performs the predetermined arithmetic processing using the captured data as input data. ,
Thus, the target sound signal processing is performed by a combination of the arithmetic processing by the plurality of digital signal processing means, and the processed sound signal is converted into a predetermined digital signal of the plurality of digital signal processing means. The data is supplied to the second bus as output data of the processing means.

A sound signal synthesizing apparatus according to a second aspect of the present invention is a sound signal synthesizing apparatus for synthesizing sound signals on a plurality of channels, wherein a series of signal processing for sound signal synthesis is divided into a plurality of signal processing parts. A plurality of arithmetic processing means for respectively executing arithmetic processing corresponding to each one of the signal processing portions, the arithmetic processing means being provided in parallel, Each of the arithmetic processing means executes arithmetic processing for each channel in a time-division processing timing unique to each arithmetic processing means in a time-division manner. Output the result,
The plurality of arithmetic processing units and at least one of the arithmetic processing units are connected in common, wherein at least one of the arithmetic processing units performs the arithmetic processing using an arithmetic processing result of another arithmetic processing unit. A data transmission means for providing the arithmetic processing result of each arithmetic processing means to another arithmetic processing means or a sound signal output port via the bus; and a sound signal for each channel for each arithmetic processing means. Parameter supply means for supplying parameters necessary for synthesis.

A digital signal processing apparatus according to a third aspect of the present invention comprises a parameter supply unit for supplying a plurality of parameters necessary for a target sound signal processing, and a plurality of independent digital signal processing units. ,
An arithmetic processing unit for each one of these digital signal processing means for inputting parameters required for arithmetic processing and performing predetermined arithmetic processing on digital input data according to the input parameters and a set program; The plurality of digital signal processing means, including a dual port memory having a write port and a read port for storing processing result data output from the arithmetic processing unit, and a common memory for each of the digital signal processing means. A parameter input means including a first bus connected thereto, for distributing and inputting each of the plurality of parameters supplied from the parameter supply means to predetermined digital signal processing means via the first bus; And a second bus commonly connected to each of the digital signal processing means. Data transmission means for transmitting output data read from the read port of the dual port memory of each of the digital signal processing means, wherein at least one of the predetermined digital signal processing means is provided with another of the digital signal processing means. And the predetermined arithmetic processing is performed using the captured data as input data, and the processing result data is transferred to the other through the dual port memory. By using the digital signal processing means, the digital signal processing means can operate at independent timing.

A sound signal synthesizing apparatus according to a fourth aspect of the present invention is a sound signal synthesizing means for individually generating sound signals in a plurality of channels based on parameters given independently of each other; Parameter supply means for supplying at least the parameters including at least the sounding designation information and the synchronous sounding designation data for designating whether or not synchronous sounding with another channel is to be performed, and is supplied corresponding to each of the channels. Control means for controlling the sound signal generating means so as to generate a sound in synchronization with sound generation of a predetermined other channel in a channel for which synchronous sounding is specified based on the synchronous sounding specifying data. Things. In the present invention, the sound signal or the sound waveform signal is not only a musical sound signal such as a musical sound signal or a musical sound waveform signal, but also an audible acoustic sound signal such as a human voice or an artificial sound. Alternatively, it has a broad meaning including all sound waveform signals.
Thus, the invention is applicable to any sound signal synthesis and / or processing.

[0009]

According to the digital signal processor of the present invention according to the first aspect, parameters required for arithmetic processing are input, and a predetermined value is applied to digital input data in accordance with the input parameters and a set program. A plurality of digital signal processing means configured to perform arithmetic processing and output the processed data are provided. Each digital signal processing means is commonly connected by a first bus and a second bus, and parameters required for respective arithmetic processing are distributed via the first bus.
The output data, which is the result of each operation, is transmitted to the second bus and can be used mutually via the second bus. That is, the at least one predetermined digital signal processing means captures output data from another digital signal processing means via the second bus, and uses the captured data as input data to perform the predetermined arithmetic processing. Can be applied. This makes it possible to perform a desired series of sound signal processing by a combination of arithmetic processing by each of the plurality of digital signal processing means. The data is supplied to the second bus as output data of a predetermined digital signal processing means.

As described above, a series of target sound signal processing is performed by combining the arithmetic processing by the plurality of digital signal processing means (in other words, a series of target arithmetic processing for the target digital sound signal processing). The processing is divided into a plurality of arithmetic processing portions corresponding to the respective digital signal processing means, and the respective arithmetic processing portions are executed in parallel in the respective digital signal processing means.) Even if the number of processing steps is large and the sound signal to be processed is a multi-channel sound signal, the overall arithmetic processing can be speeded up. In addition, since each digital signal processing means is configured to execute only a part of the arithmetic processing part of a series of objective arithmetic processing, the content of the arithmetic processing to be performed is relatively simplified. It will be. Further, the relative simplification of the content of the arithmetic processing to be executed by each digital signal processing means not only simplifies the circuit configuration of each digital signal processing means but also makes them similar to each other. Therefore, the design and manufacture of each digital signal processing means can be facilitated and the cost can be reduced, and the versatility of the device can be improved.

Further, a plurality of digital signal processing means are
Since the configuration is such that the first bus and the second bus are commonly connected to each other, when increasing the number of the digital signal processing means, routing of input parameter wiring and routing of output data interconnection wiring are performed. No need to
The number of the digital signal processing means can be increased or decreased very easily since it is only necessary to connect to each bus. Therefore, also in this respect, the versatility of the device can be improved and efficient use can be achieved. Further, when a tone synthesis system is configured by mixing a plurality of types of tone synthesis methods (for example, when an FM synthesized sound and a noise formant sound are generated simultaneously, or when a normal formant synthesized sound and a noise formant sound are simultaneously generated). In such a case, a common digital signal processing means can be used for an operation processing portion that can be processed by a common operation algorithm even in the case of different tone synthesis methods. There is no need to make a redundant configuration so that a series of independent arithmetic processes are executed for each method. Therefore, an efficient system can be configured. For example, according to the present invention, the arithmetic processing portion for generating a sound waveform is performed using digital signal processing means different for each musical tone synthesis method, but the arithmetic processing portion for generating envelope signal data is used for each musical tone synthesis method. The system can be efficiently constructed so as to use one common digital signal processing means.

Even when the contents of a part of the arithmetic processing corresponding to one musical tone synthesizing method are changed in the series of arithmetic processing, only the digital signal processing means corresponding to the arithmetic processing part to be changed has its program Alternatively, since the circuit configuration may be changed, the design can be changed efficiently and at low cost. Therefore, according to the present invention, it is possible to efficiently respond to a request to change the content of arithmetic processing for sound waveform synthesis or processing. A multi-function digital signal processing system for synthesizing or processing a musical tone by mixing musical tone synthesizing methods can be efficiently constructed.

The sound signal synthesizing device and the digital signal processing device according to the second and third aspects have the same features, functions and effects as described above. That is, also in the sound signal synthesizing device according to the second aspect, a plurality of arithmetic processing units are provided in a similar manner to the plurality of digital signal processing units. Arithmetic processing corresponding to each one of the signal processing portions obtained by dividing the series of signal processing into a plurality of signal processing portions is simultaneously performed in parallel. The sound signal synthesizing device according to the second aspect is particularly characterized in that, when synthesizing a sound signal in a time-division manner on a plurality of channels, each of the plurality of arithmetic processing means performs individual arithmetic processing. The point is that arithmetic processing for each channel is executed in a time-division manner at a time-division processing timing unique to the means. Thus, for example, the timing can be adjusted so that the channel time division processing timings in the respective arithmetic processing units are shifted from each other in accordance with the role of the signal processing portion shared by the respective arithmetic processing units. In other words, by appropriately shifting (or not necessarily shifting) each channel time-division processing timing in accordance with the use form of the arithmetic processing result of each arithmetic processing means, a certain arithmetic processing means can be obtained. In the case where the calculation processing result output from is input to another calculation processing unit and used, it can be used appropriately at an efficient timing, and the calculation processing as a whole can be promptly advanced.

The digital signal processing apparatus according to the third aspect is particularly characterized in that each digital signal processing means inputs parameters required for arithmetic processing, and executes the processing in accordance with the input parameters and a set program. By including an arithmetic processing unit for performing predetermined arithmetic processing on digital input data, and a dual-port memory having a write port and a read port for storing processing result data output from the arithmetic processing unit, is there. Thus, writing and reading of the dual port memory can be controlled at independent timings, so that a certain first digital signal processing means can output data from another second digital signal processing means to the second digital signal processing means. In the case of taking in and using via the second bus, the second
When the processing result data of the digital signal processing means is read out and taken in through the dual port memory, the reading is performed by the first digital signal processing means different from the write operation timing of the second digital signal processing means. It can be controlled at a unique timing of the digital signal processing means. Therefore, each digital signal processing means can operate at independent timing.

In the sound signal synthesizing device according to the fourth aspect, synchronous sound designation data for specifying whether or not to perform synchronous sound generation with another channel is given independently for each channel. It is arbitrarily set variably for each channel, so that a plurality of channels can be sounded synchronously controlled in various combinations. At this time, parameters other than the parameters used for the tone synchronization control, for example, tone setting / control parameters, can be arbitrarily set for each channel, so that the sound-synchronized channels have different formant or harmonic components. Can be combined to synthesize one complex tone signal as a whole. Therefore, simply setting the synchronous sounding designation data for each channel arbitrarily and synthesizing a tone signal composed of various formant configurations or combinations of overtone components by synchronizing the sounding of a plurality of channels in various combinations. This can be achieved easily and using a limited musical tone generation channel configuration.

[0016]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of an electronic musical instrument employing a digital signal processing device according to the present invention. The digital signal processing unit DSPS includes four digital signal processors DSP1, DSP2, DSP3,
DSP4 included. DSP1, DSP2, DSP
3. The DSP 4 is connected to the microcomputer COM (including CPU, ROM, RAM) of the electronic musical instrument in parallel via the parameter bus PBUS and the computer interface CIF. From the microcomputer unit COM, various parameter data for setting the pitch, timbre, volume, etc. of the musical tone to be generated based on the operation unit OPS (including the performance operation panel and the panel operation unit) are individually obtained. It is provided corresponding to a digital signal processor (hereinafter simply referred to as DSP). These parameters are based on the computer interface CI
DSP1 through DSPD via F and the parameter bus PBUS
The input is distributed to predetermined ones of SP4. Further, the DSPs 1 to 4 are interconnected via a data bus DBUS, and can exchange data between the DSPs. Each of the DSP1 to DSP4 is connected to a data interface DIF which is an output port via a data bus DBUS, and the digital / analog converter D / D is connected via the data interface DIF.
Connected to AC. The synthesized musical sound waveform signal data, which is the final result of the arithmetic processing, is output from a predetermined DSP (DSP1 in this embodiment), and is sent to the DA converter DAC via the data interface DIF. The output musical sound waveform signal converted into analog signal
It is pronounced via S.

A waveform memory WM storing tone waveform data sampled from the outside by a PCM (pulse code modulation) method is provided to each DSP 1 via a memory interface MIF and a data bus DBUS.
To the DSP4 and the interface MIF
And parameter bus PBUS and interface CI
It is connected to the microcomputer unit COM via F. Note that a system clock pulse is supplied from the clock pulse generator CLKG to each of the DSP1 to DSP4.

In this digital signal processing section DSPS,
Various operations and processes for synthesizing digital musical tone waveforms are classified and assigned to each of the DSP1 to DSP4. For example, the DSP 1 performs an operation (hereinafter, referred to as “phase operation”) for creating progressive phase data of a musical sound waveform for each of a plurality of musical sound generation channels (for example, 18 channels below).
And an operation of summing the tone waveform data of each channel generated by another DSP (for example, DSP4)
"Mixing operation"). The DSP 2 performs an operation for generating various types of envelope data for each channel (hereinafter, referred to as “envelope operation”). The DSP 3 performs an operation (hereinafter, referred to as an operation) for creating a noise signal for each channel to be used for generating a sound waveform.
In addition to performing “noise calculation”, a calculation for reading the PCM waveform (hereinafter, “PCM calculation”) is performed. The DSP 4 performs an operation (hereinafter, referred to as “waveform generation operation”) for generating a tone waveform for each channel using the phase data, the envelope data, and the noise signal created by the DSP1, DSP2, and DSP3.

FIG. 2 functionally shows the flow of information input / output to / from each of the DSPs 1 to 4 in the digital signal processor DSPS. From the microcomputer unit COM, predetermined various parameter data corresponding to each processing content is given to each of the DSP1 to DSP4 via the parameter bus PBUS and the interface CIF. FIG. 19 shows an example of the codes of these parameter data and their contents in a list. The DSP to which each parameter data is given will be described later. The DSP 2 creates various envelope data for each channel based on the parameter data for setting various envelopes from the microcomputer COM, and sends the created envelope data to the DSP 1 and the DSP via the data bus DBUS.
Send to 4. These envelope data are not limited to the amplitude control envelope data EG, but may be pitch control envelope data (for example, attack glide data A).
G) and data whose values gradually change over time, such as coefficient data IP for waveform interpolation.

The DSP 1 has a microcomputer CO
On the basis of the pitch setting and tone color setting parameter data from M and the pitch control envelope data from DSP 2, progressive phase data PG corresponding to the pitch of the generated sound for each channel is created. , To the DSP 4 via the data bus DBUS. The DSP 3 creates a correlation noise signal BWR for each channel based on the tone color setting parameter data from the microcomputer COM, and creates the created signal BW
R is sent to the DSP 4 via the data bus DBUS. When generating the PCM waveform, the DSP 3 stores the waveform memory W
Data is exchanged with M.

The DSP 4 has a microcomputer CO
Parameter data for tone color setting and volume setting from M, and phase data P from DSP1, DSP2 and DSP3
G, envelope data (volume level data LVL in consideration of EG and IP), and a correlated noise signal BWR, generate tone waveform data having a predetermined pitch, tone color, and volume for each channel, and generate the generated tone. The waveform data is sent to the DSP 1 via the data bus DBUS. DS
P1 sums the tone waveform data of each channel from the DSP 4 and transfers the summed tone waveform data to the data bus DB.
DA converter D via US and interface DIF
Send to AC.

[Description of Example of Basic Structure of DSP] Next, FIG. 3 shows an example of the basic structure of the hardware of each of the DSP1, DSP2, DSP3 and DSP4. In the figure, D
SPn corresponds to any one of the individual DSP1 to DSP4. The microprogram supply unit 5 is a storage device that stores a microprogram. The microprogram supply unit 5 of each DSPn (that is, DSP1 to DSP4) includes, among various operations for synthesizing a digital waveform,
Microprograms describing operations assigned to the DSP are stored. For example, the microprogram supply unit 5 of the DSP 1 stores microprograms for the above-mentioned “phase operation” and “mixing operation”. The microprogram supply unit 5 of the DSP 2 includes:
A microprogram for the aforementioned “envelope calculation” is stored. Microprogram supply unit 5 of DSP3
Stores microprograms for the above-described “noise calculation” and “PCM calculation”. The microprogram supply unit 5 of the DSP 4 stores a microprogram for the “waveform generation operation” described above.

In this embodiment, two types of formant sound synthesizing system and FM synthesizing system can be used as a musical tone waveform generating operation without using the external waveform memory WM. Therefore, the microprogram supply unit 5 of the DSP 1 stores two types of microprograms, a microprogram for the formant sound synthesis method and a microprogram for the FM synthesis method. The microprogram supply unit 5 of the DSP 4 also stores the same two types of microprograms. On the other hand, the DSP 2 performing the “envelope calculation” and the DSP 3 performing the “noise calculation” have the same calculation content in both of the two waveform synthesizing methods. A common microprogram is executed even when synthesizing waveforms.

The control signal generator 6 is a control device that extracts and decodes a command word from the microprogram in the microprogram supply unit 5 and generates a control signal based on the command. The control signal generator 6 of each of the DSPs 1 to 4
In response to a key-on signal KON for instructing the start of tone generation among various parameters provided via the bus PBUS, the taking out and decoding of a command word are started. Also, DSP
1, the control signal generator 6 of the DSP 4 is configured to select one of a formant sound synthesizing microprogram and an FM synthesizing microprogram in accordance with a parameter ALG which specifies a tone synthesis algorithm among various parameters provided via the bus PBUS. Is further selected, and control for changing or selecting the content of minor partial processing in the selected microprogram is performed in accordance with the specified tone synthesis algorithm. Various control signals generated from the control signal generator 6 based on the program supplied from the microprogram supply unit 5 in this way are supplied to the arithmetic and storage unit 7.

The operation and storage unit 7 performs various operations such as operation, storage, selection, delay, and data conversion in accordance with various control signals provided from the control signal generation unit 6.
Mainly, data interface IF, arithmetic unit (AL
U) 8, dual-port random access memory RA
Contains Mn. The operation unit 4 is an operation device that executes operations such as four arithmetic operations and logical operations. As described with reference to FIG. 2, various parameter data is given to each of the DSPs 1 to 4 from the microcomputer COM via the bus PBUS. Is given via The operation unit 8 of each of the DSPs 1 to 4 receives such external data in the data interface IF.
Is entered via Further, as shown in FIG. 3, the operation output of the operation unit 8 itself is input to the operation unit 8 again via the data interface IF after being appropriately delayed or stored in the RAMn. DSP1 to DSP
In accordance with a control signal from a control signal generator 6 based on a command of a program in the microprogram supply unit 5, the arithmetic unit 4 executes predetermined arithmetic assigned to the DSP using these data.

The dual-port random access memory RAMn has an input data port and an output data port separately, and is therefore a random access memory capable of simultaneously reading and writing. In the figure, R
AMn indicates that it corresponds to any one of the dual port RAM1, RAM2, RAM3, and RAM4 in each of the individual DSP1 to DSP4. The data stored in the dual port RAMn (that is, the D
The data indicating the calculation result of the calculation unit 8 of the SP) is stored in the RAM.
n and used in its own DSP, or sent to another DSP via bus DBUS, or sent to a DA converter DAC. As described above, data from another DSP is supplied to the DSP 1 and the DSP 4 via the bus DBUS. In FIG. 3, a line LX for taking in data of the bus DBUS is provided in the DSP1 and the DSP4.

FIG. 4 shows a storage map of the dual port RAMn of each DSPn. FIG. 4A is a storage map of the dual port RAM 1 of the DSP 1. The RAM 1 is provided with two channels of pitch phase data PGp1 and PGp2 for formant sound synthesis as phase data indicating the instantaneous phase (progressive phase) of the waveform signal for each of 18 channels. Two-series center frequency phase data PG for sound synthesis
Storage areas for f1 and PGf2 are provided for 18 channels, respectively. Note that the center frequency phase data PGf1,
When the FM synthesis method is selected, the storage area of PGf2 is also used as a storage area of the phase data of the two FM operation operators OP1 and OP2. Furthermore, RAM1
Has 18 channels of storage areas for two-series window function phase data PGw1 and PGw2 for formant sound synthesis, respectively.
Are provided for 18 channels, and storage areas for storing left and right musical sound waveform mixed data MIXL and MIXR, respectively, obtained by summing the musical sound waveform data of each channel corresponding to the left and right speakers for panning control, respectively. Is provided.

FIG. 4B is a storage map of the dual port RAM 2 of the DSP 2. The RAM 2 has, as envelope data for pitch control, a storage area for attack glide data AG for normal tone waveform signals (data for controlling temporal fluctuation of pitch at the rise of a tone), and an attack for noise formant sound synthesis. Glide data AG
u storage areas are provided for each of 18 channels. The RAM 2 is provided with a storage area for three channels of envelope data EG for each of 18 channels for controlling amplitude fluctuations, and a storage area for three series of interpolation data IP used as time-varying interpolation coefficients. Are provided for 18 channels, respectively. Further, R
AM2 has two sets of volume level data LVL1 and LV used for formant sound synthesis or FM synthesis.
L2 and a storage area for volume level data LVLu for noise formant sound synthesis are provided for each of 18 channels. Further, a storage area for storing the envelope waveform segment is provided. In addition, among the three series of envelope data EG and interpolation data IP,
The series is data for PCM, and the two series are data for formant sound synthesis or FM synthesis. The volume level data LVL1, LVL2, LVLu are respectively multiplication values of the envelope data EG and the interpolation data IP. The level data LVL1, LVL2 and LVLu are output from the DSP 2 to the DSP 4, but the envelope data EG and the interpolation data IP themselves are not output to the outside but are processed internally.

FIG. 4C shows a storage map of the dual port RAM 3 of the DSP 3. Data B is stored in RAM3.
A storage area for WR (data obtained by adding a DC component to a low-pass noise signal and then limiting the bandwidth thereof, also referred to as a correlation noise signal) is provided for 18 channels, and a storage area for data LPF (low-pass noise signal) is provided. Eighteen channels are provided, and a storage area TmpM used as a working RAM in the middle of calculation is provided for eighteen channels.

FIG. 4D shows a storage map of the dual port RAM 4 of the DSP 4. The RAM 4 has a storage area for the first waveform data TR1 for 18 channels,
A storage area for the second waveform data TR2 is provided for 18 channels, a storage area for the feedback waveform data FR is provided for 18 channels, and a storage area for the noise waveform data TRu is provided for 18 channels. A storage area "Funvoiced" used as a working RAM is provided on the way. The storage area for the waveform data TR1 is a storage area for the first-series tone waveform data during formant sound synthesis, and a storage area for the operator OP1 tone waveform data during FM synthesis. The storage area of the waveform data TR2 is a storage area for addition data of the first series of musical waveform data and the second series of musical waveform data or a storage area for only the second series of musical waveform data at the time of formant sound synthesis. In some cases, a storage area for added data of the tone waveform data of the operator OP1 and the tone waveform data of the operator OP2 or a storage area for only the tone waveform data of the operator OP2. The storage area of the feedback waveform data FR is the self-feedback FM by the operator OP1 in the FM synthesis mode.
This is a storage area for feedback waveform data used for calculation.

[Description of Specific Example of Hardware Configuration of Individual DSP] Next, the operation of the individual DSPs 1 to 4 and the specific hardware configuration of the storage unit 7 will be described. Basic common points of the configuration of the arithmetic and storage unit 7 will be described. As described with reference to FIGS. 2 and 3, the operation and storage unit 7 of each of the DSP1 to DSP4
Are supplied with various parameter data from the microcomputer unit COM, data from other DSPs, and data indicating the operation and the operation result of the storage unit 7 itself. DS
The operation and storage unit 7 of P1 to DSP4 is provided with a selector for inputting data to be operated by the operation unit ALU among these data. A control signal from a control signal generator 6 based on a command of a program in the microprogram supply unit 5 is supplied to a selection control input of the selector. Then, the data selected by the selector according to the control signal is input to the arithmetic unit ALU. Thus, in each of the DSP1 to DSP4, data in accordance with the processing order of the operation assigned to the DSP is sequentially selected by the selector, and the arithmetic unit ALU sequentially executes the operation using the data.

First, an example of a specific hardware configuration of the arithmetic and storage unit 7 of the DSP 1 is shown in FIG. DSP1
Performs “phase operation” and “mixing operation” among various operations for synthesizing a digital waveform, as described above.
The operation and storage unit 7 of the DSP 1 is given predetermined parameter data via a bus PBUS.
Attack glide data AG, AGu for each channel read from the dual port RAM 2 of
Also, a dual port RAM 4 of the DSP 4 described later
, The tone waveform data of each channel read from. The parameter data given from the microcomputer COM to the DSP 1 and their contents are as follows (see FIG. 19).

Parameter FNUM: A parameter for designating a pitch frequency number. Parameter RBP: Flag for simultaneously keying on a plurality of adjacent channels at the same pitch. Parameter FORM: A parameter that specifies the center frequency of the formant sound. Parameter UFORM: unvoiced formant sound (unvoiced
formant: a parameter that specifies the center frequency of the noise formant sound. Parameter VIB: A parameter for specifying on / off of vibrato. Parameter DVB: A parameter that specifies the depth and speed of vibrato. Parameter FOM: A parameter for specifying ON / OFF of modulation of the center frequency of the formant sound. Parameter DFM: A parameter that specifies the depth and speed of modulation of the center frequency of the formant sound. Parameter UFOM: A parameter for specifying ON / OFF of modulation of the center frequency of the unvoiced formant sound. Parameter UDFM: A parameter that specifies the depth and speed of modulation of the center frequency of the unvoiced formant sound. Parameter URVF: Formant follow-up control flag. Parameter PAN: a parameter that specifies panning of a formant sound or FM sound. Parameter BW: A parameter that specifies the bandwidth of the formant sound (= window function time width). Parameter MULT1: A parameter for designating a frequency multiple at the time of formant sound synthesis or a frequency multiple of the operator OP1 at the time of FM synthesis. Parameter MULT2: Operator OP2 at the time of FM synthesis
Parameter to specify the frequency multiple of.

Frequency setting parameters FNUM, FO
RM and UFORM are parameters VIB and DV for modulation.
The signal is modulated by the modulator 12 in accordance with B, FOM, DFM, UFOM, and UDFM, converted into a logarithm by the linear-log converter 13, and then input to the selector 10. Selector 1
0 and 11 are for selecting data to be operated by the arithmetic unit ALU1. The selector 10 also includes output data # RAM4 (especially, tone waveform data of each channel) read from the RAM4 of the digital signal processor DSP4, output data # REG1 of the register REG1 in the DSP1, and a delay circuit from the arithmetic unit ALU1. 18,
19 and data # 1 provided via the output controller 20 are input. One of the input data is the DSP1
Is selected by the selector 10 in accordance with a control signal from the control signal generator 6 based on a program instruction in the microprogram supply unit 5 corresponding to. The selected data is
The signal is input to the “A” input of the arithmetic unit ALU1 via the log-linear converter / shifter 14 and the delay circuit 15.

The selector 11 has output data # RAM2 (particularly, attack glide data AG, A) read from the RAM 2 of another digital signal processor DSP2.
Gu) and the output data # REG1 of the register REG1.
, Output data # RAM1 read from any storage area of the RAM1 of the DSP1, and data indicating "0". One of these input data is selected by the selector 11 according to a control signal from the control signal generator 6 of the DSP 1. The selected data is input to the “B” input of the arithmetic unit ALU1 via the log-linear conversion / shift / ± encoder 16 and the delay circuit 17.

The log-linear converter / shifter 14 performs either log-linear conversion or shift (digit shift) on input data under the control of the controller 23. Log-linear conversion / shift / ±
Under the control of the controller 23, the encoder 16 performs log-linear conversion, shift or inversion of positive / negative signs, or both shift and inversion of positive / negative signs on the input data. Is performed. The pan control parameter PAN is input to the PAN table 21, and based on this, the left and right volume level control data from the PAN table 21 (data for controlling the volume levels output from the left and right speakers of the sound system SS, respectively).
Is output. The left and right volume level control data for panning and the formant bandwidth specification parameter BW
Or frequency multiple specification parameters MULT1, MULT
One of the two data is selected by the selector 22 and input to the controller 23. Controller 23
Controls the log-linear converter / shifter 14 and the log-linear converter / shift / ± encoder 16 according to the data and the control signal from the control signal generator 6 of the DSP 1.

The arithmetic unit ALU1 basically performs an operation of adding data given to the "A" input and the "B" input. The arithmetic output of the arithmetic unit ALU1 passes through the delay circuit 18, the delay circuit 19, and the output controller 20, and is input to the selector 10 as the data # 1 as described above, and also in accordance with the control signal from the control signal generator. , Stored in the register REG1, or written to the RAM1 via the delay circuit 24.

The output controller 20 includes a DSP
1 according to the control signal from the control signal generator 6
It manages an overflow of the operation output of the LU 1 and supplies an initial value for initializing the value of the corresponding phase data in the RAM 1 at the start of sound generation. When the frequency phase data PGp1 and PGp2 overflow, the corresponding series formant center frequency phase data PGf
1, PGf2 and window function phase data PGw1, PGw2
Supplies a predetermined reset value to the controller.

The data stored in the register REG1 is input to the selectors 10, 11 as described above. The data written in the RAM 1 is read out from the RAM 1 in accordance with a control signal from the control signal generator 6 of the DSP 1, and is again input to the selector 11 via the delay circuit 25 as described above. The phase data for each channel written in the RAM 1 is read out from the RAM 1 in accordance with a control signal from the control signal generator 6 of the DSP 4 as necessary, and is calculated and stored in the DSP 4 via the delay circuit 25. It is sent to the unit 7. Further, the total data of the musical tone waveform data of each channel stored in the RAM 1 is passed through the delay circuit 25 and an overflow controller (not shown),
It is sent to the converter DAC (FIG. 1). The overflow controller is a controller that manages an overflow of the total data of the tone waveform data of each channel read from the RAM 1. Each delay circuit 15, 17, 1
8, 19, 24 and 25 delay the input data by a time D corresponding to one clock of the clock signal and output the delayed data.

As described above, the DSP 2 for executing the operation for creating the envelope data executes the well-known operation similar to the existing envelope generator, so that the attack glide data AG and AGu and the level data LVL
1, LVL2, LVLu, etc. are created and sent to the data bus DBUS at the required timing. In this specification, this D
Detailed description of the operation of SP2 and the hardware configuration of the storage unit 7 will be omitted.

Next, an example of the hardware configuration of the arithmetic and storage unit 7 of the DSP 3 is shown in FIG. The DSP 3 includes, via a bus PBUS, parameter data for generating a noise signal, data according to a parameter NBW specifying a noise bandwidth, parameter NRES data specifying a sharpness of a noise spectrum, and a skirt portion of a noise spectrum. Parameter NSKT to specify the spread shape
Is given.

The selector 30 has the parameter NB
W, NRES, operation output data # 3 provided from the arithmetic unit ALU3 via the delay circuit 37, overflow / underflow controller (OF / UF) 38, shifter 39, and white noise generation circuit 32
Is input. One of these input data is DSP3
According to the control signal from the control signal generator 6 of the selector 3, the selector 3
0 is selected. The selected data is input to the A input of the arithmetic unit ALU3 via the delay circuit 33. The selector 31 receives the output data # RAM3 of the RAM3 and the output data # REG3 of the register REG3, and selectively outputs predetermined input data according to a control signal based on a microprogram command. The selected data is
A signal “±” indicating a positive or negative sign is added to the most significant bit, and is input to the B input of the arithmetic unit ALU3 via the gate circuit 34 and the delay circuit 35. Output data of the parallel-to-serial converter 36 is input to a control input of the gate circuit 34. The parallel-to-serial converter 36 converts the output data #AREG of the register AREG to serial and outputs the data. Gate circuit 3
4 and the parallel / serial converter 36 are for calculating a partial product for serial multiplication.

The arithmetic unit ALU3 adds the data input to the A input and the data input to the B input, and outputs the addition result to the data # 3 via the delay circuit 37, the overflow / underflow controller 38, and the shifter 39. Is input to the selector 30 and, in accordance with the control signal from the control signal generator 6, the register REG3 or the AREG
, Or written to the RAM 3 via the delay circuit 40.

The overflow / underflow controller 38 manages an overflow or an underflow of the operation output of the arithmetic unit ALU3, and manages the effective digit of the operation to an arbitrary digit. The shifter 39 performs data shift at the time of serial multiplication or data shift processing according to a predetermined coefficient parameter (for example, a noise spectrum skirt parameter NSKT or an interpolation coefficient parameter IP). Register REG3, Register AR
The EG is a register that can latch input data in accordance with a control signal or pass the data as it is. The register REG3 is assumed to have no time lag between the write timing and the output timing.

The data written in the RAM 3 is a DSP
3 according to a control signal from the control signal generator 6 of the RAM 3.
3 and the data #R via the delay circuit 41
AM3 is input to the selector 31. Also, RAM
The data written in 3 can be read from the RAM 3 according to a control signal from the control signal generator 6 of the DSP 4. In that case, the data is converted into a logarithm by the linear-log converter 42 via the delay circuit 41,
3 is sent to the DSP 4 as data # RAM3L. Each of the delay circuits 33, 35, 37, 40 and 41 delays the input data by a time D corresponding to one clock of the clock signal and outputs the data. The delay circuit 43 delays the input data by a time 3D corresponding to three clocks of the clock signal and outputs the data.

Next, an example of the configuration of the arithmetic and storage unit 7 of the DSP 4 is shown in FIG. The DSP 4 has a parameter RHY (a parameter for designating ON / OFF of the rhythm sound generation mode), a parameter WF1 (a basic waveform of a periodic function at the time of formant sound synthesis, or a basic waveform of the operator OP1 at the time of FM synthesis) via the bus PBUS. Parameter WF2 (operator OP during FM synthesis)
2), parameter FBL (parameter for setting self-feedback level at FM synthesis),
Data of a parameter SKT (parameter for setting the characteristic of the skirt portion of the formant sound) (see FIG. 19) is given.

The selector 50 has the arithmetic output data # 4 supplied from the arithmetic unit ALU4 via the delay circuit 55 and the overflow / underflow controller (OF / UF) 56, and the data # RAM2 ( Level data LVL1 of each channel
LVL2, LVLu) and data # RAM1 (phase data P of each channel) read from RAM1 of DSP1.
Gp1, PGp2, PGf1, PGf2, PGw1, P
Gw2, PGu) through the rhythm sound generator 52 is input. The rhythm sound generator 52 is connected to the bus PBU.
According to the parameter RHY given from S, the input phase data is disturbed to create rhythm sound phase data. One of these input data is selected by the selector 50 in accordance with a control signal from the control signal generator 6 of the DSP 4. The selected data is input to the A input of the arithmetic unit ALU4 via the delay circuit 53.

The selector 51 receives the data # RAM4 read from the RAM 4, the output data # REG4 of the register REG4, and the output data # RAM3L read from the DSP 3. One of these input data is selected by the selector 51 according to a control signal from the control signal generator 6 of the DSP 4. The selected data is sent to the arithmetic unit ALU via the delay circuit 54.
4 is input to the B input. The arithmetic unit ALU4 adds the data input to the A input and the data input to the B input,
The operation output is supplied to a selector 5 as output data # 4 via a delay circuit 55 and an overflow controller 56.
At the same time, it is input to the selector 64 via the following respective paths. In one of the paths, the signal is converted to an exact number by a log-linear converter 58 via a delay circuit 57, and then input to an “α” input of a selector 64 via a delay circuit 59. In another path, the log s passes through the wave shape shifter 60 and the delay circuit 61.
After being converted into logarithmic sine waveform data by the in-table 62, it is input to the “β” input of the selector 64 via the delay circuit 63. In still another path, the output data # 4 is directly input to the “γ” input of the selector 64.

The overflow / underflow controller 56 manages the overflow or underflow of the operation result in the arithmetic unit ALU4 (that is, manages the effective digits of the operation). The wave shape shifter 60 performs a changing process of shifting the phase value or setting the phase value to zero only in a specific section with respect to the input phase data in accordance with the basic waveform selection designation parameters WF1 and WF2 given from the bus PBUS. It is what you do. Such processing includes, for example, Japanese Patent Publication No. 6-44193.
In this publication, the system already disclosed by the present applicant can be basically used. Further, when the formant sound window function waveform is generated, the wave shape shifter 60 shifts the phase value down by one bit with respect to the input phase data (that is, halves the phase value).
Is performed. Thereby, the first half cycle of the log sin waveform is read from the log sin table 62 with respect to one cycle of the pitch cycle of the input phase data by the phase data shifted down to a half rate.

The output of the selector 64 is input to a shift / log-linear converter 65. The shift / log-linear converter 65 performs a shift or log-
The linear conversion or one of the processes is performed according to a control signal. The FM feedback level parameter FBL or the formant sound skirt characteristic specifying parameter SKT is input to the controller 66 via the bus PBUS. The controller 66 gives shift amount designation data to the shift / log-linear converter 65 according to this parameter. Here, the parameter SKT is shifted by 1 bit so that the shift / log-linear converter 65 outputs a waveform of sin (sine wave) raised to the power of “2 × SKT” when a formant sound window function waveform is generated. Up (ie, doubling the value of the data) and input to the controller 66. For example, when SKT = “1”, the input data is shifted up by one bit to convert the logarithmic sine waveform data composed of the first half wave of the sine wave by “2”, thereby converting the sine wave data to an antilog representation. Sometimes, waveform data that becomes a waveform corresponding to the function value of the square of sin is generated, and this can be used as a window function. The waveform corresponding to the function value of the square of sin gives a broader skirt of a half-wave sine wave, and is suitable for a window function.

The output data of the shift / log-linear converter 65 is temporarily stored in the register REG 4 or written into the RAM 4 via the delay circuit 67 in accordance with the control signal from the control signal generator 6. Register REG4
Is a shift register whose output data # REG4
Is input to the selector 51. The data written in the RAM 4 is read out from the RAM 4 according to a control signal from the control signal generator 6 of the DSP 4 and is input to the selector 51 as output data #RAM 4 via the delay circuit 68. The data written in the RAM 4 is DS
RAM according to a control signal from control signal generator 6 of P1
4 and sent to the DSP 1 via the delay circuit 68.

[Explanation of Musical Sound Synthesis Operation in Cooperation of Each DSP] Next, each DSP in the digital signal processing unit DSPS
A description will be given of a process in which a musical sound waveform is synthesized by the DSP 1, DSP 2, DSP 3, and DSP 4 executing operations in parallel based on respective microprograms. FIG.
FIG. 6 is a time chart showing channel timing when each of the DSPs 1 to 4 executes the computation of each channel in parallel. In the figure, reference numerals 1 to 18 indicate time-division calculation timings of the channels 1 to 18, respectively. As shown in the figure, each of the DSPs 1 to 4 executes the operation of each channel while sequentially switching the channel every time when 21 system clock pulses are given.
That is, the system clock pulse is 21 × 18 = 37.
Assuming that the time given for eight clocks is one cycle, 18
Used for time sharing on channels.

Each of the DSPs 1 to 4 executes the operation of each channel at a mutually shifted timing according to the processing contents programmed in each DSP. That is,
As shown in the drawing, the timing at which DSP 2 executes “envelope calculation” for a certain channel (for example, channel 1), the timing at which DSP 1 executes “phase calculation” for that channel 1, and the timing at which DSP 3 executes The timing at which the “Noise operation” of 1 is executed is 2
The timing at which the DSP 4 executes the “waveform generation calculation” of the musical tone waveform data of the channel 1 is further delayed by one channel time (21 clocks). DSP1 performs "mixing operation" for the channel 1
Is further delayed by one channel (21 clocks).

Thus, after the envelope data of a certain channel is created in the DSP 2, the phase data and the noise signal of the channel are converted to D at the timing delayed by two channels by using the envelope data.
It is created in SP1 and DSP3. Next, at the timing further delayed by one channel, the tone waveform data of the corresponding channel is created in the DSP 4 by using the envelope data, the phase data, and the noise signal. Subsequently, at the timing further delayed by one channel, DSP
At 1, the tone waveform data of the channel is summed with the tone waveform data of the other channels. In this way, in addition to causing each of the DSPs 1 to 4 to execute an operation in parallel, the DSP 1 to the DSP 4 execute the operation of each channel by shifting the channel timing with respect to each other in accordance with the processing content programmed in each DSP. This makes it possible to generate musical tone waveform data at a higher speed.

Next, assuming that each of the DSP1 to DSP4 operates at the time-division channel timing shown in FIG. 8, the operation of synthesizing the tone waveform based on the cooperation of the DSPs will be described. FIGS. 10, 12 and 14 show the DSPs 1 to D, respectively.
FIG. 4 is an operation function development block diagram showing circuit elements in SP4 combined with each other along a programmed processing flow, and shows a state in which each of DSP1 to DSP4 is associated with and cooperates with each other; Is represented by In addition, DS
The circuit element P2 is not shown in FIGS. 10, 12, and 14 for convenience of description.

First, an operation example of synthesizing a musical sound waveform by the formant sound synthesizing method based on the cooperation of the DSPs 1 to 4 will be described. Hereinafter, a musical sound waveform in a method of obtaining a final formant sound waveform by obtaining two series of formant sound waveforms based on two series of pitch frequency phase data and formant center frequency phase data, and adding these formant sound waveforms. Will be described. In this way, two (or three or more) formant sound waveforms are synthesized based on two (or three or more) phase data, and the final form is obtained by adding them. As a method for obtaining a suitable formant sound waveform, for example, a method already disclosed by the present applicant in Japanese Patent Application Laid-Open No. 2-254497 can be basically used. It should be noted that each of the DSP1 to DSP4 should perform arithmetic processing in the "formant sound synthesis mode" mode.
Selection of tone color etc. by PS (FIG. 1) or other appropriate means /
Instructed by the value of the tone synthesis algorithm parameter ALG given according to the setting operation. For example, when the parameter ALG is “0”, it indicates that the arithmetic processing should be performed in the “formant sound synthesis mode” mode.

Operation Example of DSP1 for Formant Sound Synthesis FIG. 9 shows an operation example of each step of the microprogram "phase operation" and "mixing operation" of the DSP1 when synthesizing a formant sound. . One cycle of the microprogram includes 21 steps S0 to S20, and one step corresponds to one cycle of the system clock. This one cycle corresponds to the one-channel timing in FIG. 8, and the program cycle for each channel is executed in 18-channel time division as shown in FIG.
Steps S0 to S10 and S13 to S18 are “phase calculation”
And steps S11, S12, S
Steps 19 and 20 are steps for "mixing operation". In FIG. 9, (a) shows "A" of the arithmetic unit ALU1.
(B) shows data set in a state of being input to the input;
Indicates data set to be input to the "B" input of the arithmetic unit ALU1, (c) indicates the content of data # 1,
(D) shows the contents of the data written and input to the register REG1, and (e) shows the contents of the data input written to the RAM1. FIG. 10 is a functional block diagram showing a process of creating phase data in the DSP 1. Therefore, this drawing is not a diagram showing the actual hardware circuit configuration.

(1) Operation of DSP 1 in Step S0 In Step S0, an operation for modulating the value of the pitch frequency number FNUM used to create the pitch frequency phase data PGp1 and PGp2 of two series of formant sounds is performed. , Using the arithmetic unit ALU1 (FIG. 5).
9 (a) and 9 (b) show the input data to the A and B inputs of the arithmetic unit ALU1 in a simplified manner. In step S0, the A input of the arithmetic unit ALU1 corresponds to the pitch frequency number FNUM. The phase increment value data is input, and a state is set in which the attack glide data AG is input as the B input of the arithmetic unit ALU1. Note that FIG.
The meaning of n or n-1 in parentheses together with FNUM in (a) will be described later.

More specifically, in FIG. 5, the pitch frequency number FNU is
M and the parameters VIB and DVB for vibrato are given, and the selector 10 selects the linear-log converter 1
3 is selected. by this,
Vibrato modulation controlled pitch frequency number FNU
The data obtained by converting M into a logarithmic value is a linear-log converter 13.
Is selected by the selector 10 and input to the A input of the arithmetic unit ALU1 via the log-linear converter / shifter 14 and the delay circuit 15. In this step S0, the log-linear conversion / shift unit 14 and the log-linear conversion /
The shift / ± unit 16 passes the input data without performing any conversion or shift operation.

On the other hand, the RA of the DSP 2
Attack glide data AG of the logarithmic expression of the corresponding channel is read from M2, and is read as data # RAM2
Is supplied to the DSP 1 via the data bus DBUS and input to the selector 11. The selector 11 selects and outputs the data # RAM2, that is, AG, and inputs it to the B input of the arithmetic unit ALU1 via the log-linear conversion / shift / ± unit 16 and the delay circuit 17. Therefore, a vibrato-controlled pitch frequency number F of logarithmic representation
NUM and attack glide data AG are calculated by ALU1
Is added. As is well known, the addition of logarithms corresponds to the multiplication of the logarithmic antilogarithms (that is, linear numbers). Therefore, at the antilogarithm level, the vibrato-controlled pitch frequency number FNUM is multiplied by the attack glide data AG. Thus, the arithmetic processing for performing the attack glide modulation is performed.

In this way, in step S0, the calculation for modulating the value of the pitch frequency number FNUM is performed, and the modulated pitch frequency number FNUM is obtained as a logarithmic value. The modulated pitch frequency number FNUM is obtained by a delay of a total of three clocks by each of the delay circuits 15, 17, 18, and 19, and then a step S3 described later.
Is output as output data # 1 via the output controller 20 at the timing of.

For the sake of reference, the above arithmetic processing will be arranged along the arithmetic function development diagram of FIG. In FIG. 10, the circuit elements with the same initials as those in FIG. 5 indicate the same or corresponding elements. In addition, the step number written in parentheses at the end of the reference numeral of each circuit element in FIG. 10 indicates that the circuit element functions in that step. For example, "ALU1 (S0)" indicates that the circuit element corresponds to the arithmetic unit ALU1 that functions in step S0. Therefore, regarding the processing in step S0, pay attention to the circuit route indicated by (S0) in FIG. 12 and 14 described later.
Also uses the same notation.

In FIG. 10, the vibrato data generator 12
a (S0), AND gate 12b (S0) and adder 1
2c (S0) corresponds to the modulation unit 12 (FIG. 5), and periodic vibrato data having a depth and a speed corresponding to the vibrato depth and the speed parameter DVB is output from the vibrato data generator 12a (S0). Generated and gate 1
2b (S0). AND gate 12b (S
0) is enabled when the vibrato on / off parameter VIB specifies vibrato on, and outputs the above periodic vibrato data. AND gate 12b (S
0) is added to the adder 12c.
In (S0), it is added to the pitch frequency number FNUM,
Data obtained by vibrato-modulating the pitch frequency number FNUM is output. The output of the adder 12c (S0) is converted into a logarithmic value by a linear-log converter 13 (S0).
Then, as described above, the arithmetic unit ALU1 (S0) adds the attack glide data AG.

(Description of Channel Synchronization Operation) In connection with the fact that the modulation operation of the pitch frequency number FNUM is performed in step S0 as described above, the "channel synchronization operation" function will be described below. The “channel synchronization operation” is a function of automatically and simultaneously controlling the tone generation of the same pitch in a plurality of adjacent tone generation channels. The channel synchronization operation flag RBP is used for this function. This flag RBP is provided for each channel. For example, the flag RBP of channel 1 is set to “0”.
In the case where the flags RBP of the adjacent channels 2 and 3 are “1”, respectively,
Is controlled so that a musical tone having the same pitch as the musical tone assigned to is automatically generated at the same timing as the key-on timing (sound generation timing) of channel 1. The channel synchronization operation flag RBP is provided from the microcomputer COM for each channel in accordance with a tone color setting or a selection operation or a selection operation in the operation unit OPS.

Therefore, in the process of step S 0, if the channel synchronization operation flag RBP of the channel currently being processed (this channel number is indicated by n) is “0”, the pitch frequency number FN supplied to the modulation unit 12
As the UM, a pitch frequency number FNUMn indicating the pitch of a musical tone assigned to the channel n is given. In this case, various processes related to key-on / off, including the generation of an envelope in the DSP 2, are performed based on the key-on signal KON (ie, KONn) of the musical tone assigned to the channel n.

On the other hand, if the channel synchronization operation flag RBP of the channel n currently being processed is “1” in the process of step S 0, the pitch frequency number FNUM to be supplied to the modulation unit 12 is set to 1 of the channel n.
The previous channel n-1 (for example, if n = 2, n-
A pitch frequency number FNUMn-1 indicating the pitch of the musical tone assigned to 1 = 1) is given.
In this case, various processes related to key-on / off, including the generation of an envelope in the DSP 2, are performed based on the key-on signal KON (ie, KONn-1) of the musical tone assigned to the immediately preceding channel n-1. To do. Note that the channel number is assumed to be the smallest, and when n = 1, the pitch frequency number FNUMn of its own channel and the key-on signal KON (that is, the key-on signal KON) regardless of the value of the channel synchronization operation flag RBP of the channel n = 1. KONn).

Therefore, when the flag RBP is “1”, the adjacent channel n and channel n−1 (when the data of the RBP is “1” even in the channel n−1,
In all the adjacent channels up to the channel with the smallest number whose RBP data is "0", the musical tone waveform synthesis processing is performed in synchronization with the same pitch and sound generation start timing. As an example, the flag RB of channel 1
P is “0” and the flag RB of channels 2, 3, and 4
P is “1”, and the flags RBP from channel 5 to channel 18 are “0”,
"1", "1", "1", "0", "1", "1",
"1", "1", "0", "0", "1", "0",
If it is "0", the tone waveform synthesis processing is performed in the channels 1 to 4 in synchronism with the same pitch and tone generation start timing as the tone assigned to the channel 1, and in the channels 5 to 8, all the channels are processed. The tone waveform synthesizing process is performed in synchronization with the same pitch and tone generation start timing as the tone assigned to channel 5, and all channels 9 to 13 are synchronized with the same pitch and tone generation start timing as the tone assigned to channel 9. The tone waveform synthesis processing is performed. In the channel 14, the tone waveform synthesis processing is performed independently at the pitch of the musical tone assigned to the channel 14 and the tone generation start timing, and the channels 15 and 16 are assigned to the channel 15. Synthesizing sound waveforms at the same pitch and tone generation timing Management is performed, the channel 17 and 18, independently tone waveform synthesis processing on the pitch and the sound start timing of the tone allocated to the channel of each is performed.

As described above, by performing musical tone waveform synthesis processing based on the same pitch and the same key-on timing in a plurality of adjacent channels, the pitch of the musical tone is the same, but independent formant frequency numbers are provided for each channel. Formant sounds are synthesized at different formant center frequencies according to the FORM data, and the sounding timings of these formant sounds are completely synchronized. Therefore, the musical sounds (formant sounds) of the channels synchronized with each other are apparently As a result, it is possible to obtain a tone having a multimodal formant characteristic composed of a plurality of different formant components.

(2) Operation of DSP 1 in Step S2 In step S2, an operation for modulating the value of the formant frequency number FORM used to create the two series of center frequency phase data PGf1 and PGf2 of the formant sound is performed. , Using the arithmetic unit ALU1 (FIG. 5). As shown in FIGS. 9A and 9B, in step S2, phase increment value data corresponding to the formant frequency number FORM is input as an A input of the arithmetic unit ALU1, and attack glide data is input as a B input of the arithmetic unit ALU1. The state is set so that AG is input.

More specifically, in FIG. 5, the formant frequency number FORM and the parameters DFM and FOM for modulating the formant sound center frequency are given as input parameters to the modulating section 12, and the selector 10 includes a linear-log converter 13 Is selected. As a result, data obtained by converting the frequency-controlled formant frequency number FORM into a logarithmic value is output from the linear-log converter 13, which is selected by the selector 10, and is selected by the log-linear converter / shifter 14 and the delay circuit. 15 to the A input of the arithmetic unit ALU1. In step S2, under the control of the controller 23, the log-linear conversion / shift unit 14 and the log-linear conversion / shift / ± unit 16 do not perform any conversion or shift operation, and pass the input data as it is.

On the other hand, as the output data # RAM2 read from the RAM 2 of the DSP 2, the attack glide data AG of the logarithmic expression of the corresponding channel is selected by the selector 11.
Is selected by the selector 11, and is input to the B input of the arithmetic unit ALU1 via the log-linear conversion / shift / ± unit 16 and the delay circuit 17. Accordingly, the arithmetic unit ALU1 adds the logarithmic formant frequency number controlled formant frequency number FORM and the attack glide data AG. As a result, at the true level, the formant frequency number FORM subjected to the frequency modulation control is multiplied by the attack glide data AG to perform the arithmetic processing for performing the attack glide modulation.

Thus, in step S2, the calculation for modulating the value of the formant frequency number FORM is performed, and the modulated formant frequency number FORM is obtained as a logarithmic value. The modulated formant frequency number FORM is stored in each of the delay circuits 15, 1
After a total of three clock delays by 7, 18, and 19, the data is output as output data # 1 via the output controller 20 at the timing of step S5 described later.

The above-described arithmetic processing in step S2 is organized according to the arithmetic function development diagram of FIG. 10. In FIG. 10, the modulation data generator 12d (S2), the AND gate 1
2e (S2) and the adder 12f (S2)
(FIG. 5), the modulation data generator 12d (S2) generates periodic frequency modulation data having a depth and a speed corresponding to the frequency modulation depth and speed parameter DFM, and an AND gate 12e. (S2) is input. The AND gate 12e (S2) is enabled when the frequency modulation on / off parameter FOM specifies frequency modulation on, and outputs the above periodic frequency modulation data. The frequency modulation data output from the AND gate 12e (S2) is added to the formant frequency number FORM by the adder 12f (S2), and the formant frequency number F
Data obtained by frequency-modulating the ORM is output. The output of the adder 12f (S2) is output to the linear-log converter 13
It is converted to a logarithmic value in (S2), and the arithmetic unit ALU1 (S2)
Is added to the attack glide data AG.

(3) Operation of DSP 1 in Step S3 As shown in FIGS. 9A and 9B, in Step S3,
Data # 1 is input as the A input of the arithmetic unit ALU1,
A state is set in which data indicating a value “0” is input as the B input of the arithmetic unit ALU1.

More specifically, in FIG. 5, the selector 10 is in a state of selecting data # 1, and the selector 11 is in a state of selecting data having a value "0". As the data # 1, the pitch frequency number FNUM (logarithmic value) modulated in step S0 is given at the timing of this step S3, which is delayed by three clocks (FIG. 9C). In step S3, under the control of the controller 23, the log-linear converter / shifter 14
Modulated pitch frequency number FNUM output from
The log-linear conversion / shift / ± unit 16 does not perform either the conversion or the shift operation, and passes the “0” data output from the selector 11 as it is. Therefore, the modulated pitch frequency number FNUM converted to an antilog number and “0” are added by the arithmetic unit ALU1, but this is only performed by passing the pitch frequency number FNUM consisting of an antilog value. It means there is.

As described above, in step S3, an operation for converting the modulated pitch frequency number FNUM in logarithmic expression to an antilog is performed. The true value of the pitch frequency number FNUM thus converted is written to the register REG1 via the output controller 20 at the timing of step S6 described later, after a total of three clock delays by the delay circuits 15, 17, 18, and 19. It is. FIG.
In FIG. 10, the log-linear converter 14 (S3) corresponds to the calculation function of the log-linear converter / shifter 14 (FIG. 5) in step S3. The executed arithmetic unit ALU1 (S
0), that is, the modulated pitch frequency number FNUM is input to the log-linear converter 14 (S3) and is converted into an antilog.

(4) Operation of DSP 1 in Step S4 In step S4, an arithmetic operation for modulating the value of the unvoiced formant frequency number UFORM used to generate the center frequency phase data PGu of the unvoiced formant sound is performed by the arithmetic unit. This is performed using ALU1 (FIG. 5). FIG.
As shown in (a) and (b), in step S4, the phase increment value data corresponding to the unvoiced formant frequency number UFORM is input as the A input of the arithmetic unit ALU1, and the attack glide data AGu is input as the B input of the arithmetic unit ALU1. Is set to be input.

More specifically, in FIG. 5, unvoiced formant frequency number UFORM and parameters UDFM and UFOM for unvoiced formant sound center frequency modulation are given as input parameters to modulating section 12, and
In the selector 10, the output from the linear-log converter 13 is selected. As a result, data obtained by converting the frequency-modulated unvoiced formant frequency number UFORM into a logarithmic value is output from the linear-log converter 13, which is selected by the selector 10 and
The signal is input to the A input of the arithmetic unit ALU1 via the linear converter / shifter 14 and the delay circuit 15. Note that, in this step S4, the log-
In the linear conversion / shift unit 14 and the log-linear conversion / shift / ± unit 16, neither the conversion nor the shift operation is performed, and the input data is passed as it is.

On the other hand, as output data # RAM2 read from RAM2 of DSP2, attack glide data AGu expressed in logarithmic expression of the corresponding channel is selected by selector 1.
1 is selected by the selector 11 and the log-
The signal is input to the B input of the arithmetic unit ALU1 via the linear conversion / shift / ± unit 16 and the delay circuit 17. Therefore, a frequency-modulated unvoiced formant frequency number UFORM and a logarithmic representation of the attack glide data AG
u is added by the arithmetic unit ALU1. Thus, at the true level, the attack glide data AG is added to the frequency-modulated unvoiced formant frequency number UFORM.
By multiplying by u, the arithmetic processing for performing the attack glide modulation is performed.

As described above, in step S4, the calculation for modulating the value of the unvoiced formant frequency number UFORM is performed, and the modulated unvoiced formant frequency number UFORM is obtained as a logarithmic value. This modulated unvoiced formant frequency number UFORM is
After a total of three clock delays by the delay circuits 15, 17, 18, and 19, the output data # is output via the output controller 20 at the timing of step S7 described later.
Output as 1.

In the operation function development diagram of FIG. 10, the modulation data generator 12g (S4), the AND gate 12h (S4), and the adder 12i (S4) correspond to the modulation unit 12 (FIG. 5). Periodic frequency modulation data having a depth and a speed corresponding to the depth and speed parameters UDFM is generated from the modulation data generator 12g (S4) and input to the AND gate 12h (S4). AND gate 12h
(S4) is enabled when the frequency modulation on / off parameter UFOM specifies frequency modulation on, and outputs the above periodic frequency modulation data. AND gate 12h
The frequency modulation data output from (S4) is added to the adder 12
Silent formant frequency number UFOR at i (S4)
M, added to the silent formant frequency number UFO
Data obtained by frequency-modulating the RM is output. The output of the adder 12i (S4) is output to the linear-log converter 13 (S4).
The data is converted into a logarithmic value in 4), and is added to the attack glide data AGu in the arithmetic unit ALU1 (S4).

(5) Operation of DSP 1 in Step S5 As shown in FIGS. 9A and 9B, in Step S5,
Data # 1 is input as the A input of the arithmetic unit ALU1,
A state is set in which data indicating a value “0” is input as the B input of the arithmetic unit ALU1. Specifically, in FIG. 5, the modulated formant frequency number FORM (logarithmic value) in step S2 is given as data # 1.
At the same time, the selector 10 is set to select this data # 1. In this step S5, the log-linear converter / shifter 1 is controlled by the controller 23.
4 converts this logarithmic value to an antilog number, but the log-linear conversion / shift / ± unit 16 does not perform any conversion or shift operation, and passes the input data as it is.

On the other hand, the data indicating the value “0” is the selector 1
1 is selected by the selector 11 and the log-
The signal is input to the B input of the arithmetic unit ALU1 via the linear conversion / shift / ± unit 16 and the delay circuit 17. Therefore, the modulated formant frequency number FO converted to an antilog
RM and “0” are added by the arithmetic unit ALU1. In this way, in step S5, an operation for converting the modulated formant frequency number FORM into an antilog is performed. The true value of the modulated pitch frequency number FNUM is written to the register REG1 via the output controller 20 at the timing of step S8 to be described later, after a total of three clock delays by the delay circuits 15, 17, 18, and 19. It is.

In the operation function development diagram of FIG. 10, the log-linear converter 14 (S5) is the log-linear converter / shifter 1
4 (FIG. 5), and the modulated formant frequency number FO output from the arithmetic unit ALU1 (S2).
It is shown that the RM is input to the log-linear converter 14 (S5) and is converted to an antilog.

(6) Operation of DSP 1 in Step S6 In step S6, the pitch frequency phase data P
An arithmetic unit ALU1 (FIG. 5) is used to make the value of the pitch frequency number FNUM used to create Gp1 and PGp2 a predetermined number of times. In this step S6, the pitch frequency number FNUM converted into an exact value by the processing in step S3 is given to the input of the register REG1 with a delay of three clocks, and is taken into the register REG1 as shown in FIG. Stored. It is assumed that the output data # REG1 of the register REG1 has no time delay with respect to the write input, and the taken-in pitch number FNUM of an exact numerical value is immediately output as the data # REG1.

As shown in FIGS. 9A and 9B,
In step S6, a state is set in which data obtained by processing the data # REG1 is input as the A input and the B input of the arithmetic unit ALU1. That is, in FIG.
As REG1, the pitch frequency number FNUM converted to an exact number in step S3 is provided to the selectors 10 and 11, and the selectors 10 and 11 are set to select this data # REG1. On the other hand, in step S6, the frequency multiple parameter MULT1 is provided to the controller 23 via the selector 22, and the log-multiple parameter MULT1 is controlled by the controller 23 based on the parameter.
The linear conversion / shift unit 14 performs a shift operation by a predetermined number of digits (this number of digits will be described later), and the log-linear conversion / shift / ± unit 16 performs a shift operation by a predetermined number of digits ( The number of digits will also be described later) and the operation of inverting the sign is performed (normally, the sign of the frequency number is inverted to the sign). The operation of inverting the sign is a process for causing the arithmetic unit ALU1 to function as a subtractor.

Therefore, the arithmetic unit ALU1 subtracts the pitch frequency number FNUM shifted by a predetermined digit from the pitch frequency number FNUM shifted by a predetermined digit. Here, the number of digits is such that the result of this subtraction is larger than the value of the initial pitch frequency number FNUM by the parameter MULT.
It is set to be larger by a multiple indicated by 1. For example, when the multiple indicated by the parameter MULT1 is “3”, the predetermined number of shift digits in the log-linear conversion / shift unit 14 is “2”, and the log-linear conversion / shift /
The predetermined number of shift digits in the encoder 16 is "0".
Thus, by adding the pitch frequency number FNUM which has not been shifted but the sign of which is inverted to the negative to the pitch frequency number FNUM which has been increased by four times by shifting up by 2 bits, "4 × FNUM" is obtained.
−FNUM = 3 × FNUM ”is performed, and as a result, pitch frequency number data three times larger than the value of the initial pitch frequency number FNUM is obtained. As described above, by performing a shift operation (2n-th power operation) with a predetermined shift number in each of two sequences and subtracting the multiple indicated by the parameter MULT1, a total of 2 n Arbitrary multiples other than the multiplication (for example, 3, 5, 6, 7, etc.) can be performed.

The pitch frequency number FNUM data changed to the desired multiple in step S6 is delayed by a total of three clocks by each of the delay circuits 15, 17, 18, and 19 at the timing of step S9 described later. The data is written to the register REG1 via the output controller 20.

The operation function development diagram corresponding to step S6 is shown in FIG. 10 along the path following log-linear converter 14 (S3), and shifter 1 shown there.
4 (S6) is a log-linear converter / shifter 14 (FIG. 5)
, The shifter 16a (S6) and the inverting circuit 16b
(S6) corresponds to the log-linear conversion / shift / ± unit 16 (FIG. 5), and the shift controller 23 (S6).
Corresponds to the controller 23 (FIG. 5). That is, the log-linear converter 14 (S
In step S6, the pitch frequency number FNUM (exact value) converted into an exact value by the process according to 3) is:
The data is input to the shifters 14 (S6) and 16a (S6).
The shifters 14 (S6) and 16a (S6) are provided with a shift controller 23 (S6) according to the parameter MULT1.
, The pitch frequency number FNUM is shifted by a predetermined number of digits as described above. Shifter 16a
The output of (S6) is output from the inversion circuit 16 under the control of the shift controller 23 (S6) according to the parameter MULT1.
In step b (S6), the sign is inverted to a negative value. Then, the output of the shifter 14 (S6) and the inversion circuit 16b (S
The output of 6) is added by the arithmetic unit ALU1 (S6).

(7) Operation of DSP 1 in step S7 In step S7, the arithmetic unit ALU1 performs an operation of accumulating the modulated unvoiced formant frequency number UFORM to generate progressive phase data PGu that changes sequentially.
(FIG. 5). As shown in FIGS. 9A and 9B, in step S7, data # 1 is input as the A input of the arithmetic unit ALU1, and the phase data PGu obtained in the previous cycle is input as the B input of the arithmetic unit ALU1. Is set to

More specifically, in FIG. 5, the unvoiced formant frequency number UFORM processed in step S4
(Logarithmic value) is delayed by 3 clocks and the data #
1 and the selector 10 is set to select this data # 1. This step S7
Then, under the control of the controller 23, the log-linear conversion / shift unit 14 converts this logarithmic value into an antilogarithm, but the log-linear conversion / shift / ± unit 16 does not perform any conversion or shift operation. , Pass the input data as it is.

On the other hand, in this step S7, the phase data PGu of the corresponding channel is read from the RAM 1 and input to the selector 11 as output data # RAM1. The selector 11 is set to a state in which the RAM read data # RAM1 is selected. The data # RAM1, that is, the progressive phase data PGu for the noise signal, is input to the B input of the arithmetic unit ALU1 through the log-linear conversion / shift / ± unit 16 and the delay circuit 17. Thus, the arithmetic unit ALU1 stores the unvoiced formant frequency number UFORM (exact value) in the RAM1.
Is added to the progressive phase data PGu read from the. This addition result is output to each of the delay circuits 15, 17, 1
After a total of four clock delays by 8, 19, and 24, the data is stored in the storage area of the phase data PGu of the RAM 1 via the output controller 20 at the timing of step S11 described later. In this way, in step S7, the unvoiced formant frequency number UFORM is accumulated for each cycle, phase data PGu is generated as a result of the accumulation, and stored in the RAM 1.

The operation function development diagram corresponding to this step S7 is shown in the path following the operation unit ALU1 (S4) in FIG. 10, and the log-linear converter 14 (S7) shown there is A phase generator ALU1 & RAM1 (S7) corresponding to the linear converter / shifter 14 (FIG. 5);
Corresponds to the arithmetic unit ALU1 and the RAM1 (FIG. 5).
The unvoiced formant frequency number UFO obtained by the operation of the arithmetic unit ALU1 (S4) in step S4
After the RM (logarithmic value) is input to the log-linear converter 14 (S7) and converted to an antilog, the phase generator ALU1 &
The phase data PGu is accumulated by the accumulation in the RAM 1 (S7).

(8) Operation of DSP 1 in Step S8 As shown in FIGS. 9A and 9B, in Step S8,
A state is set in which data # REG1 is input as the A input of the arithmetic unit ALU1 and data indicating the value "0" is input as the B input of the arithmetic unit ALU1.

More specifically, in FIG. 5, the modulated formant frequency number F converted to an antilog in step S5
The ORM is taken into the register REG1 in this step S8 with a delay of three clocks (see FIG. 9D), and is output from the register REG1 as data # REG1.
The selector 10 selects the data # REG1, and the selector 11 selects "0". Further, under the control of the controller 23, the log-linear conversion / shift unit 14 and the log-linear conversion / shift / ± unit 16 do not perform any conversion or shift operation, and pass the input data as it is. Therefore, the formant frequency number FORM consisting of an exact value only passes through the arithmetic unit ALU1.

The formant frequency number FORM output from the arithmetic unit ALU1 is determined by the delay circuits 15, 17,
After a total of three clock delays by 18 and 19, the data is written to the register REG1 via the output controller 20 at the timing of step S11 described later. In this step S8, since only the process of setting the contents of the data # REG1 at the timing after step S11 to the modulated formant frequency number FORM (exact numerical value) is performed, it is not particularly shown in FIG.

(9) Operation of DSP 1 in Step S9 In Step S9, the data of the pitch frequency number FNUM, which has been increased by a predetermined multiple in Step S6, is set to 1
The calculation for generating the pitch frequency phase data PGp1 of the series is performed using the arithmetic unit ALU1 (FIG. 5). FIG.
As shown in (a) and (b), in step S9, the data # REG1 is input as the A input of the arithmetic unit ALU1, and the first series of pitch frequency phase data PGp1 is input as the B input of the arithmetic unit ALU1. Set to state.

More specifically, in FIG. 5, the pitch frequency number FNUM processed in step S6 is taken into the register REG1 in this step S9 with a delay of three clocks (see FIG. 9D), and the register REG1 is stored as data # REG1. Output from The selector 10 is set to select this data # REG1. In this step S9, under the control of the controller 23,
The log-linear conversion / shift unit 14 shifts down the pitch frequency number data by one bit (the reason will be described later), but the log-linear conversion / shift / shift
In the ± unit 16, neither the conversion nor the shift operation is performed.
Pass the input data as is.

On the other hand, in this step S9, the phase data PGp1 of the corresponding channel is read from the RAM 1 and input to the selector 11 as output data # RAM1. The selector 11 is set to a state in which the RAM read data # RAM1 is selected. This data # RAM1, that is, the progressive phase data PGp1 for the pitch frequency is obtained by log-linear conversion / shift / ± unit 1
6 and the delay circuit 17 and is input to the B input of the arithmetic unit ALU1. Accordingly, the arithmetic unit ALU1 adds the pitch frequency number data shifted down by 1 bit and the phase data PGp1 read from the RAM1. The reason why the pitch frequency number data is shifted down by one bit by the log-linear converter / shifter 14 is that, as described at the beginning of the description of the waveform synthesizing operation by this formant sound synthesizing method, two series of formant sound waveforms are used. Since the final formant sound waveform is obtained by the addition, the pitch frequency phase data of each series is set to half the original size.

Thus, in the arithmetic unit ALU1, the value of 1/2 of the pitch frequency number is added to the progressive phase data PGp1 read from the RAM1. This addition result is output to each of the delay circuits 15, 17, 18, 19, 24
After a total delay of four clocks, the output controller 20
Is stored in the storage area of the phase data PGp1 in the RAM1. In this way, in step S9, half the pitch frequency number data obtained by increasing the value of the modulated pitch frequency number FNUM by a predetermined number of times is accumulated for each cycle, and the accumulated value is calculated. As the calculation result, the first series of pitch frequency phase data PGp1 is obtained. still,
The phase data PGp1 is initialized to a predetermined value (for example, “0”) by the output controller 20 when the performance operator of the electronic musical instrument is turned on (that is, at the start of musical sound generation). An example of a change in the value of the pitch frequency phase data PGp1 of the first series created in this way is shown in FIG.
(A).

The operation function development diagram corresponding to step S9 is shown in the path following operation unit ALU1 (S6) in FIG. 10, and the phase generator ALU shown there
1 & RAM1 (S9, S10) are arithmetic units ALU1 and RA
M1 (FIG. 5). The pitch frequency number data obtained by the operation of the arithmetic unit ALU1 (S6) in step S6 is stored in the phase generator ALU1 & RAM1.
The pitch frequency phase data PGp accumulated in (S9)
1 is created.

(10) DSP1 in step S10
In step S10, the arithmetic unit ALU1 (FIG. 5) uses the arithmetic unit ALU1 (FIG. 5) to generate the second series of pitch frequency phase data PGp2 using the data of the pitch frequency number FNUM that has been multiplied by a predetermined number in step S6. Do it. FIG.
As shown in (a) and (b), in step S10, the data # REG1 is input as the A input of the arithmetic unit ALU1, and the second series of pitch frequency phase data PGp2 is input as the B input of the arithmetic unit ALU1. Set to state.

More specifically, in FIG. 5, data #REG
As 1, the same pitch frequency number data as in step S9 is given, and the selector 10 is set to select this data # REG1. Also in this step S10, under the control of the controller 23, the log-linear converter / shifter 14 shifts down this pitch frequency number data by one bit (the reason is the same as that described in step S9). However, in the log-linear conversion / shift / ± unit 16, neither the conversion nor the shift operation is performed, and the input data is passed as it is.

On the other hand, in this step S10, the RAM 1
, The phase data PGp2 of the corresponding channel is read out and input to the selector 11 as output data # RAM1, which is selected by the selector 11 and operated via the log-linear conversion / shift / ± unit 16 and the delay circuit 17. Is input to the B input of the ALU1. Therefore, the pitch frequency number data shifted down by 1 bit and R
The arithmetic unit ALU1 adds the phase data PGp2 read from AM1. This addition result is output to each delay circuit 1
After a total of four clock delays by 5, 17, 18, 19, and 24, the data is stored in the storage area of the phase data PGp2 of the RAM 1 via the output controller 20 at the timing of step S14 described later.

In this manner, in step S10, the value of the modulated pitch frequency number FNUM is set to a value several times as large as 1/2 of the pitch frequency number data obtained.
Is accumulated for each cycle, and as a result of the accumulation, pitch frequency phase data PGp2 of the second series is obtained. When the performance operator of the electronic musical instrument is turned on, the phase data PGp2 is output to the output controller 20.
With respect to the initial value of the phase data PGp1,
A value shifted by 80 degrees (that is, the phase data PGp1)
Is an initial value of half of the maximum phase value, that is, a value corresponding to 180 degrees or π). FIG. 17B shows an example of the second series of pitch frequency phase data PGp2 created in this way.
As shown in this figure, the pitch frequency phase data PGp1 of the first series and the pitch frequency phase data PGp2 of the second series are mutually displaced because the initial setting is shifted by half of the maximum phase value. It occurs with a shift of half a cycle.

The operation function development diagram corresponding to step S10 is similar to step S9 in FIG.
The phase generator ALU1 & RAM1 (S9, S1) is shown in the path following LU1 (S6).
0) corresponds to the arithmetic unit ALU1 and the RAM1 (FIG. 5). The pitch frequency number data obtained by the operation of the arithmetic unit ALU1 (S6) in step S6 is accumulated by the phase generator ALU1 & RAM1 (S10),
Pitch frequency phase data PGp2 is created.

(11) DSP1 in step S13
Steps S11 and S12 are steps for performing a "mixing operation", and therefore will be described in detail after the description of the operation of the DSP 4, and will proceed to step S13. The modulated formant frequency number FORM composed of an antilog representation processed in step S8 is given to the input of the register REG1 in step S11 three clocks later, and is taken into the register REG1 (see FIG. 9D). In step S13, an operation of creating the first series of center frequency phase data PGf1 by accumulating the formant frequency number FORM stored in the register REG1 and output as the data # REG1 is performed by:
This is performed using the arithmetic unit ALU1 (FIG. 5).

As shown in FIGS. 9A and 9B, in step S13, the data # is input to the A input of the arithmetic unit ALU1.
REG1 is input and 1 is input as the B input of the arithmetic unit ALU1.
The center frequency phase data PGf1 of the series is set to be input. More specifically, in FIG.
At 0, the data # REG1 is selected, and the formant frequency number FORM output from the register REG1 is selectively output. Further, under the control of the controller 23, the log-linear conversion / shift unit 14 and the log-linear conversion / shift / ± unit 16 do not perform any conversion or shift operation, and pass the input data as it is.

On the other hand, the center frequency / phase data PGf1 of the first channel of the corresponding channel is read out from the RAM 1 and input to the selector 11 as data # RAM1, which is selected by the selector 11 to perform log-linear conversion / shift. Arithmetic unit A via the / ± unit 16 and the delay circuit 17
It is input to the B input of LU1. Therefore, the arithmetic unit ALU1
Then, formant frequency number FORM is RAM
1 is added to the phase data PGf <b> 1 read.
This addition result is output to each of the delay circuits 15, 17, 18, 19,
After a total of four clock delays due to 24, the data is stored in the storage area of the phase data PGf1 of the RAM 1 via the output controller 20 at the timing of step S17 described later. In this manner, in step S13, the formant frequency number FORM is accumulated for each cycle to create the first series of center frequency phase data PGf1. The phase data PGf1 is initially set to a predetermined initial value (for example, “0”) by the output controller 20 when the performance operator of the electronic musical instrument is turned on, and the first series of pitch frequency phase data PGp
Also at the time of 1 overflow, the output controller 20 resets it to a predetermined initial value (for example, “0”). An example of the center frequency phase data PGf1 of the first series created in this way is shown in FIG.

FIG. 10 is an exploded view of the arithmetic function corresponding to step S13.
Is shown in the path of the selector SEL1 subsequent to. The selector SEL1 is a control signal generator 6 of the DSP 1 (FIG. 3)
Phase generator ALU1 & RAM1
(S13, S16) correspond to the arithmetic unit ALU1 and the RAM1 (FIG. 5). The formant frequency number FORM, which has been converted to an exact value by the log-linear converter 14 (S5) by the processing of step S5, is selected by the selector SEL1 in the formant sound synthesis mode and is made available for phase calculation. Phase generator ALU1 & RA
M1 (S13, S16) is accumulated to create the first series of center frequency phase data PGf1.

(12) DSP1 in step S14
In step S14, an accumulation operation for creating the first series of window function phase data PGw1 based on the formant bandwidth (= window function time width) designation parameter BW is performed using the arithmetic unit ALU1 (FIG. 5). Do. As shown in FIGS. 9A and 9B, in step S14, A of the arithmetic unit ALU1
Window function frequency number based on formant bandwidth specification parameter BW as input (denoted as BW for convenience)
Is input, and the first-series window function phase data PGw1 is set as the B input of the arithmetic unit ALU1.

Specifically, in FIG. 5, the selector 10 does not select any data. Then, the formant bandwidth designation parameter BW is input to the controller 23 via the selector 22, and under the control of the controller 23, the log-linear converter / shifter 14 outputs the window function frequency according to the parameter BW. The number is output. On the other hand, the window function phase data PGw1 of the corresponding channel is read from the RAM 1 and is input to the selector 11 as data # RAM1, and is selected by the selector 11 and passed through the log-linear conversion / shift / ± unit 16 as it is. Is input to the B input of the arithmetic unit ALU1 via the delay circuit 17. Therefore, the arithmetic unit ALU1 adds the window function frequency number and the phase data PGw1 read from the RAM1.

The result of this addition is calculated by the delay circuits 15, 17,
After a total of three clock delays by 18 and 19, the data is output as output data # 1 via the output controller 20 at the timing of step S17 described later.
The window function phase data PGw1 is stored in the output controller 2 when the performance operator of the electronic musical instrument is turned on.
It is initialized to a predetermined value (for example, “0”) by 0, and is also reset to a predetermined value (for example, “0”) by the output controller 20 when the pitch frequency phase data PGp1 of the first system overflows. The development diagram of the arithmetic function corresponding to step S14 is shown in the path of the window function frequency number generator 14 (S14, S15) in FIG. Window function frequency number generator 14 (S
14, S15) is the log-linear converter / shifter 1 of FIG.
Window function phase generator ALU1 & RAM1
(S14, S15) correspond to the arithmetic unit ALU1 and the RAM1.

(13) DSP1 in step S15
In step S15, almost the same as step S14, based on the formant bandwidth designation parameter BW, 2
An operation for creating the window function phase data PGw2 of the series is
This is performed using the arithmetic unit ALU1 (FIG. 5). Step S15
Is different from the case of step S14 in that the RAM 1
, The window function phase data PGw2 of the second series of the corresponding channel is read and input to the selector 11 as data # RAM1, and this is selected by the selector 11. Therefore, in the arithmetic unit ALU1, the window function frequency number BW is added to the phase data PGw2 read from the RAM1. The result of this addition is output as output data # 1 via the output controller 20 at the timing of step S18, which will be described later, after a total of three clock delays by the delay circuits 15, 17, 18, and 19. Note that the output controller 20 outputs the phase data PGw2 from the initial value of the phase data PGw1 by 180 when the performance operator of the electronic musical instrument is turned on.
(If the initial value of PGw1 is "0"), it is initially set to half the maximum phase value, that is, 180 degrees or π, and the pitch frequency phase data PGp2 of the second series
Output controller 2
It is reset to a predetermined initial value by 0.

FIG. 10 shows a development diagram of the arithmetic function corresponding to step S15. The window function frequency number generator 14 (S
14, S15). The window function frequency number generator 14 (S14, S15) corresponds to the log-linear converter / shifter 14 in FIG.
1 and RAM1.

(14) DSP1 in step S16
In step S16, the data #RE stored in the register REG1 is stored in substantially the same manner as in step S13.
Formant frequency number FO output as G1
An operation for creating the second series of center frequency phase data PGf2 by accumulating the RMs is performed using the arithmetic unit ALU1 (FIG. 5). Step S16 is performed in step S16.
The difference from the case of 13 is that the center frequency phase data PGf2 of the second series of the corresponding channel is read out from the RAM 1 and input to the selector 11 as data # RAM1, which is selected by the selector 11. . Therefore, in the arithmetic unit ALU1, the formant frequency number FORM is added to the second series of center frequency phase data PGf2 read from the RAM1. This addition result is delayed by a total of four clocks by each of the delay circuits 15, 17, 18, 19, and 24, and thereafter, a step S20 described later is performed.
At the timing, the data is stored in the storage area of the phase data PGf2 of the RAM 1 via the output controller 20. In this manner, in step S16, the formant frequency number FORM is accumulated for each cycle to create the second series of center frequency phase data PGf2. The phase data PGf2 is stored in the output controller 20 when the key of the performance operator of the electronic musical instrument is turned on.
Is initialized to a predetermined initial value (for example, “0”), and the second series of pitch frequency phase data PGp2
Output controller 2
It is reset to a predetermined initial value by 0. The center frequency phase data PGf2 of the second series created in this way
FIG. 17D shows an example.

FIG. 10 is an exploded view of the arithmetic function corresponding to step S16.
Is shown in the path of the selector SEL1 (S13, S16) subsequent to. This selector SEL1 (S13, S16)
Corresponds to the processing function of the control signal generator 6 (FIG. 3) of the DSP 1, and includes a phase generator ALU1 & RAM1 (S13, S1).
6) corresponds to the arithmetic unit ALU1 and the RAM1 (FIG. 5). By the processing of step S5, the log-linear converter 1
4 (S5), the formant frequency number FORM that has been converted to an exact value is selected by the selector SEL1 in the formant sound synthesis mode and is made available for phase calculation, and is accumulated by the phase generator ALU1 & RAM1 (S16). And the second series of center frequency phase data PGf2
Is created.

(15) DSP1 in step S17
In step S17, one of the window function phase data PGw1 created in the process of step S14 and the pitch frequency phase data PGp1 of the first series is selected as the first series of window function phase data PGw1 to be actually used. Perform the following processing. As shown in FIGS. 9A and 9B, in step S17, the data # 1 is input as the A input of the arithmetic unit ALU1.
Is input, and the first-series pitch frequency phase data PGp1 is set as the B input of the arithmetic unit ALU1.

More specifically, in FIG.
Is given as data # 1 with a delay of three clocks, and the selector 10 is set to select this data # 1. Also, R
A first series of pitch frequency phase data PGp1 of the corresponding channel is read from AM1, and the read output is input to selector 11 as data # RAM1.
This is selected by the selector 11. The log-linear converter / shifter 14 is controlled by the controller 23.
In this example, neither the conversion operation nor the shift operation is performed, and the input data is passed as it is.

Therefore, in the arithmetic unit ALU1, the pitch frequency phase data PGp1 (the arithmetic unit A) is obtained from the window function phase data PGw1 (A input of the arithmetic unit ALU1) obtained in step S14 by accumulating the window function frequency number BW.
(B input of LU1) is subtracted. If this subtraction result is positive (that is, the window function phase data PGw1 obtained by accumulating the window function frequency number BW is larger than the pitch frequency phase data PGp1), the window function obtained in the processing of step S14 is obtained. The phase data PGw1 passes through a delay of a total of four clocks by each of the delay circuits 15, 17, 18, 19, and 24 and the processing of the output controller 20,
When the data is input to the input of the RAM 1 at the timing of the next step S18, this is input to the phase data PGw1 of the RAM 1.
Is controlled to be stored in the storage area. On the other hand, the result of the subtraction is negative or zero (that is, the window function phase data P obtained by accumulating the window function frequency number BW).
Gw1 is equal to or smaller than the pitch frequency phase data PGp1).
The value of Gp1 is stored in the storage area of the phase data PGw1 in the RAM1. In the actual processing, when the pitch frequency phase data PGp1 is stored in the storage area of the phase data PGp1 of the RAM 1 in step S13, the phase data PGp1 is stored in the phase data P
The phase data PGp1 is also stored in the RAM1 as the phase data PGw1 unless the storage of the phase data PGw1 is rewritten according to the positive value of the subtraction result as described above. To be done.

Here, the window function phase data PG input to the RAM 1 through the processing of the output controller 20
An example of w1 is shown in FIG. FIG. 17E shows an example in which the window function phase data PGw1 obtained in step S14 is larger than the pitch frequency phase data PGp1. As described above, when the window function phase data PGw1 obtained in step S14 is larger than the pitch frequency phase data PGp1, the value of the window function phase data PGw1 becomes the maximum value before the value of the pitch frequency phase data PGp1. Reach. In the output controller 20 (FIG. 5),
When the value of the window function phase data PGw1 exceeds a predetermined maximum value, output control is performed so as to hold (slice) the value of the window function phase data PGw1 at the predetermined maximum value. Therefore,
The change waveform of the window function phase data PGw1 is shown in FIG.
As shown in (2), it has an inclined portion and a flat portion. On the other hand, when the window function phase data PGw1 obtained in step S14 is equal to or smaller than the pitch frequency phase data PGp1, the window function phase data PGw1 is
The pitch frequency phase data PGp shown in FIG.
It has the same content as 1.

(16) DSP1 in step S18
In step S18, according to substantially the same procedure as in step S17, the window function phase data PGw2 created in step S15 and the pitch of the second series A process for selecting one of the frequency phase data PGp2 is performed. The processing in step S18 differs from the processing in step S17 in that the window function phase data PGw2 obtained in the processing in step S15 is given to the selector 10 as data # 1 with a delay of three clocks, and is selected. The second series of pitch frequency phase data PGp2 of the corresponding channel is read, and the read output is data #R
AM1 is input to the selector 11 and is selected by the selector 11.

Therefore, as in the case of step S17,
Using the subtraction function of the arithmetic unit ALU1, the window function phase data PGw2 obtained by the accumulation processing in step S15 is compared with the pitch frequency phase data PGp2 of the second series, and the phase data PGw2 obtained by the accumulation processing is compared. Is larger than the data PGp2, this is the next step S1.
At timing 9, the data is written to the storage area of the phase data PGw2 of the RAM 1 (FIG. 9E). Otherwise, the data PGp2 is written to the storage area of the phase data PGw2 of the RAM1.

FIG. 17F shows an example of the window function phase data PGw2 input to the RAM 1 through the processing of the output controller 20. FIG. 17F shows the step S.
This is an example of a case where the window function phase data PGw2 obtained in step 15 is larger than the pitch frequency phase data PGp2. Thus, the window function phase data PGw obtained in step S15
If 2 is larger than the pitch frequency phase data PGp2, the value of the window function phase data PGw2 reaches the maximum value before the value of the pitch frequency phase data PGp2.
As described above, when the value of the window function phase data PGw2 exceeds a predetermined maximum value, the output controller 20 (FIG. 5) holds the value of the window function phase data PGw2 at the predetermined maximum value (slices). ) Output control. Therefore, the change waveform of the window function phase data PGw2 is as shown in FIG.
As shown in (f), it has an inclined portion and a flat portion. On the other hand, if the window function phase data PGw2 obtained in step S15 is equal to or smaller than the pitch frequency phase data PGp2, the window function phase data PGw2
2 has the same content as the pitch frequency phase data PGp2 shown in FIG.

FIG. 10 is a development view of the arithmetic functions corresponding to steps S17 and S18.
7, S18) and selector SEL2 (S17, S18)
The route is shown. The comparator C1 (S17, S
18) corresponds to the subtraction function of the arithmetic unit ALU1, and the selector SEL2 (S17, S18) corresponds to the function of controlling the writing to the RAM1 according to the subtraction result of the arithmetic unit ALU1. Window function phase generator ALU1 & RAM1 (S
14, S15) outputs data from the phase generator AL.
Phase data PG from U1 & RAM1 (S9, S10)
When p1 or PGp2, the selector SEL2 (S17, S1) is selected according to the output of the comparator C1.
8) In window function phase generator ALU1 & RAM1 (S1
4, S15) to the window function phase data PGw1 or P
Gw2, and if not, the selector SEL2 (S17, S1) according to the output of the comparator C1.
8) In phase generator ALU1 & RAM1 (S9, S1
0) output PGp1 or PGp2 to the window function phase data P
Select as Gw1 or PGw2.

By the above processing, the repetition period of the window function waveform created as described later based on the window function phase data PGw1 and PGw2 is always synchronized with the pitch of the musical tone, and the time width of the window is adjusted by the parameter BW (That is, the gradient of the window function phase data PGw1 and PGw2). For details of such a window function phase data creation control method, see, for example, JP-A-3-84.
No. 596, which has already been proposed by the present applicant, can be used. Steps S19 and S20 are
Since it is the step of performing “mixing operation”, DSP4
The operation will be described after the description of the operation.

Note that, in the operation function development diagram of FIG.
As an example of the internal processing function of the modulating unit 12, several circuit elements starting with the reference numeral 12 are shown. Here, the data generators 12a (S0), 12d for each modulation
(S2), pitch frequency number FNUM is obtained by using modulation data such as vibrato generated from 12g (S4).
Adder 12 as arithmetic means for changing / modulating the modulation
c (S0), 12f (S2) and 12i (S4) are used. At this stage, the pitch frequency number FNUM
Since is a real number, it is actually preferable to use a multiplier to perform frequency change control in proportion to the cent value. However, since the amount of frequency change in the modulation section 12 is a small amount at the maximum, there is no adverse effect even if an adder is used as shown in FIG. 10, and the cost is reduced. However, by changing the configuration and the microprogram of the DSP 1 and providing these modulation data such as vibrato as logarithmic values, for example, attack glide data A
If G is added to the pitch frequency number FNUM (multiplication at the antilog level), the frequency change control proportional to the cent value can be performed by multiplication at the antilog level. Of course you can.

-Example of Operation Related to Noise Signal by DSP3- Next, an example of operation of each step of the microprogram related to "noise formant sound synthesis operation" in DSP3 of FIG. 6 will be described with reference to FIG. . FIG.
As in the example of the microprogram operation of the DSP 1 shown in FIG.
It comprises 21 steps from 0 to S20, one step corresponding to one cycle of the system clock. This one cycle also corresponds to the one-channel timing in FIG. 8, and the program cycle for each channel is executed in 18-channel time division as shown in FIG. 11A shows data set to be input to the "A" input of the arithmetic unit ALU3 of FIG. 6, and FIG. 11B shows the state of input to the "B" input of the arithmetic unit ALU3 of FIG. Indicates the data to be set in the
(C) shows the content of data # 3 output from the shifter 39 of FIG. 6, (d) shows the content of data written and input to the register REG3 of FIG. 6, and (e) shows the content of the register AREG of FIG. Indicates the contents of the data to be written and input to
(F) shows the contents of the data input written into the RAM 3 of FIG. FIG. 12 is an arithmetic function development block diagram showing a process of generating a noise signal in the DSP 3 having the hardware configuration shown in FIG.
It is not a diagram showing an actual hardware circuit configuration.

(1) Operation of DSP 3 in Step S0 In Step S0, the DSP 3 controls the spectrum configuration of a low-pass noise signal used to create a correlation noise signal used as a modulation signal for noise formant sound synthesis. The calculation is performed using the arithmetic unit ALU3 (FIG. 6). In other words, the spectral level of the low-pass noise signal is relatively enhanced in the low-frequency part, so that the peak part of the formant in the noise formant sound created by the modulation operation processing using the correlation noise signal based on this low-pass noise signal. This is a process for controlling the sharpness of the image. In FIGS. 11A and 11B, A of the arithmetic unit ALU3
The input data to the input and the B input are shown in a simplified manner. In this step S0, a parameter N for specifying the sharpness of the noise formant is used as the A input of the arithmetic unit ALU3.
The data according to RES is input, and a state is set in which the low-pass noise signal LPF is input as the B input of the arithmetic unit ALU3.

More specifically, in FIG. 6, the selector 30 selects data according to the parameter NRES, and the data is supplied to the arithmetic unit ALU via the delay circuit 33.
3 is input to the A input. Further, the low-pass noise signal LPF is read from the RAM 3 from the storage area of the low-pass noise signal LPF of the corresponding channel, and is input to the selector 31 as output data #RAM 3. In the selector 31, the output data #RAM from the RAM 3
3 is selected and the low-pass noise signal L
Select PF. At this time, data to which a positive sign + is added is given as the sign additional data +/−, and data obtained by adding the positive sign + to the low-pass noise signal is applied to the gate circuit 3.
4 and to the B input of the arithmetic unit ALU3 via the delay circuit 35. The gate circuit 34 is controlled to be opened and closed at the time of serial multiplication, which will be described later. In other cases, the gate circuit 34 is always enabled and passes input data as it is.

Therefore, in the arithmetic unit ALU3, the data according to the parameter NRES is converted to the low-pass noise signal LP.
It is added to F. Note that the low-pass noise signal LP
F is a signal obtained by performing a low-pass filter process on a white noise signal as described later. Adding data according to the parameter NRES to the low-pass noise signal LPF means adding a DC component corresponding to the parameter NRES to the low-pass noise signal LPF.
Low frequency part (DC part of frequency 0)
And the sharpness of the formant envelope of the resulting noise formant sound can be controlled.

As described above, in step S0, the calculation for controlling the low-frequency spectrum of the low-pass noise signal LPF is performed. This calculation result is output to each delay circuit 33,
After a total of two clock delays, the data is written to the register AREG at a timing of step S2 to be described later via the overflow buffer 35, the overflow / underflow controller (OF / UF) 38, and the shifter 39 (FIG. 11).
(E)). The overflow / underflow controller (OF / UF) 38 functions as a limiter in step S0. Further, the shifter 39 does not perform the shift operation in step S0, and passes the input data as it is.

[0133] For reference, the above arithmetic processing is arranged along the arithmetic function development diagram of FIG. Also in FIG. 12, the circuit elements denoted by the same reference numerals as those in FIG. 6 indicate the same elements, and the circuit elements in which the step numbers are written in parentheses as in the arithmetic unit ALU3 (S0) correspond to the step numbers. Indicates that it works in the step where In FIG. 12, the processing in step S0 corresponds to the operation unit A
In LU3 (S0), this is a path for adding coefficient data read from the coefficient table TB1 (S0) according to the parameter NRES to the low-pass noise signal LPF output from the arithmetic unit ALU3 (S5). Arithmetic unit ALU
The calculation result of 3 (S0) is input to the limiter 38 (S0), and a predetermined limiter process is performed. This limiter 3
8 (S0) corresponds to the limiter function of the overflow / underflow controller 38 in FIG.

(2) Operation of DSP 3 in Step S1 In Step S1, in order to control the noise formant bandwidth, the arithmetic unit ALU3 (FIG. 6) is used to calculate the lower limit of the allowable change range of the correlation noise signal. Do it. As shown in FIGS. 11A and 11B, in step S1,
Data according to a parameter NBW specifying a noise bandwidth is input as an A input of the arithmetic unit ALU3, and the arithmetic unit A
A state is set in which the correlation noise signal BWR is input as the B input of LU3.

More specifically, referring to FIG. 6, the selector 30 selects the data according to the parameter NBW, and the data is supplied to the arithmetic unit ALU3 via the delay circuit 33.
Is input to the A input. Further, the correlation noise signal BWR is read from the storage area of the correlation noise signal BWR of the corresponding channel from the RAM 3, and this is output data #
The data is input to the selector 31 as the RAM 3. The selector 31 is set to a state of selecting the output data # RAM3 from the RAM 3, and selects the correlation noise signal BWR. At this time, data to which a negative sign-is added as the sign additional data +/- is given, and the correlation noise signal BWR is given.
Is added to the B input of the arithmetic unit ALU3 via the gate circuit 34 and the delay circuit 35. Therefore, the arithmetic unit ALU3 subtracts the correlation noise signal BWR obtained in the previous cycle from the data according to the parameter NBW. As a result, the difference between the correlation noise signal BWR obtained in the previous cycle and the specified noise bandwidth value NBW is obtained, and the lower limit value of the allowable change range of the correlation noise signal BWR is calculated with a negative sign. The lower limit value of the actual allowable range of the correlation noise signal BWR is a positive sign. However, for the sake of arithmetic processing, in step S1, the difference is first obtained with a negative sign, and then converted to a positive sign. ing.

As described above, in step S1, the calculation for obtaining the lower limit of the allowable change range of the correlation noise signal is performed. This calculation result is output to each of the delay circuits 33, 35, 3
7 and overflow / underflow controller 3
8 and the shifter 39, after a total of two clock delays, the register RE
G3, and the delay circuit 40
The clock is delayed and temporarily stored in the storage area TmpM of the corresponding channel of the RAM 3 at the timing of step S4 described later (see FIGS. 11D and 11F). Also in step S1, the overflow / underflow controller (OF / UF) 38 functions as a limiter, and the shifter 39 passes the input data without performing the shift operation.

In the operation function development diagram of FIG.
1 corresponds to the coefficient table TB2 according to the parameter NRW in the arithmetic unit ALU3 (S1).
The coefficient data read from (S1) is
This is a path to be added to the previous correlation noise signal BWR whose sign has been inverted at NV1 (S1). Arithmetic unit ALU3 (S
The calculation result of 1) is input to the limiter 38 (S1),
A predetermined limiter process is performed. Inverter INV1
(S1) corresponds to the function of adding a negative sign-by sign additional data +/-. In addition, the inverter INV1
The RAM 3 (S20) functioning as a shift register (S / R) on the input side of (S1) stores data #R
AM3 corresponds to the function of supplying the previous correlation noise signal BWR.

(3) Operation of DSP 3 in Step S 2 In Step S 2, the arithmetic unit ALU 3 (FIG. 6) is used to calculate the upper limit of the permissible range of the change of the correlation noise signal in order to control the noise formant bandwidth. Do it. As shown in FIGS. 11A and 11B, in step S2,
As in step S1, data according to the parameter NBW specifying the noise bandwidth is input as the A input of the arithmetic unit ALU3, and the correlation noise signal BWR is set as the B input of the arithmetic unit ALU3. The process of step S2 is different from step S1 in that a process of adding a positive sign + as sign additional data +/− to output data of the selector 31 is performed. As a result, the arithmetic unit ALU3 adds the data according to the parameter NBW to the correlation noise signal BWR obtained in the previous cycle, and calculates the upper limit value of the change allowable range of the correlation noise signal BWR with a plus sign.

In the operation function development diagram of FIG.
2 corresponds to the coefficient table TB2 according to the parameter NRW in the arithmetic unit ALU3 (S2).
This is a path in which the coefficient data read from (S1) is added to the previous correlation noise signal BWR output from the shift register RAM3 (S20), and this is processed by the limiter 38 (S2).

(4) Operation of DSP 3 in Step S3 In Step S3, the low-pass noise signal LPF is obtained by performing a low-pass filter operation on the white noise signal WN in combination with the subsequent Step S5.
Ask for. As shown in FIGS. 11A and 11B, in step S3, the white noise signal WN is input as the A input of the arithmetic unit ALU3, and the low-pass noise signal LPF is input as the B input of the arithmetic unit ALU3. Is set.

More specifically, in FIG. 6, the selector 30 selects the white noise signal WN output from the white noise generator 32, and the signal WN is
The signal is input to the A input of the arithmetic unit ALU3 via the delay circuit 33. Further, the low-pass noise signal LPF is read from the RAM 3 from the storage area of the low-pass noise signal LPF of the corresponding channel, and is input to the selector 31 as output data #RAM 3. In the selector 31,
The output data from the RAM 3 is set to a state of selecting the RAM # 3, and the low-pass noise signal LPF is selected. At this time, data to which a negative sign-is added is given as the sign additional data +/-, and data obtained by adding a negative sign-to the low-pass noise signal is applied to the gate circuit 34 and the delay circuit 35.
Is input to the B input of the arithmetic unit ALU3.

Therefore, the arithmetic unit ALU3 subtracts the low-pass noise signal LPF obtained in the previous sampling cycle from the white noise signal WN. The result of the subtraction is output to each of the delay circuits 33, 35, 37, the overflow / underflow controller 38, and the shifter 39.
After a delay of a total of two clocks, the data is output as data # 3 in step S5. overflow·
The underflow controller (OF / UF) 38 functions as a limiter in step S3. Also, shifter 3
In step S3, a shift-down process is performed on the basis of a parameter NSKT that specifies the spread shape of the noise spectrum. The parameter NSKT corresponds to a low-pass filter coefficient, and this shift-down processing corresponds to coefficient multiplication processing.

In the operation function development diagram of FIG.
3 corresponds to the white noise generator 32.
The white noise signal WN from (S3) is calculated by the arithmetic unit AL.
In U3 (S3), the low-pass noise signal LPF one sample before, which is inverted in sign by the inverter INV2 (S3).
Is the path to be added to The calculation result of the arithmetic unit ALU3 (S3) is input to the limiter 38 (S3), and is subjected to a predetermined limiter process. Further, the inverter INV1 (S
RAM3 (S5) functioning as a shift register (S / R) on the input side of 3) stores data # RAM3
Corresponds to the function of supplying the low-pass noise signal LPF of the previous sample.

(5) Operation of DSP 3 in Step S4 In Step S4, in order to control the bandwidth of the noise formant, an operation for obtaining the permissible change width of the correlation noise signal is performed using the arithmetic unit ALU3 (FIG. 6). . FIG.
As shown in (a) and (b), in step S4, a state is set in which the data # 3 is input as the A input of the arithmetic unit ALU3 and the data # REG3 is input as the B input of the arithmetic unit ALU3.

More specifically, in FIG. 6, the calculation result data of step S2 (upper limit value of the allowable range of change of the correlation noise signal BWR) is input to the selector 30 as data # 3, and this is selected by the selector 30. Delay circuit 33
Is input to the A input of the arithmetic unit ALU3. on the other hand,
The selector 31 receives, as data # REG3, the calculation result data of step S1 (a value obtained by adding a negative sign to the lower limit value of the allowable variation range of the correlation noise signal BWR), and this is selected by the selector 31. The lower limit value of the permissible change range of the correlation noise signal BWR to which the minus sign is added is determined by the BLU of the arithmetic unit ALU3 via the gate circuit 34 and the delay circuit 35.
Entered in the input. Therefore, the arithmetic unit ALU3 subtracts the lower limit absolute value of the allowable change range from the upper limit absolute value of the allowable change range of the correlation noise signal BWR. As a result, an allowable change width between the upper limit value and the lower limit value of the correlation noise signal BWR is obtained.

As described above, in step S4, the calculation for obtaining the allowable change width of the correlation noise signal BWR is performed. After a total of two clock delays by the delay circuits 33, 35, and 37, the operation result is shifted down by one bit by the shifter 39, and written into the register REG3 at the timing of step S6 described later (see FIG. 9D). ). In the operation function development diagram of FIG. 12, the processing corresponding to the processing in step S4 is the operation unit ALU3 (S4).

(6) Operation of DSP 3 in Step S5 As shown in FIGS. 11A and 11B, in Step S5, data # 3 is input as the A input of the arithmetic unit ALU3, and the B input of the arithmetic unit ALU3. Is set in a state where the low-pass noise signal LPF is input. For details, see FIG.
, The selector 30 stores the calculation result data (the input white noise signal W
After the low-pass noise signal LPF of the previous sample is subtracted from N, a value obtained by performing a coefficient operation process according to the parameter NSKT is input thereto, selected by the selector 30, and input to the A input of the arithmetic unit ALU 3 via the delay circuit 33. Is input to On the other hand, the low-pass noise signal LPF of the previous sample read from the storage area of the low-pass noise signal LPF of the channel is input to the selector 31 as the output data # RAM3 from the RAM 3, and this is input to the selector 31.
After a positive sign is added, the signal is input to the B input of the arithmetic unit ALU3 via the AND gate circuit 34 and the delay circuit 35.

Therefore, in the arithmetic unit ALU3, the data subjected to the coefficient arithmetic processing is the low-pass noise signal LPF of the previous sample.
Is added to This addition result is output to each of the delay circuits 33 and 3
5 and 37, the overflow / underflow controller 38, and the shifter 39, after a total of two clock delays, further delayed by one clock in the delay circuit 40, and the low-pass noise signal LPF of the corresponding channel of the RAM 3 in the RAM 3 at the timing of step S8 described later. Is stored in the storage area. Thus, in the combination of the processing of steps S3 and S5,
A low-pass filter operation is performed on the white noise signal WN, and the obtained low-pass filter output, that is, the low-pass noise signal LPF is stored in the RAM 3. In this case, the RAM 3 performs the function of delaying the low-pass noise signal LPF by one sample time, that is, the function of the shift register RAM 3 (S5) in FIG. In the operation function development diagram of FIG. 12, the processing in step S5 corresponds to the operation unit ALU3 (S5) and the shift register RAM3 (S5).
Part.

(7) DS in steps S6 to S17
Operation of P3 In steps S6 to S17, the change allowable width data of the correlation noise signal BWR obtained in step S4 is converted to the data in step S2.
In order to perform scaling by the low-pass noise signal LPF stored in the register AREG (hereinafter, it is assumed that the data is 12-bit data), the process of multiplying the allowable variation width and the low-pass noise signal LPF by a serial operation is performed. Do. As described above, the low-pass noise signal LPF processed in step S0 is stored in the register AREG in step S2, and is stored in the register AREG.
The serial low-pass noise signal SLPF is subjected to parallel / serial conversion in step 7 and serially output from the lower bits sequentially as 12-bit serial low-pass noise signal SLPF for 12 clocks from step 6 to step S17.

First, in step S6, FIG.
As shown in (b), nothing is input to the “A” input of the arithmetic unit ALU3, and a state is set in which the partial product data # REG3 · SLPF is input as the B input of the arithmetic unit ALU3. More specifically, in FIG. 6, the calculation result data of step S4 (that is, data indicating the permissible change width of the correlation noise signal BWR, hereinafter simply referred to as “permissible change width data”) is input to the selector 31 as data # REG3. This is selected by the selector 31, added with a positive sign, and input to the gate circuit 34. A signal indicating the first bit of the serial low-pass noise signal SLPF (the value of the least significant bit of the low-pass noise signal LPF) is supplied to the control input of the gate circuit 34 from the parallel-serial converter 37. Therefore, the gate circuit 34 outputs the SLPF
If the bit of the SLPF is "0", all "0" is output as the partial product output data, and if the bit of the SLPF is "1", the value of data # REG3 is output as it is. As a result, a multiplication for obtaining a partial product of the change allowable width data and the value of the least significant bit of the low-pass noise signal LPF is performed. The result of the multiplication is input to the B input of the arithmetic unit ALU3 via the delay circuit 35.

The arithmetic unit ALU3 functions to add partial products obtained by serial multiplication. In the first two steps, that is, in steps S6 and S7, the arithmetic unit ALU3
No data is input to the A input of the arithmetic unit ALU3.
The partial product data given to the input passes as it is. This is because the partial product data is delayed by a total of two clocks by the delay circuits 35 and 37. Therefore, in this step S6, the partial product data is
3, after a delay of a total of two clocks by each of the delay circuits 35 and 37, the data is shifted down by 2 bits by the shifter 39 via the overflow / underflow controller 38, and the data # 3 is transmitted at the timing of step S8 described later. (See FIG. 11C). After step S8, the data # 3 is selected by the selector 30 and applied to the A input of the arithmetic unit ALU3. The reason why the output of the arithmetic unit ALU3 is shifted down by 2 bits by the shifter 39 is that the output is added to the partial product operation result of 2 bits higher (that is, the B input of the arithmetic unit ALU3), so that the data weight is adjusted.

In the next step S7, the gate circuit 34 multiplies the permissible change width data # REG3 by the data of the second lower bit of the serial low-pass noise signal SLPF. The multiplication result is delayed by two clocks and shifted down by two bits, and is output as data # 3 at step S9 (see FIG. 11C).

In step S8, allowable change width data #R
The multiplication of EG3 and data of the third bit from the lower order of the serial low-pass noise signal SLPF is performed by the gate circuit. From step S8 to step S18,
As shown in FIG. 11A, the output data # of the shifter 39
3 is selected by the selector 30 and given to the A input of the arithmetic unit ALU3. Therefore, the partial product (the A input of the arithmetic unit ALU3) related to the least significant bit of the SLPF and S
Partial product related to the third low-order bit of LPF (arithmetic unit A
And the B input of LU3) are added by an arithmetic unit ALU3 to obtain a partial sum of products. The partial product sum output from the arithmetic unit ALU3 is shifted down by 2 bits by a shifter 39 via an overflow / underflow controller 38 after a delay of a total of 2 clocks by each of the delay circuits 33, 35, and 37, which will be described later. It is output as data # 3 at the timing of step S10 (see FIG. 11C).

In the step S9, the permissible change width data #R
The gate circuit 34 multiplies the EG3 by the fourth bit data from the lower order of the serial low-pass noise signal SLPF. At this time, the data # 3 corresponding to the partial product related to the second bit from the lower order of the SLPF is selected by the selector 30 and supplied to the A input of the arithmetic unit ALU3.
Therefore, the partial product related to the second bit from the lower order of the SLPF (A input of the arithmetic unit ALU3) and the 4th order from the lower order of the SLPF
The partial product relating to the bit (the B input of the arithmetic unit ALU3) is added by the arithmetic unit ALU3 to obtain a partial product sum. The partial sum of products output from the arithmetic unit ALU3 is delayed by an overflow / underflow controller 38 after a total of two clock delays by the delay circuits 33, 35 and 37.
, And is shifted down by 2 bits by the shifter 39, and is output as data # 3 at the timing of step S11 described later (see FIG. 11C).

Hereinafter, steps S10 and S1 are similarly performed.
In steps S2, S14, and S16, partial products related to odd-numbered bits from the lower order of the signal SLPF are sequentially obtained, and the sum of partial products related to the odd-numbered bits obtained so far is calculated. The total sum of the partial products related to the odd-numbered bits obtained by the processing in step S16 is 2
Data # at the timing of step S18 due to clock delay
3 is output from the shifter 39 (see FIG. 11C). Similarly, steps S11, S13, S
In steps S15 and S17, the partial products for the even-numbered bits from the lower order of the signal SLPF are sequentially obtained, and the sum of the partial products for the even-numbered bits obtained so far is obtained. The sum of the partial products related to the even-numbered bits obtained by the processing in step S17 is output from the shifter 39 at the timing of step S19 with a delay of two clocks in total, and is written into the register REG3 (FIG. 11).
(C)).

As described above, the multiplication for scaling the change allowable width data of the correlation noise signal BWR with the randomly changing low pass noise signal LPF is performed by serially multiplying the allowable change width data and the low-pass noise signal LPF. Done. However, in the processing up to step S17, the sum of the partial products regarding the odd-numbered bits and the sum of the partial products regarding the even-numbered bits are separately obtained. Needs to add both. The processing in steps S6 to S17 corresponds to the multiplier ALU3 (S6 to S17) in FIG.

(8) D in steps S18 to S20
Operation of SP3 As shown in FIGS. 11A and 11B, in step S18, data # 3 is input as the A input of the arithmetic unit ALU3, and the temporary storage area data TmpM of the RAM 3 is input as the B input of the arithmetic unit ALU3. It is set to be entered.

More specifically, in FIG. 6, the selector 30 stores, as data # 3, the calculation result of step S16 described above (that is, the sum of partial products related to odd-numbered bits).
Is selected by the selector 30 and input to the A input of the arithmetic unit ALU3 via the delay circuit 33. The RAM 3 also stores a temporary storage area Tm of the channel.
The stored data of pM (that is, the value obtained by adding the minus sign to the lower limit value of the correlation noise signal BWR, which is the calculation result of step S1 and taken into the region TmpM in step S4) is read out and output as data # RAM3. . The selector 31 selects the data # RAM3 read from the RAM3, that is, “a value obtained by adding a negative sign to the lower limit value of the correlation noise signal BWR”. This selector 31
Is output as positive / negative sign data +/−
(That is, the negative sign is inverted to the positive sign), and is input to the B input of the arithmetic unit ALU3 via the gate circuit 34 and the delay circuit 35.

Therefore, in the arithmetic unit ALU3, "the lower limit of the correlation noise signal BWR (with a positive sign)" (B input)
"A part of the values obtained by scaling the allowable variation width data of the correlation noise signal BWR by the low-pass noise signal LPF (sum of partial products related to odd-numbered bits; A input) is added. Is the shifter 39 at the timing of step S20 with a total delay of two clocks.
And input to the selector 30 as data # 3. In the next step S19, as described above, the sum of the partial products related to the even-numbered bits obtained by the processing in step S17 is delayed by a total of two clocks,
9 and written to the register REG3 (see FIG. 11C).

In the next step S20, FIG.
As shown in (b), a state is set in which data # 3 is input as the A input of the arithmetic unit ALU3 and data # REG3 is input as the B input of the arithmetic unit ALU3. That is, in FIG. 6, the selector 30 selects the data # 3, and the calculation result of the step S18 is
Is input to the A input. The selector 31 selects the output data # REG3 of the register REG3, and the sum of the partial products related to the even-numbered bits obtained by the processing in step S17 is input to the B input of the arithmetic unit ALU3. Therefore, in step S20, the arithmetic unit AL
In U3, a part of the value obtained by scaling the allowable variation width data of the correlation noise signal BWR by the low-pass noise signal LPF (the part related to the odd bit) with respect to the “lower limit value of the correlation noise signal BWR (with a positive sign)” For the value (A input) obtained by adding the sum of the products, the remaining value of the value obtained by scaling the allowable variation width data of the correlation noise signal BWR by the low-pass noise signal LPF (sum of the partial products related to the even-numbered bits) B input), and the “value obtained by scaling the allowable variation data of the correlation noise signal BWR by the low-pass noise signal LPF” is added to the “lower limit value of the correlation noise signal BWR”, and the new “correlation noise signal BWR” is added. The noise signal BWR "is obtained.
"Correlation noise signal BW output from arithmetic unit ALU3
R "is the total of 3 by the delay circuits 33, 35, 37, and 40.
At the timing of step S2 for the next channel with a clock delay, the data is written in the storage area of the "correlation noise signal BWR" of the corresponding channel in the RAM 3.

The correlation noise signal BWR created and written in the RAM 3 as described above is read out in the steps S1 and S2 of the DSP 3 for the corresponding channel in the next cycle, and is used for updating. .
Further, the correlation noise signal BWR written in the RAM 3
Is used at a predetermined timing in order to be used in a noise formant sound synthesis operation in another DSP 4.
After being read from the RAM 3 and converted to a logarithmic value by the linear-log converter 42 through the delay circuit 41,
3 and transmitted to the bus DBUS as data # RAM3L and given to the DSP4.

The arithmetic processing of steps S18 to S20 described above is shown in FIG. 12, and the output of adder ALU3 (S4) (that is, the "lower limit value of correlation noise signal BWR (with a negative sign)" is output to inverter INV3 (S18 ) To add a plus sign, add this to the output of the multiplier MULT (S6 to S17) in the arithmetic unit ALU3 (S18, 20), and store it in the RAM3 (S20) functioning as a shift register (S / R). The correlation noise signal BWR read out in the next sampling cycle from the RAM 3 (S20) functioning as a shift register (S / R) is converted into a logarithmic value by the linear-log converter 42. The data is converted and output to the outside (data bus DBUS), and is used inside the DSP 3 for updating its own data.

The noise formant sound synthesizing system in which the skirt portion and the bandwidth of the noise formant can be independently controlled using the noise formant control parameters NRES, NSKT, NBW and the like as described above. For specific examples, see, for example, JP-A-4-3465.
Since the system already disclosed by the present applicant in Japanese Patent Publication No. 02 can be basically used, refer to the same publication as necessary for details of the system itself.

Operation Example Related to Formant Sound Synthesis by DSP4 Next, an operation example of each step of the microprogram of the DSP4 in FIG. 7 will be described with reference to FIG. D
One cycle of the microprogram of SP4 is also step S
It comprises 21 steps from 0 to S20, one step corresponding to one cycle of the system clock. This one cycle also corresponds to the one-channel timing in FIG. 8, and the program cycle for each channel is executed in 18-channel time division as shown in FIG. In FIG. 13, (a) shows data set to be input to the "A" input of the arithmetic unit ALU4 of FIG. 7, and (b) shows data input to the "B" input of the arithmetic unit ALU4 of FIG. Indicates the data to be set in the
(C) shows the content of data # 4 output from the overflow / underflow controller (OF / UF) 56 of FIG. 7, (d) shows the content of data written and input to the register REG4 of FIG. 7, (E) is the RAM of FIG.
4 shows the contents of the data input to be written. FIG.
Waveform synthesis calculation processing in the DSP 4 having the hardware configuration shown in FIG.
1 & RAM1 (only S11, S12, S19, S20 operate in the DSP1) is an arithmetic function development block diagram, and like FIG. 10 and FIG. 12, is not a diagram showing an actual hardware circuit configuration.

(1) Operation of DSP 4 in Step S0 In step S0, one process of an operation for creating a periodic function waveform is performed in order to generate a first formant formant sound waveform. As shown in FIGS. 13A and 13B, in step S0, the center frequency phase data PGf1 of the first series is input as an A input of the arithmetic unit ALU4, and the arithmetic unit ALU4 is input.
Nothing is input to the B input of No. 4.

More specifically, the center frequency phase data PGf1 of the first series of the channel is read out from the RAM1 of the DSP 1 at a predetermined timing, and the read data PGf1 is used as the data # RAM1 and is read from the DSP1 of FIG. Sent to the bus DBUS and the data bus DBU
The signal is input to the DSP 4 of FIG. 7 via S and input to the rhythm sound generator 52. According to the rhythm sound generation on / off parameter RHY, the rhythm sound generator 52 disturbs and outputs the phase data PGf1 in a mode in which a rhythm sound (that is, percussion instrument sound) is generated. The data PGf1 is output as it is without disturbing the phase. Phase data PGf controlled by the rhythm sound generator 52
1 is input to the selector 50. In the process of step S0, the selector 50 is set to a state of selecting the output data of the rhythm sound generator 52. On the other hand, the selector 51 does not select any data.

Therefore, the center frequency phase data PGf1 of the first series, which is controlled so as to disturb or not disturb the phase in accordance with the rhythm sound generation on / off parameter RHY, passes through the arithmetic unit ALU4 via the delay circuit 53 as it is. Via a circuit 55 and an overflow / underflow controller 56 and then to the wave shape shifter 6
0, a delay circuit 61, a log sin table 62, and a delay circuit 63, and are provided to the “β” input side of the selector 64. That is, in response to the processing in step S0, the selector 64 selects the “β” input. Therefore, the phase data PGf1 calculated as described above in step S0 and passed through the overflow / underflow controller (OF / UF) 56 is processed as described above.
Is processed in a path leading to the “β” input of the selector 64 via the wave shape shifter 60, the delay circuit 61, the log sin table 62, and the delay circuit 63, and is selected and output by the selector 64.

In the wave shape shifter 60, the phase data P is set according to the basic waveform selection designation parameter WF1.
A phase operation process of shifting the phase value of Gf1 or setting the phase value to zero only in a specific section is performed. As a result, the change characteristic of the time-to-phase value of the phase data PGf1 is changed drastically, and the basic waveform shape of the waveform data read from the log sin table 62 is changed to a simple sine wave based on the changed phase data as described later. To complex waveforms. In other words, if the phase data simply changes linearly with time, a simple sine wave will be read, but if a special change such as intermittent change is shown, a special time-lapse waveform will be read. Become. Log si
In the n-table 62, the phase data processed by the wave shape shifter 60 is input, and the logarithmic sine waveform amplitude value data corresponding to the phase value is read out. Thus, the periodic function waveform data corresponding to the phase data of the formant center frequency is output as a logarithmic value. Selector 6
The waveform data of the logarithmic value output from 4 passes through the shift / log-linear converter 65 as it is, and after a delay of a total of 4 clocks by each of the delay circuits 53, 55, 61, 63, a step S4 to be described later is performed. At the timing, the data is written to the register REG4 (see FIG. 13D).

In FIG. 14, the operation function development diagram corresponding to step S0 is shown in a path starting from noise applicator 52 (S0, S10).
0, S10) corresponds to the rhythm sound generator 52 (FIG. 7),
The arithmetic unit ALU4 (S0, S10) corresponds to the arithmetic unit ALU4 (FIG. 7), and the shift linear-log sin converter 60
& 62 (S0, S10) is the wave shape shifter 60
And the log sin table 62 (FIG. 7).
The center frequency phase data PGf1 from the DSP 1 is supplied to the noise applicator 52 (S0, S10) according to the parameter RHY.
After the control of disturbing / not disturbing the phase with
It passes through U4 (S0, S10) as it is, and is shifted by a shift linear-log sin converter 60 & 62 (S0, S10).
The above processing according to the parameter WF1 is performed, and finally, sin waveform data in logarithmic expression is read according to the controlled phase data PGf1.

(2) Operation of DSP 4 in Step S2 Since the operation in Step S1 is a continuation of the operation from the immediately preceding channel, the operation will be described after the operation in Step S20. In step S2, an operation for creating a window function waveform is performed to generate the first formant waveform. FIG. 13 (a),
As shown in (b), in step S2, the arithmetic unit ALU
4 as the A input of the first window function waveform phase data PG
w1 is input, and nothing is input to the B input of the arithmetic unit ALU4.

More specifically, the first-series window function waveform phase data PGw1 of the channel is read from the RAM1 of the DSP 1 at a predetermined timing, and the data PGw1 is used as the data # RAM1 from the DSP1 of FIG. The data is transmitted to the DSP 4 shown in FIG. In this case, the rhythm sound generation on / off parameter RHY is off, and the window function waveform phase data PGw1
Is input to the selector 50 without any change by the rhythm sound generator 52. The selector 50 is set to select the data # RAM1, that is, the data PGw1. On the other hand, the selector 51 does not select any data. Therefore, the window function waveform phase data PGw
1 passes through the arithmetic unit ALU4 as it is via the delay circuit 53, passes through the delay circuit 55 and the overflow / underflow controller (OF / UF) 56, and then passes through the wave shape shifter 60, the delay circuit 61, and the log si.
selector 6 via the n-table 62 and the delay circuit 63
4 at the “β” input.

That is, the selector 64 selects the “β” input corresponding to the processing in step S2. Therefore, the phase data PGw1 is output from the selector 64 via the wave shape shifter 60, the delay circuit 61, the log sin table 62, and the delay circuit 63. In the process corresponding to step S2, the wave shape shifter 60 outputs 1 of the window function waveform phase data PGw1.
In order to output the first half of the sine waveform (that is, half wave) as a window function waveform from the log sin table 62 in correspondence with the cycle, the window function waveform phase data P
The phase value of Gw1 is shifted down by one bit. Log si
In the n-table 62, the logarithmic value of the sine waveform amplitude value corresponding to the phase value of the shifted window function waveform phase data PGw1 is read. In this manner, the window function waveform data of the first series is obtained as a logarithmic value.

On the other hand, the skirt characteristic designating parameter SKT of the formant is shifted up by one bit by the controller 66 and input to the shift / log-linear converter 65. As described above, 1 output from the selector 64
Logarithmic data "log sin (PG
w1) ”is input to the shift / log-linear converter 65, and is shifted up by one bit from the skirt characteristic designation parameter SKT (that is, 2 × SKT).
It is shifted up by 2 × SKT bits. That is,
“(2 × SKT) · log sin (PGw1)”
This can be expressed as an exact number by 2 × SK of sin (PGw1).
It means that it is converted to a T-th power waveform. This means
Window function waveform sin read as half wave of sine waveform
This means that (PGw1) is converted into a 2n-th power waveform, and is converted into a window function waveform having a wide tail (skirt). 2 × SKT of sine wave obtained in this way
The logarithmic expression data of the window function waveform consisting of the half-wave of the power is
After a total of four clock delays by the delay circuits 53, 55, 61, 63, the data is written to the register REG4 at the timing of step S6 described later (FIG. 13D).
reference). In this step S2, the shift / log-
The linear converter 65 functions as a shifter as described above, and does not function as a log-linear converter.

The operation function development diagram corresponding to step S2 is shown in FIG. 14 along a path starting from the operation unit ALU4 (S2, S12).
12) corresponds to the arithmetic unit ALU4 in FIG. 7, and the shift linear-log sin-square converter 60 & 62 (S2, S12)
Correspond to the wave shape shifter 60 and the log sin table 62 in FIG. 7, and the shifter 65 (S2, S12) corresponds to the shift / log-linear converter 65. DSP1
Frequency data PGf1 from the arithmetic unit ALU
4 (S2, S12) as it is, and is shifted down by one bit in the shift linear-log sin-square converters 60 & 62 (S2, S12) and converted into a logarithmic value of a sin waveform, and then is shifted according to the data of the parameter SKT. 6
At 5 (S2, S12), a predetermined bit shift is performed.

(3) Operation of DSP 4 in Step S5 In step S5, an operation for controlling the volume level of the periodic function waveform data corresponding to the first formant center frequency is executed. As shown in FIGS. 13A and 13B,
In step S5, the volume level data LVL1 is input as the A input of the arithmetic unit ALU4,
A state is set in which data # REG4 is input as an input.

More specifically, the volume level data LVL1 of the logarithmic expression of the channel is read from the RAM 2 of the DSP 2 at a predetermined timing (as described above, this data LV).
The data LVL1 is sent to the data bus DBUS, is taken into the DSP 4 of FIG. 7 via the data bus DBUS, and is input to the selector 50 as data # RAM2. In step S5, the selector 50 is set to select the data # RAM2, that is, the volume level data LVL1. On the other hand, the center frequency phase data PGf1 of the first series
The logarithmic value data of the periodic function waveform obtained in step S0 based on
After being taken into EG4, the register RE is stored in step S5.
G4 is output as data # REG4, and the selector 51 is set to select this data # REG4.

Therefore, the logarithmic value of the periodic function waveform of the formant center frequency and the volume level data LVL1
Is added by the arithmetic unit ALU4. As a result, at a true level, a process of adding a volume envelope to the periodic function waveform by multiplying by the volume level data LVL1 is performed. This calculation result is output to each delay circuit 5
After a total of two clock delays of 3, 54 and 55, the data # 4 is passed through the overflow / underflow controller 56 at the timing of step S6 described later.
(See FIG. 13C). Step S5
FIG. 14 is a development diagram of the arithmetic function corresponding to the shift linear-log sin square converters 60 & 62 (S0, S1).
The logarithmic value of the periodic function waveform from 0) and the logarithmic volume level data LVL1 from the DSP 2 are calculated by the arithmetic unit ALU4.
This is shown in the path added in (S5, S15).

(4) Operation of DSP 4 in Step S7 In step S7, the above-mentioned volume function-controlled periodic function waveform corresponding to the formant center frequency and the window corresponding to the pitch correspond to the center frequency of the formant in order to generate the first series of formant sound waveforms. Performs an operation to multiply the function waveform. FIG.
As shown in (a) and (b), in step S7, a state is set in which the data # 4 is input as the A input of the arithmetic unit ALU4 and the data # REG4 is input as the B input of the arithmetic unit ALU4.

More specifically, the logarithmic value data of the periodic function waveform corresponding to the formant center frequency subjected to the volume envelope control processed in step S5 is output as data # 4 in step S7 with a delay of two clocks, and Then, the state is set in which this data # 4 is selected. On the other hand, window function waveform phase data PGw1 of the first series
The logarithmic value data of the window function waveform obtained in step S2 based on
After being fetched by G4, the register REG is added to step S7.
4 is output as data # REG4, and the selector 51 is set to select this data # REG4. Therefore, the logarithmic value of the periodic function waveform and the logarithmic value of the window function waveform are added by the arithmetic unit ALU4. As a result, at the true level, the amplitude modulation arithmetic processing for synthesizing the first series of formant sound waveform signals is performed by multiplying the periodic function waveform corresponding to the formant tall frequency and the window function waveform corresponding to the pitch. It will be.

In response to the processing in step S7, the selector 64 selects the "α" input. Therefore, the output data (logarithmic value) of the arithmetic unit ALU4, which is the result of the amplitude modulation operation, passes through the delay circuit 55 and the overflow / underflow controller 56, and then passes through the delay circuit 5
The signal is converted into an exact number by a log-linear converter 58 through 7, and output from a selector 64 through a delay circuit 59. The antilog data output from the selector 64 as the result of the amplitude modulation operation passes through the shift / log-linear converter 65 as it is, and is input to the RAM 4 via the delay circuit 67.
Therefore, the real number data as the result of the amplitude modulation operation, that is, the waveform data of the synthesized first formant sound is
After a delay of a total of 5 clocks by each of the delay circuits 53, 54, 55, 57, 59, 67, a step S described later is performed.
At timing 12, the data is written to the storage area of the first formant waveform data TR1 of the first channel of the channel in the RAM 4 (see FIG. 13E).

An example of the periodic waveform of the first series based on the formant center frequency phase data PGf1 of the first series is as shown in FIG. 18A, which is based on the window function waveform phase data PGw1 of the first series. FIG. 18C shows an example of the window function waveform of the first series, and FIG. 18E shows an example of the formant sound waveform of the first series generated by multiplying the window function waveforms. Become like The pitch of the first series of formant sound waveforms is （of the regular pitch (f0) according to the pitch frequency number data (twice in the cycle). In the window function waveforms of FIGS. 18C and 18D, the level 0 section between the window waveforms is shown in FIG.
7 (e) and 7 (f) correspond to the flat part of the maximum phase value in the phase data PGw1 and PGw2.

The operation function development diagram corresponding to step S7 is shown in the path starting from operation unit ALU4 (S7, S17) in FIG. 14, and is shown in operation unit ALU4 (S7, S17).
17) corresponds to the arithmetic unit ALU4 in FIG.
(S7, S17) correspond to the overflow / underflow controller 56 of FIG.
8 (S7, S17) corresponds to the log-linear converter 58 in FIG. 7, and the register RAM 4 (S7) corresponds to the RAM 4 in FIG. The gate G1 indicates that the path is enabled only in the formant sound synthesis mode. The logarithmic value of the periodic function waveform from the arithmetic unit ALU4 (S5, S15) and the logarithmic value of the window function waveform given from the shifter 65 (S2, S12) via the gate G1 in the formant sound synthesis mode are: Arithmetic unit ALU4 (S
7, S17) and then added to the limiter 56 (S7, S17).
17), the log-linear converter 58 (S7, S1)
In 7), the data is converted into an antilog number and recorded in the register RAM 4 (S7).

(5) Operation of DSP 4 in Step S10 In Step S10, as in Step S0, one process of calculation for creating a periodic function waveform is performed to generate a second series of formant sound waveforms. The difference from step S0 is that the center frequency phase data PGf2 of the second series of the channel is read from the RAM1 (FIG. 5) of the DSP 1, and the data PGf2 is passed as the data # RAM1 via the rhythm sound generator 52 to the selector 50. Is the point selected by The center frequency phase data PGf of the second series
2, the delay circuit 53, the arithmetic unit ALU4, the delay circuit 55, the overflow controller 56, the wave shape shifter 60, the delay circuit 61, the log sin table 62, the delay circuit 63,
Processing is performed in the same manner as described above via the selector 64 and the shift / log-linear converter 65 (however, in the wave shape shifter 60, the phase operation processing according to the basic waveform selection designation parameter WF2 for the second series is performed). Applied). Then, after a total of four clock delays, the data is written to the register REG4 at the timing of step S14 described later (see FIG. 13D). FIG. 14 is a development view of the arithmetic function corresponding to step S10.
It is shown on the path starting from (S0, S10).

(6) Operation of DSP 4 in Step S12 In Step S12, as in Step S2, an operation for creating a window function waveform is performed to generate a second formant waveform. The difference from step S2 is that the window function waveform phase data PGw2 of the second series of the channel is read from the RAM 1 (FIG. 5) of the DSP 1, and the data PGw2 is selected by the selector 50 via the rhythm sound generator 52. It is a point. This second series of window function waveform phase data PGw2 is also used as the first series of data P
Similarly to Gw1, the delay circuit 53, the arithmetic unit ALU4, the delay circuit 55, the overflow controller 56, the wave shape shifter 60, the delay circuit 61, the log sin table 62, the delay circuit 63, the selector 64, the shift / log-
After a delay of a total of four clocks via the linear converter 65, the data is written to the register REG4 at the timing of step S16 described later (see FIG. 13D). In FIG. 14, the arithmetic function development diagram corresponding to step S12 is shown in a path starting from the above-described noise imparting device 52 (S2, S12).

(7) Operation of DSP 4 in Step S13 In step S13, an operation for creating a periodic function waveform corresponding to the center frequency of the unvoiced formant sound is performed. As shown in FIGS. 13A and 13B, in step S13, the central frequency phase data PGu of the unvoiced formant sound is input as the A input of the arithmetic unit ALU4, and the arithmetic unit AL
Nothing is set to the B input of U4.

More specifically, the phase data PGu of the channel is read from the RAM 1 of the DSP 1 at a predetermined timing, and the phase data PGu is sent to the data bus DBUS as the data #RAM 1 (FIG. 5). This data # RAM1, that is, PGu is transferred from the data bus DBUS to DS
The signal is taken into P4 (FIG. 7), passes through the rhythm sound generator 52 as it is, and is input to the selector 50. Selector 50
Then, the data # RAM1, that is, PGu is set to be selected. On the other hand, the selector 51 does not select any data. Therefore, the center frequency phase data PGu of the unvoiced formant sound passes through the arithmetic unit ALU4 as it is via the delay circuit 53, passes through the delay circuit 55 and the overflow / underflow controller 56,
Then, a wave shape shifter 60, a delay circuit 61,
The signal is supplied to the “β” input side of the selector 64 via the log sin table 62 and the delay circuit 63.

That is, in response to the processing in step S13, the selector 64 selects the "β" input.
Accordingly, the phase data PGf1 calculated as described above by the processing in step S13 and passed through the overflow / underflow controller 56 is supplied to the wave shape shifter 60, the delay circuit 61, and the log sin.
A selector 64 via a table 62 and a delay circuit 63
, And is selected by the selector 64 and output. Thus, the logarithmic value data of the periodic function waveform corresponding to the center frequency phase data PGu of the unvoiced formant sound is read from the log sin table 62. The logarithmic value data output from the selector 64 passes through the shift / log-linear converter 65 as it is, and after a delay of a total of four clocks by each of the delay circuits 53, 55, 61, 63, the timing of step S17 described later Is written to the register REG4 (see FIG. 13D).

The operation function development diagram corresponding to step S13 is shown in the path of the log sin table 62 (S13) in FIG. 14, and according to the value of the phase data PGu given from the DSP 1, S1
In step 3), logarithmic value data of the sin waveform is read. still,
Among the parameters provided from the microcomputer COM (FIG. 1), the formant follow-up control flag URVF
Is "1", a mode in which the formant frequency FORM is used without using the unvoiced formant frequency UFORM as the center frequency for noise formant sound synthesis is instructed. In this case, the control signal generation unit 6 of the DSP 4 supplies the formant follow-up control flag U
If RVF is “1”, the center frequency phase data read from the RAM 1 of the DSP 1 for the processing in step S13 is not the center frequency phase data PGu of the unvoiced formant sound, but the center frequency phase data PGf1 of the formant sound or Read PGf2. Therefore, when the formant following control flag URVF is “1”, in this step S13, the periodic function waveform data corresponding to the center frequency for unvoiced formant sound synthesis is created according to the center frequency phase data PGf1 or PGf2 of the formant sound. Perform the operation to be performed.

(8) Operation of DSP 4 in Step S15 In Step S15, as in Step S5, an operation for controlling the volume level of the periodic function waveform data corresponding to the second formant center frequency is executed. FIG.
As shown in (a) and (b), in step S15, the volume level data LVL2 is input as the A input of the arithmetic unit ALU4.
Is input, and data #R is input as the B input of the arithmetic unit ALU4.
The state is set such that EG4 is input.

More specifically, at a predetermined timing, the volume level data LVL2 of the logarithmic expression of the channel is read from the RAM 2 of the DSP 2 (as described above, this data LV).
The data LVL2 is transmitted to the data bus DBUS, is taken into the DSP 4 of FIG. 7 via the data bus DBUS, and is input to the selector 50 as data # RAM2. In step S15, the selector 50 is set to select the data # RAM2, that is, the volume level data LVL2. On the other hand, the center frequency phase data PGf2 of the second series
, The logarithmic value data of the periodic function waveform obtained in step S10 is fetched into the register REG4 in step S14 with a delay of 4 clocks, and then output as data # REG4 from the register REG4 in step S15. A state is set in which this data # REG4 is selected.

Therefore, the logarithmic value of the periodic function waveform of the second formant center frequency and the volume level data LVL2 are added by the arithmetic unit ALU4. As a result, at the true number level, a process of adding a volume envelope to the periodic function waveform by multiplying by the volume level data LVL2 is performed. The result of this operation is, after a total of two clock delays by the delay circuits 53, 54, 55, the overflow / underflow controller
6 and is output as data # 4 at the timing of step S17 described later (see FIG. 13C). An operation function development diagram corresponding to step S15 is shown in step S5.
Similarly to the above, it corresponds to the path passing through the arithmetic unit ALU4 (S5, S15) in FIG.

(9) Operation of DSP 4 in Step S16 In step S16, a calculation for controlling the volume level of the correlation noise signal BWR is performed. As shown in FIGS. 13A and 13B, in step S16, A of the arithmetic unit ALU4
The noise volume level data LVLu is input as an input, and the correlation noise signal B is input as the B input of the arithmetic unit ALU4.
WR is set to be input.

More specifically, logarithmic volume level data LVLu of the channel is read from the RAM 2 of the DSP 2 at a predetermined timing, and the data LVVLu is transmitted to the data bus DBUS. The data is taken into the DSP 4 and input to the selector 50 as data # RAM2. In step S16, the selector 50 is set to a state where the data # RAM2, that is, the noise volume level data LVLu is selected.
On the other hand, the correlation noise signal BWR of the channel is read from the RAM 3 of the DSP 3 at a predetermined timing, is converted into a logarithmic value by the linear-log converter 42 (FIG. 6), and is appropriately delayed by the delay circuit 43 (FIG. 6). After that, the data is sent to the data bus DBUS as data # RAM3L, taken into the DSP 4 of FIG. 7 via the data bus DBUS, and input to the selector 51. In step S16,
The selector 51 is set to select the data # RAM3L, that is, the correlation noise signal BWR of the channel.

Thus, the arithmetic unit ALU4 adds the volume level data LV to the correlation noise signal BWR expressed in logarithmic form.
Add Lu. This is because at the true level, the correlation noise signal B is multiplied by the volume level data LVLu.
This means that a process of giving a volume envelope to WR has been performed. The output of the arithmetic unit ALU4 is delayed by one clock by the delay circuit 55, passes through the overflow controller 56, and is input to the selector 50 as data # 4 in step S18 as shown in FIG. The operation function development diagram corresponding to step S16 is shown in FIG.
The correlation noise signal BWR from P3 and the volume level data LVLu from DSP2 are shown in the path calculated by the arithmetic unit ALU4 (S16).

(10) DSP4 in step S17
In step S17, in the same manner as in step S7, the volume function-controlled periodic function waveform corresponding to the formant center frequency and the window function waveform corresponding to the pitch corresponding to the formant center frequency are used to generate the second formant waveform. Perform the multiplication operation. As shown in FIGS. 13A and 13B, in step S17, a state is set in which data # 4 is input as the A input of the arithmetic unit ALU4 and data # REG4 is input as the B input of the arithmetic unit ALU4. You.

More specifically, the logarithmic value data of the periodic function waveform corresponding to the formant center frequency for which the volume envelope control for the second series processed in step S15 is performed is as follows:
The data is output as data # 4 in step S17 two clocks later, and is selected by the selector 50. Also, based on the window function waveform phase data PGw2 of the second series, step S1
After the logarithmic value data of the window function waveform obtained in step 2 is fetched into the register REG4 in step S16 with a delay of 4 clocks, the data #R is read from the register REG4 in step S17.
The signal is output as EG4 and is selected by the selector 51. Therefore, the logarithmic value of the periodic function waveform and the logarithmic value of the window function waveform for the second series are added by the arithmetic unit ALU4. As a result, at the true number level, an amplitude modulation operation for synthesizing the second series of formant waveform data is performed by multiplying the periodic function waveform corresponding to the formant tall frequency by the window function waveform corresponding to the pitch. .

In response to the processing in step S17, the selector 64 selects the “α” input. Therefore,
The output data (logarithmic value) of the arithmetic unit ALU4, which is the result of the amplitude modulation operation, passes through the delay circuit 55 and the overflow / underflow controller 56, and then passes through the delay circuit 5
The signal is converted into an exact number by a log-linear converter 58 through 7, and output from a selector 64 through a delay circuit 59. The output of the selector 64 passes through the shift / log-linear converter 65 as it is, and after a delay of a total of four clocks, the register RE is output at the timing of step S0 of the next channel.
G4 is written (see FIG. 13D).

An example of the periodic waveform of the second series based on the formant center frequency phase data PGf2 of the second series is as shown in FIG. 18B, which is based on the window function waveform phase data PGw2 of the second series. FIG. 18D shows an example of the window function waveform of the second series, and FIG. 18F shows an example of the formant sound waveform of the second series generated by multiplying the window function waveforms. Become like The pitch of this formant sound waveform is also half (two times in period) the pitch (1 / f0) according to the pitch frequency number data. The operation function development diagram corresponding to step S17 is the same as step S7, and FIG.
This is shown in the path starting from (S7, S17).

(11) DSP4 in step S18
In step S18, an operation of multiplying the periodic function waveform corresponding to the center frequency and the above-mentioned correlation noise signal BWR subjected to the volume envelope control to generate a noise formant sound waveform is executed. As shown in FIGS. 13A and 13B, in step S18, a state is set in which data # 4 is input as the A input of the arithmetic unit ALU4 and data # REG4 is input as the B input of the arithmetic unit ALU4. You.

More specifically, the logarithmic value data of the correlation noise signal BWR processed in step S16 is output as data # 4 in step S18 with a delay of two clocks, and the selector 50 is set to select this data # 4. Is done. On the other hand, the logarithmic value data of the periodic function waveform corresponding to the center frequency for noise synthesis obtained in step S13 is 4
After being fetched into the register REG4 in step S17 with a delay of the clock, the data is output from the register REG4 as data # REG4 in step S18 and the selector 51
In this state, a state is set in which this data # REG4 is selected. Accordingly, the logarithmic value data of the periodic function waveform corresponding to the center frequency for noise synthesis and the correlation noise signal BW
The logarithmic value data of R is added by the arithmetic unit ALU4. As a result, at the level of the antilogarithm, a process of obtaining a signal obtained by amplitude-modulating the periodic function waveform with the correlation noise signal BWR is performed by multiplying the periodic function waveform corresponding to the center frequency by the correlation noise signal BWR. become. Thus, the noise formant sound is synthesized.

In response to the processing in step S18, the selector 64 selects the "α" input. Therefore,
The output data (logarithmic value) of the arithmetic unit ALU4, which is the result of the amplitude modulation operation, passes through a delay circuit 55 and an overflow / underflow controller 56 functioning as a limiter, and then passes through a delay circuit 57 to the log-linear converter 5.
8 and is converted to an antilog by a delay circuit 59.
Output from The output of the selector 64 passes through the shift / log-linear converter 65 as it is, and is input to the RAM 4 through the delay circuit 67. After a total of 5 clock delays, at the timing of step S2 of the next channel, The data is written in the storage area of the noise formant waveform data TRu of the corresponding channel in the RAM 4 (FIG. 13).
(E)).

The development diagram of the arithmetic function corresponding to step S18 is shown in FIG. 14 along a path passing through arithmetic unit ALU4 (S18), and arithmetic unit ALU4 (S18) corresponds to arithmetic unit ALU4 in FIG. FIG. 7 shows the limiter 56 (S18).
7 corresponds to the overflow / underflow controller 56, the linear-log converter 58 (S18) corresponds to the linear-log converter 58 in FIG.
18) corresponds to the RAM 4 in FIG. Selector SE
L1 corresponds to a function of selecting a periodic function waveform corresponding to the center frequency according to the value of the formant follow-up control flag URVF. That is, if the flag URVF is “0”, the periodic function waveform data corresponding to the unvoiced formant frequency phase data PGu from the path of the log sin table 62 (S13) is selected, and the arithmetic unit ALU4 (S1
8), when the flag URVF is "1", the shift linear-log sin converters 60 & 62 (S0, S1)
0) Formant frequency phase data PGf from the path
The periodic function waveform data corresponding to 1 or PGf2 is selected and given to the arithmetic unit ALU4 (S18).

(12) DSP4 in step S20
In step S20, step S20 for the next channel is performed.
By a combination with the processing of the first step, an operation of adding the first formant waveform and the second formant waveform to generate final formant waveform data is executed. As shown in FIGS. 13A and 13B, in step S20, nothing is set to the A input of the arithmetic unit ALU4, and the first-series waveform data TR1 is input as the B input of the arithmetic unit ALU4. Is entered.

More specifically, the waveform data TR1 (that is, the first series of formant sound waveform data) of the channel is read from the RAM 4 at a predetermined timing, and the data TR1 is transferred to the data # RAM4 via the delay circuit 68.
Is input to the selector 51. In the selector 51,
This data # RAM4 is set to be selected. No data is selected by the selector 50. Therefore, the formant sound waveform data TR1 of the first series
Passes through the arithmetic unit ALU4 as it is via the delay circuit 54. This data TR1 is output as data # 4 at the timing of step S1 of the next channel via the overflow / underflow controller 56 after a delay of a total of two clocks by each of the delay circuits 54 and 55 (FIG. c)).

(13) Operation of DSP 4 in Step S1 of Next Channel As shown in FIGS. 13 (a) and 13 (b), in step S1, data # 4 is input as an A input of the arithmetic unit ALU4, and A state is set in which data # REG4 is input as the B input of ALU4.

More specifically, step S20 of the previous channel
Is read out as data # 4 in step S1 with a delay of two clocks, and the selector 50 is set to select this data # 4. On the other hand, the second formant waveform data obtained in step S17 of the previous channel is taken into the register REG4 in step S0 with a delay of 4 clocks (FIG. 13 (d)), and in the next step S1, the data is output from the register REG4. #RE
The data is output as G4, and the selector 51 is set to select this data # REG4. Therefore, 1
The formant sound waveform data of the series and the formant sound waveform data of the second series are added by the arithmetic unit ALU4.
This produces a final formant sound waveform.

In response to the process in step S1, the selector 64 selects the "γ" input, the overflow / underflow controller 56 functions as a limiter, and the shift / log-linear converter 65 It is set to pass through as it is. Accordingly, the finally synthesized formant sound waveform data output from the arithmetic unit ALU4 passes through the delay circuit 55, the overflow / underflow controller 56 and the selector 64, and passes through the shift / log-linear converter 65 as it is. , After a total of three clock delays, at the timing of step S4, the waveform data TR
2 (see FIG. 13E).

FIG. 18 (g) shows an example of a combined formant sound waveform obtained by finally adding the formant sound waveforms of two series. As shown in the figure, the first and second formant sound waveforms each having a frequency of 1 / 2f0 and synthesized by modulation with a window function waveform that is substantially alternately shifted by 180 degrees (FIG. 18). (E), (f))
Are added and synthesized, a synthesized formant sound waveform having a pitch corresponding to the regular pitch (1 / f0) according to the pitch frequency number data is obtained. This synthesized formant sound waveform is stored in the storage area of the RAM 4 for the waveform data TR2.

As a modified example of the processing in steps S20 and S1, the formant sound waveform data of the first series and the formant sound waveform data of the second series are added without adding
Only the formant waveform data of the series may be written to the storage area of the RAM 4 for the waveform data TR2. In this case, the first series of formant waveform data is stored in the storage area of the waveform data TR1 in the RAM 4, and the second series of formant waveform data is stored in the storage area of the waveform data TR2.

FIG. 14 is a development diagram of arithmetic functions corresponding to steps S20 and S1.
(S17, S20, S1), the first series of formant waveform data and the second series of formant waveform data from the log-linear converter 58 (S7, S17) are stored in the register ALU4 & RAM4 ( S17,
S20, S1) are added and held. The path of the register ALU4 & RAM4 (S17, S20, S1) corresponds to the processing of the ALU4 and the RAM4 in FIG.

-Operation Example of Formant Sound Mixing Operation by DSP1-Next, returning to FIGS. 5 and 9, an operation example of "mixing operation" of the DSP1 will be described. (1) Operation of DSP 1 in Step S11 In Step S11, a calculation is performed to sum the combined formant sound waveform data of each channel for the left speaker of the sound system SS. FIG. 13 (a),
As shown in (b), in step S11, a state is set in which the waveform data TR2 is input as the A input of the arithmetic unit ALU1 and the data MIXL is input as the B input of the arithmetic unit ALU1 in FIG.

More specifically, the waveform data TR of the corresponding channel is read from the RAM 4 (FIG. 7) of the DSP 4 at a predetermined timing.
2 (final formant sound waveform data obtained by adding the first and second formant sound waveform data) is read out, and the data TR2 is given to the DSP 1 via the data bus DBUS, The data is input to the selector 10 as the data # RAM4 in FIG. The selector 10 is set to select this data. Further, the left level control data read from the PAN table 21 in accordance with the parameter PAN for specifying the panning of the formant sound is given to the controller 23 via the selector 22. The waveform data TR2 output from the selector 10 is shifted by the log-linear converter / shifter 14 under the control of the controller 23 according to the left level control data corresponding to the parameter PAN (that is, the level is changed according to the left level control data). ), And is input to the “A” input of the arithmetic unit ALU1 via the delay circuit 15.

On the other hand, the left musical tone mixed data MIXL is read out from the RAM 1 of the DSP 1, and the data MIXL is input to the selector 11 of FIG. 5 as the data #RAM 1 and is selected by the selector 11. This data MIXL
Passes through the log-linear conversion / shift / ± encoder 16 as it is, and passes through the delay circuit 17 to “B” of the arithmetic unit ALU1.
Entered in the input. Accordingly, the synthesized formant waveform data TR2 of the channel and the left musical tone mixed data MIX whose level is controlled in accordance with the left level control data.
L is added by the arithmetic unit ALU1. The result of this addition is
The total of 4 by each of the delay circuits 15, 17, 18, 19, and 24
After the clock delay, at the timing of step S15 in FIG.
(FIG. 9 (e)). In this way, the sample values of the synthesized formant sound waveform data of the respective channels that have been left-level controlled for panning are sequentially summed up by the processing of step S11 in FIG. Stored in the storage area.

(2) Operation of DSP 1 in Step S12 In Step S12, as in Step S11, an operation of summing the combined formant sound waveform data of each channel for the right speaker of the sound system SS is executed. The difference from step S11 is that P is determined according to a parameter PAN that specifies panning of the formant sound.
Read the right level control data from the AN table 21,
And giving it to the controller 23 via the selector 22. The point is that the right musical tone mixed data MIXR is read from the RAM 1 as the data #RAM 1 and the data MIXR is selected by the selector 11. Therefore, the combined formant sound waveform data TR2 whose level is controlled in accordance with the right level control data and the right musical tone mixed data MIXR are added by the arithmetic unit ALU1. This addition result is stored in the storage area of the right tone mixed data MIXR in the RAM 1 via the output controller 20 at the timing of step S16 after a total of four clock delays by the delay circuits 15, 17, 18, 19, and 24. (FIG. 9E).
In this way, step S1 of FIG.
By the process of 2, the sample values of the synthesized formant sound waveform data of the respective channels whose right level is controlled for panning are sequentially summed up and stored in the storage area of the right musical tone mixed data MIXR in the RAM 1.

(3) Operation of DSP 1 in step S19 In step S19, the left level control is performed on the noise formant waveform data of each channel, and the total level for the left speaker of the sound system SS is calculated in the same manner as in step S11. Execute the operation to be performed. Step S11
The difference is that the noise waveform data (noise formant sound waveform data) TRu of the channel is read from the RAM 4 of the DSP 4 and supplied to the DSP 1 via the data bus DBUS, and the data TRu is selected by the selector 10. And PAN table 21 according to parameter uPAN specifying panning of unvoiced formant sound.
Is read out from the left side, and is supplied to the controller 23 via the selector 22. Further, the left musical tone mixed data MIXL written in the RAM 1 in step S15 is read out and input to the selector 11 as data # RAM1. Therefore,
The arithmetic unit ALU1 adds the noise waveform data TRu left-level controlled in accordance with the parameter uPAN and the left musical tone mixed data MIXL. The result of this addition is delayed by a total of four clocks by the delay circuits 15, 17, 18, 19, and 24, and then at the timing of step S3 for the next channel, via the output controller 20 and the RAM 1
(FIG. 9 (e)).

(4) Operation of DSP 1 in Step S20 In Step S20, right level control is performed on the noise formant sound waveform data of each channel as in Step S19, and the sound system SS is controlled in the same manner as in Step S12. Perform the summing operation for the right speaker. The difference from step S19 is that the right musical tone mixed data MIXR is read from the RAM 1 and the data MI
XR is selected by the selector 11. Therefore, the waveform data TRu of which the right level is controlled in accordance with the parameter uPAN and the right musical tone mixed data MIXR are calculated by the arithmetic unit AL.
It is added at U1. This addition result is output to each delay circuit 15,
After a total of four clock delays due to 17, 18, 19, and 24, at the timing of step S4 for the next channel,
It is stored in the storage area of the right musical tone mixed data MIXR of the RAM 1 via the output controller 20 (FIG. 9).
(E)).

The values of the left musical tone mixed data MIXL and the right musical tone mixed data MIXR are the same as those of the formant sound waveform data and noise waveform data of all channels.
Each time the total accumulation of sample data values is completed, they are updated. In the above description, it has been described that the combined formant waveform data obtained by adding the first and second series of formant waveform data is stored in the storage area of the waveform data TR2 in the RAM 4. Only the formant sound waveform data of the second series is stored in RAM4
Is stored in the storage area of the waveform data TR2 of the waveform data TR1, the waveform data TR2, and the waveform data TRu.
It is only necessary to control the level for bread for each of the three, and then sum them up.

Steps S11, S12, S19,
The arithmetic function development diagram corresponding to S20 is the digital mixer 14 & ALU1 & RAM1 (S11, S1
2, S19, S20). The selector SEL2 shown in FIG.
7, S20, S1), that is, the function of selectively reading out the waveform data TR2 stored in the RAM 4 of the DSP 4 and sending it out to the DSP 1 for the mixing process.

As described above, DSP1, DSP2,
Based on the cooperation of the DSP3 and DSP4, musical sound waveform data (mixed data of left and right musical sounds MIXL, MIXR) is created by the formant sound synthesizing method, and the RAM of the DSP1 is created.
1 is stored. The tone waveform data (MIXL, MIXR) created in this manner is transmitted to the DSP at a predetermined timing.
1 and is sent to the DA converter DAC via the data bus DBUS and the interface DIF.

-Example of Operation of DSP 1 Related to FM Synthesis- Next, an example of operation in the case of performing a musical tone waveform synthesis operation by the FM synthesis method based on the cooperation of the DSPs 1 to 4 will be described. Note that the DSP 2 and the DSP 3 execute a common microprogram in the above-described formant sound synthesis method and the FM synthesis method, and therefore, description of the operation examples thereof will be omitted. In the following example, two calculation elements are used as waveform calculation elements for FM (frequency modulation), and each calculation element is assigned to an operator OP1.
And OP2. For example, in one FM calculation algorithm, a modulated wave signal is generated by an operator OP1, and the operator OP2 performs phase modulation of a carrier signal by the modulated wave signal, that is, frequency modulation calculation, and generation calculation of a modulated waveform signal based on the result. Do. Therefore, for convenience of explanation, a waveform generated by the operator OP1 is hereinafter referred to as a modulated wave, and a waveform generated by the operator OP2 is referred to as a carrier wave. However, note that the meaning of this word is not strict. That is, another FM
In the calculation algorithm, neither operator output may modulate the phase of the waveform generated by another operator, and in another FM calculation algorithm, the phase of its own may be modulated by the output waveform data of a certain operator. There is also. In some cases, the operator OP
The phase of the waveform generated by the operator OP1 may be modulated by the output waveform of No. 2. Generally, the DSP 1 performs the phase data generation calculation of the operators OP1 and OP2, and the DSP 4 performs the modulation wave waveform generation based on the generated phase data in the operators OP1 and OP2, the phase modulation calculation of the carrier wave, and the waveform generation calculation based on the modulated phase data. Perform processing. The FM operation algorithm to be executed is
It is designated by the tone synthesis algorithm parameter ALG described above. For example, if the value of the parameter ALG is "0"
In other cases, it is instructed that the tone synthesis operation should be performed in the FM synthesis mode, and a predetermined FM operation algorithm is selected according to the ALG value "1" or "2" at that time. In the example described below, each FM operation algorithm can be realized by using a common FM synthesis microprogram, and after that, data used for processing in some predetermined steps is selectively selected. Each FM operation algorithm can be realized only by performing the change processing.

FIG. 15 shows an operation example for each step of the microprogram in the DSP 1 when performing tone synthesis based on the FM synthesis method. As in the example of FIG. And "mixing operation". Therefore, in order to understand the operation example of FIG. 15, the operation example of FIG. 9 for the formant sound synthesizing method which has already been described in detail can be referred to, and a duplicate description will be omitted. FIG. 10 is a development view of the arithmetic function of the processing executed by the DSP 1 based on the program of FIG.
Correspond to those shown in the above. However, since the step numbers in parentheses at the end of the numbers of the respective circuit function elements in FIG. 10 correspond to the program in FIG.
Please note that it does not always correspond to the steps in FIG.

In FIG. 15, steps S0, S3, S
In step 6, a change control process of the pitch frequency number FNUM is performed, and a frequency number for the first operator OP1 for FM, that is, a modulated wave frequency number is created. In step S9, progressive phase data (that is, modulated wave phase data) PGf1 of the operator OP1 is created by accumulating the frequency number of the operator OP1 obtained in steps S0 to S6. In steps S2, S5 and S8, the pitch frequency number FNU
A frequency number changing process based on M is performed to create a frequency number for the second operator OP2 for FM, that is, a carrier frequency number. And step S
In step 16, the operator OP obtained in steps S2 to S8
By performing an accumulating operation of the frequency number of 2, the progressive phase data (that is, carrier phase data) PGf2 of the operator OP2 is created. For convenience of explanation, the phase data P in each of the operators OP1 and OP2 is used.
Gf1 and PGf2 use the same signs as the center frequency phase data PGf1 and PGf2 in the above-described formant sound synthesis processing, but have completely different contents.

The processing procedure of the “phase calculation” step other than the above-described steps in FIG. 15 is substantially the same as the same step in FIG. However, since the result is not used in the FM synthesis operation, there is no problem),
Further, the processing procedure of the “mixing calculation” step is substantially the same as the same step in FIG. So, below,
The processing in steps S0, S3, S6 and the processing in step S9 based on the processing results, and the processing in steps S2, S5, S6
8 and the processing of step S16 based on the processing result will be particularly described.

(1) Operation of DSP 1 in Steps S0, S3, S6 In FIG. 15, in steps S0, S3, S6, FIG.
The change control processing of the pitch frequency number FNUM is performed in exactly the same procedure as in steps S0, S3, and S6. However, even though the processing procedure is the same, since the specific contents of the parameters used in the processing are completely different between FM synthesis and formant sound synthesis, the data created as a result is completely different. Needless to say.
That is, in steps S0, S3, and S6 in FIG. 15, by performing exactly the same processing procedure as steps S0, S3, and S6 in FIG. 9, the frequency number is changed based on the pitch frequency number FNUM. As the pitch frequency number, a frequency number for the operator OP1, that is, a modulated wave frequency number is generated. First, in step S0, a process of changing and controlling the pitch frequency number FNUM indicating the pitch of the musical tone to be generated in accordance with the attack glide data AG is performed. In this case, as described above, the channel synchronization operation flag RBP
"Channel synchronization operation" processing is also performed according to the content of the pitch frequency number FNUM.
Mn or FNUMn-1 is used).

In the next step S3, similarly to FIG. 9, the process of converting the logarithmic value of the change-controlled pitch frequency number FNUM into an exact value is performed by the log-linear converter / shifter 1.
4 (FIG. 5). This conversion result is obtained in step S6.
Is output from the output controller 20 (FIG. 5) and is taken into the register REG1. Register R
The data captured by EG1 is output without time delay and input to selectors 10 and 11 as data # REG1. In this way, in step S6, the pitch frequency number FNUM converted into an exact value by the processing in step S3 is used as selector # 1 as data # REG1.
0 and 11 which are respectively selected and output to arithmetic unit A
It is given to the A and B inputs of LU1. On the other hand, in step S6, the frequency multiple parameter MULT1 for the FM modulation wave is given to the controller 23 via the selector 22, and the log-linear converter / shifter 14 and the log-linear converter 14 are controlled by the controller 23 based on the parameter. The conversion / shift / ± unit 16 performs a shift operation for a predetermined number of digits and an inversion operation of the sign. This is because, as described above, an operation of an arbitrary multiple other than 2 n times (for example, 3 times, 5 times, 6 times, 7 times, etc.) is performed.

In this manner, frequency number data consisting of a frequency obtained by multiplying the pitch frequency of a musical tone by a desired multiple set by the parameter MULT1 is generated as a modulated wave frequency number. The modulated wave frequency number data changed to the desired multiple of the pitch frequency in step S6 is subjected to a total of three clock delays by the delay circuits 15, 17, 18, and 19, and then to step S9 described later.
Is written to the register REG1 via the output controller 20 at the timing shown in FIG. Step S0, S
3 and S6 are performed by the vibrato data generator 12a (S0) shown in FIG.
This corresponds to the path leading to (S6).

(2) Operation of DSP 1 in Step S9 As shown in FIGS. 15A and 15B, in Step S9, the data # REG1 is input as the A input of the arithmetic unit ALU1, and the B input of the arithmetic unit ALU1 is input. As the current value of the modulated wave phase data PGf1 (ie, the accumulated result up to the previous time)
Is set to be input.

More specifically, in FIG. 5, the modulated wave frequency number data obtained in the processing of step S6 is stored in the register REG1 in this step S9 with a delay of three clocks (see FIG. 15D), and the data # It is immediately output from the register REG1 as REG1. The selector 10 selects the data # REG1. The data # REG1 passes through the log-linear converter / shifter 14 as it is, and is input to the A input of the arithmetic unit ALU1 via the delay circuit 15. On the other hand, the current value of the modulated wave phase data PGf1 of the channel (that is, the accumulated result up to the previous time) is read from the RAM 1 and input to the selector 11 as data # RAM1. The selector 11 is set to a state in which this data is selected. The data # RAM1 passes through the log-linear conversion / shift / ± unit 16 as it is, and is input to the B input of the arithmetic unit ALU1 via the delay circuit 17.

Therefore, in the arithmetic unit ALU1, the modulation wave frequency number is added to the current value of the modulation wave phase data PGf1, and the value of the modulation wave phase data PGf1 is increased by the value of the modulation wave frequency number. The result of this addition is
The total of 4 by each of the delay circuits 15, 17, 18, 19, and 24
After the delay of the clock, at the timing of step S13 to be described later, the RAM
1 is stored in the storage area of the modulated wave phase data PGf1 of the channel. The arithmetic processing corresponding to this step S9 is performed by the arithmetic unit ALU1 (S6) shown in FIG.
13, S16) on the path leading to the phase data PGf1.
Is generated. The selector SEL
1 is an arithmetic unit ALU1 (S6) in the FM synthesis mode.
Of the phase generator ALU1 & RAM1 (S1
3, S16) shows a selection function to be accumulated.

(3) Operation of DSP 1 in Steps S2, S5, and S8 In FIG. 15, in steps S2, S5, and S8, the same processing procedure as steps S0, S3, and S6 is used.
A change control process of the pitch frequency number FNUM is performed.
However, even if the processing procedure is the same, since the specific contents of the parameters used for the processing are different, the data created as a result is different. That is, in steps S2, S5, and S8 of FIG.
By performing exactly the same processing procedure as above, the frequency number is changed based on the pitch frequency number FNUM, but as the changed pitch frequency number,
A frequency number for the operator OP2, that is, a carrier frequency number is generated.

In the processing of steps S2 and S5, the pitch frequency number FNUM indicating the pitch of the musical tone to be generated is changed and controlled in accordance with the attack glide data AG, as in steps S0 and S3. In step S8, as in step S6, the pitch frequency number FNUM converted into an exact value by the processing in step S5 is the data #R
EG1 is input to the selectors 10 and 11, which are respectively selected and applied to the A input and the B input of the arithmetic unit ALU1. On the other hand, in step S8, the frequency multiple parameter MULT2 for the FM carrier is supplied to the controller 23 via the selector 22, and the log-linear conversion / shifter 14 and the log-linear conversion are controlled by the controller 23 based on the parameter. / Shift / ± 1
In step 6, a shift operation for a predetermined number of digits and an inversion operation of the sign are performed. This is because, as described above, an operation of an arbitrary multiple other than 2 n is performed.

In this way, frequency number data consisting of a frequency obtained by multiplying the pitch frequency of a musical tone by a desired multiple set by the parameter MULT2 is generated as a carrier frequency number. The carrier frequency number data changed to the desired multiple of the pitch frequency in step S8 is output by the output controller at the timing of step S11 after a total of three clock delays by the delay circuits 15, 17, 18, and 19. The data is written into the register REG1 through the step 20 (see FIG. 15D). The arithmetic processing corresponding to steps S2, S5, and S8 also corresponds to the path from the vibrato data generator 12a (S0) to the arithmetic unit ALU1 (S6) in FIG.

(4) Operation of DSP 1 in Step S16 As shown in FIGS. 15A and 15B, in Step S16, the data # REG1 is input as the A input of the arithmetic unit ALU1, and the B input of the arithmetic unit ALU1 is input. As the current value of the carrier phase data PGf2 (ie, the accumulated result up to the previous time)
Is set to be input. Specifically, in FIG. 5, the carrier frequency number data taken into the register REG1 in the step S11 is the data # REG1
Is output from the register REG 1 and is input to the selector 10. In the process corresponding to step S16, the selector 10 is set to select this data # REG1. The data # REG1 passes through the log-linear converter / shifter 14 as it is, and is input to the A input of the arithmetic unit ALU1 via the delay circuit 15. Meanwhile, RA
From M1, the carrier phase data PGf2 of the corresponding channel
Is read out (that is, the accumulation result up to the previous time) and input to the selector 11 as data # RAM1.
Selected by the selector 11. The carrier phase data PGf2 output from the selector 11 is log-linear converted /
The signal passes through the shift / ± unit 16 as it is, and is input to the B input of the arithmetic unit ALU1 via the delay circuit 17.

Accordingly, in the arithmetic unit ALU1, the carrier frequency number is added to the current value of the carrier phase data PGf2, and the value of the carrier phase data PGf2 is increased by the value of the carrier frequency number. The result of this addition is
The total of 4 by each of the delay circuits 15, 17, 18, 19, and 24
After the delay of the clock, at the timing of step S20 to be described later, the RAM
1 is stored in the storage area of the carrier phase data PGf2 of the channel. The arithmetic processing corresponding to this step S16 is performed by the arithmetic unit ALU1 (S6) in FIG.
In the path leading to (S13, S16), the phase data PG
It corresponds to the part that generates f2.

(5) DSP in steps S4 and S7
Operation of Steps S4 and S7 in FIG.
Are performed in the same way as the corresponding steps in the above, and a process of creating the phase data PGu corresponding to the center frequency for the noise formant sound is performed. Even in the FM synthesis mode, noise formant sound synthesis, that is, noise waveform data TRu
Can be synthesized. The noise phase data PGu obtained in step S7 is R
The data is stored in the storage area of the data PGu of the AM1, and is used for the noise formant sound synthesis by the processing of the DSP 4 as described above. The arithmetic processing corresponding to steps S4 and S7 is performed by the modulation data generator 12g in FIG.
It corresponds to the path from (S4) to the phase generator ALU1 & RAM1 (S7).

(6) Steps S11, S12, S19,
Operation of DSP 1 in S20 Steps S11, S12, S19, S2 in FIG.
0 is basically the same as the corresponding step in FIG. 9, and the left and right level control data according to the panning parameters PAN and uPAN are stored in the waveform data TR1 and T1 in the RAM 1 for each channel.
R2 and TRu are multiplied, the level-controlled waveform data is summed for all channels, and the left and right tone mixed data
XL, MIXR are obtained. These steps S11, S1
The "mixing operation" process in steps S2, S19, and S20 is performed in the same manner as described above.
9, S20).

(7) Operations of Other Steps Steps S10, S13 to S15, S17, S in FIG.
The processing operation of the arithmetic unit ALU1 at 18 is basically the same as the corresponding step in FIG. 9, and is generally involved in the arithmetic processing of the phase data PGp1, PGp2, PGw1, PGw2. However, in FM synthesis, these phase data are not used at all, so it is meaningless processing. For the sake of simplicity of program creation, the program only partially overlaps with the formant sound synthesis program. Therefore, a program in which the operation contents of these steps are completely omitted may be used. Note that the point that the result of step S13 is stored in the storage area of the data PGp1 in the RAM 1 in step S17 in FIG. 15 is different from the process in step S17 in FIG. This is because, in the FM synthesis, the arithmetic processing of the arithmetic unit ALU1 in step S13 is meaningless, so that the arithmetic result is written in the storage area of the data PGf1 in the same manner as in the processing of step S17 in FIG. In this case, the correct modulated wave phase data PGf1 written in the storage area of the data PGf1 of the RAM1 in the RAM writing process in the above will be damaged.
The data is written to the storage area of the data PGp1 of AM1. In other words, in the step which does not substantially affect the FM synthesis processing with or without the presence, a part of the program of the formant sound synthesis processing is left.
Even in such a step, some processing that may affect the FM synthesis processing is replaced with another meaningless processing.

-Example of Operation Related to FM Synthesis by DSP4-FIG. 16 shows an example of the operation of each step of the microprogram in the DSP4 when performing tone synthesis based on the FM synthesis method. Like the example in
The DSP 4 performs a process for “waveform generation calculation”. Therefore, in order to understand the operation example of FIG. 16, the operation example of FIG. 13 for the formant sound synthesizing method already described in detail can be referred to, and a duplicate description will be omitted.
The operation function development diagram of the processing executed by the DSP 4 based on the program of FIG. 16 corresponds to that shown in FIG. However, the step numbers given in parentheses at the end of the numbers of the respective circuit function elements in FIG.
Since it corresponds to the program of FIG.
It does not always correspond to step 6. However, in FIG. 14, portions corresponding to only the steps for FM synthesis shown in FIG. 16 are denoted by "FM" along with the step numbers, which correspond to the steps in FIG. .

Referring to FIG. 16, steps S0, S4, S
5, S9, S11 and S14 mainly use the operator OP1.
Performs the generation processing of the waveform data including the self-feedback FM operation in. Steps S10, S14, S15,
In S19, S20, S1, and S4, mainly the operator OP
2 for generating FM synthesized waveform data including the FM operation. Steps S13, S16, S18, S
In step 2, similarly to FIG. 13, a process of creating noise formant sound waveform data is performed. Note that the self-feedback FM
The calculation is, as is well known, to perform a calculation of modulating the input phase data by feeding back the waveform data generated in response to the input of a certain phase data to the phase input side. In this embodiment, the operator OP1 can perform a self-feedback FM operation.

(1) DSP in steps S0 and S4
Operation 4 In step S0, a waveform data generation process of the operator OP1 is performed. As shown in FIGS. 16A and 16B, in step S0, OP1 is input as the A input of the arithmetic unit ALU4.
(Modulated wave) phase data PGf1
A state is set in which feedback waveform data FR is input as B input of LU4. Specifically, the phase data PGf1 of the operator OP1 for the channel is read from the RAM1 (FIG. 5) of the DSP1 at a predetermined timing, and is read as the data # RAM1 on the data bus D.
The signal is supplied to the DSP 4 of FIG. 7 via the BUS, passes through the rhythm sound generator 52 of FIG. 7, and is input to the selector 50 to be selected. On the other hand, the feedback waveform data FR of the channel is read from the RAM 4 of FIG. 7, and the data FR is input to the selector 51 as the data #RAM 4 and selected. The RAM 4 has a storage area for storing the waveform data generated by the operator OP1 as feedback waveform data FR for use in the self-feedback FM calculation. Usually, FM
In the synthesis mode, the rhythm sound generator 52 is not used, and the data provided as the data # RAM1 passes through the selector 50 without any change. Thus, in the arithmetic unit ALU4, the feedback waveform data FR is added to the phase data PGf1 of OP1. This allows
The phase data PGf1 for generating the waveform of the operator OP1 is self-feedback modulated by its own generated waveform.

In response to the processing in step S0, the selector 64 in FIG. 7 selects the β input. Therefore, after the operation result data of the arithmetic unit ALU4 passes through the delay circuit 55 and the overflow / underflow controller 56, the wave shape shifter 60, the delay circuit 61,
The data is output from the selector 64 via the log sin table 62 and the delay circuit 63. The wave shape shifter 60 performs a phase value conversion process in a specific phase section in the same manner as described above according to the parameter WF1. However, the parameter WF1 supplied at this time is the FM synthesis operator O
It is prepared for P1. In the log sin table 62, the logarithmic value of si represents the OP1 phase data PGf1 that has been subjected to the self-feedback modulation as described above and subjected to the phase value conversion processing as necessary.
Read n waveform data. Thus, by the processing in step S0, the self-feedback FM calculation and the waveform data generation processing in the operator OP1 are performed.

The operator OP1 waveform data (for example, modulated wave waveform data) composed of the logarithmic expression selected via the β input of the selector 64 passes through the shift / log-linear converter 65 as it is, and the delay circuits 53 , 55,6
Step S after a total of 4 clock delays by 1,63
At timing 4, the data is written to the register REG4 (see FIG. 16D). Of course, depending on the FM calculation algorithm to be realized, there is a case where the operator OP1 does not perform the self-feedback FM. In that case,
In the step S0, control is performed so that the feedback waveform data FR is not read from the RAM 4 or the selector 51 does not select any input data. As a result, the arithmetic unit ALU4 outputs the phase data PGf1 of OP1 without change, and the waveform data that is not subjected to the self-feedback FM is read from the log sin table 62.

(2) Operation of DSP 4 in Step S5 In step S5, an operation for controlling the amplitude level of the waveform data of the operator OP1 is performed. FIG. 16 (a), (b)
As shown in (5), in step S5, A
A state is set in which amplitude level data LVL1 is input as an input, and data # REG4 is input as a B input of arithmetic unit ALU4. More specifically, logarithmic amplitude level data LVL1 for setting the amplitude level of the operator OP1 for the channel is read from the RAM2 of the DSP2, and the data LVL1 is given to the DSP4 via the data bus DBUS as data # RAM2. It is input to the selector 50 of FIG. The selector 50 selects the data # RAM2, that is, LVL1. on the other hand,
The logarithmic value data of the waveform data of the operator OP1 fetched into the register REG4 in the step S4 is output as data # REG4 from the register REG4 and selected by the selector 51. Therefore, the logarithmic OP
1 and the amplitude level data LVL1 are
At the true level, the processing is performed by multiplying the amplitude level data LVL1 by the waveform data of OP1. The amplitude level data LVL1 is composed of time-varying envelope data.
When the waveform data generated from P1 is modulated wave waveform data, it functions as an amplitude control coefficient of a modulated wave signal, that is, a modulation index.

According to the processing in step S5, FIG.
The selector 64 selects the α input. Therefore,
The operation result of the arithmetic unit ALU4 via the delay circuit 55 and the overflow / underflow controller 56 is
The signal is supplied to a log-linear converter 58 via a delay circuit 57, is converted into an exact number, and is output from a selector 64 via a delay circuit 59. The waveform data of OP1 whose amplitude level has been controlled and is outputted from the selector 64 and whose amplitude level has been controlled, is delayed by a total of four clocks by the delay circuits 53, 55, 57 and 59, and then shifted by the shift / log-linear converter 65. And is written into the register REG4 at the timing of step S9 described later (see FIG. 16D).
At the same time, the data is stored in the storage area of the waveform data TR1 of the OP1 of the corresponding channel in the RAM 4 at the timing of step S10 further delayed by one clock through the delay circuit 67 (see FIG. 16E). The waveform data TR1 stored in the predetermined storage area of the RAM 4 at the timing of step S10 corresponds to the waveform data generated and output by the operator OP1 of the channel.

(3) Operation of DSP 4 in Steps S9, S11, and S14 In these steps S9, S11, and S14, the operator OP1 performs self-feedback level control.
Hunting (or oscillation) by self-feedback
Perform processing to prevent the phenomenon. First, step S9
Then, the waveform data TR1 (corresponding to the waveform data generated in the previous sampling cycle) of the operator OP1 of the channel stored in a predetermined storage area of the RAM 4 is read and input to the selector 51 as data # RAM4. Selected. No data is selected by the selector 50. Therefore, the waveform data TR1 of OP1 generated in the previous sampling cycle
Passes through the arithmetic unit ALU4 as it is via the delay circuit 54, passes through the delay circuit 55 and the overflow / underflow controller 56, and is output as data # 4 at the timing of step S11 after a total of two clock delays. (See FIG. 16 (c)).

In step S11, the waveform data TR1 of OP1 generated in the previous sampling cycle and output as the data # 4 is input to the selector 50.
Selected. Further, the waveform data TR1 of OP1 generated in the current sampling cycle and stored in the register REG4 by the processing of step S9 is the data #REG.
4 is input to the selector 51 and is selected. As a result, the waveform data T1 of the OP1 generated in the previous and current two sampling cycles for the channel is obtained.
R1 is added by the arithmetic unit ALU4. As described above, the OPs generated in the previous and current two sampling cycles
The reason why one waveform data TR1 is added is to prevent a hunting (or oscillation) phenomenon due to self-feedback.

In response to the processing in step S11,
In FIG. 7, the selector 64 selects the γ input, and the controller 66 generates a feedback level control coefficient in accordance with the feedback level designation parameter FBL. The shift / log-linear converter 65 responds to the feedback level control coefficient. The input data is shifted down by an amount, and a 1-bit shift-down process is further performed for an averaging operation (1/2 operation) accompanying the above-described addition processing for preventing the hunting phenomenon. Therefore,
The calculation result of the arithmetic unit ALU4 is output from the selector 64 as it is via the delay circuit 55 and the overflow / underflow controller 56, and the averaging calculation and the feedback level control calculation are performed by the shift / log-linear converter 65 by the shift-down processing. Will be applied. shift/
The output of the log-linear converter 65 is input to the RAM 4 via the delay circuit 67, and the delay circuits 53, 54, 5
Step S after a total of 3 clock delays by 5,67
At the timing of 14, the feedback waveform data FR of the corresponding channel is stored in the storage area of the RAM 4 (see FIG. 16E).

The above steps S0, S4, S5, S9,
In the generation processing of the waveform data TR1 and the feedback waveform data FR in the operator OP1 by the processing of S11 and S14, in the operation function development diagram of FIG. Through the register RAM4 (S
7) and a path until the feedback level controller and the register 65 & RAM 4 (S9FM, S11FM) perform feedback level control and store as the feedback waveform data FR. . In this case, the selector SEL2 is a feedback level controller and a register 65 & RAM4 (S9F
M, S11FM), that is, the feedback waveform data FR is read from the RAM 4 and the adder ALU4 (S0, S1
0).

(4) Operation of DSP 4 in Step S10 In step S10, waveform data generation processing of the operator OP2 is performed. As shown in FIGS. 16 (a) and (b),
In step S10, O is input as A input of the arithmetic unit ALU4.
A state is set in which the phase data PGf2 (carrier phase data) of P2 is input, and the waveform data TR1 (modulated waveform data) of OP1 is input as the B input of the arithmetic unit ALU4. Specifically, the RA of the DSP 1 is
The phase data PGf2 of the operator OP2 for the channel is read from M1 (FIG. 5), and this is given to the DSP 4 of FIG. 7 as the data # RAM1 via the data bus DBUS, and the rhythm sound generator 52 of FIG.
And is input to the selector 50 and selected. On the other hand, the waveform data TR1 of the OP1 of the channel is read from the RAM 4 in FIG.
The data is input to the selector 51 as the RAM 4 and is selected.
Therefore, in the arithmetic unit ALU4, the phase data PG of OP2 is obtained.
f2 (carrier phase data) contains the waveform data TR1 of OP1
(Modulated wave waveform data) are added, and a frequency modulation operation is performed.

In response to the processing in step S10, the selector 64 in FIG. 7 selects the β input. Therefore, after the operation result data of the arithmetic unit ALU4 passes through the delay circuit 55 and the overflow / underflow controller 56, the wave shape shifter 60 and the delay circuit 6
1, output from the selector 64 via the log sin table 62 and the delay circuit 63. Wave Shape Shifter 6
At 0, a phase value conversion process in a specific phase section is performed according to the parameter WF2, as described above. However, the parameter WF2 supplied at this time is prepared for the FM combining operator OP2. In the log sin table 62, sin waveform data expressed by logarithmic values is read according to the phase data PGf2 for OP2 that has been frequency-modulated as described above and has undergone phase value conversion processing as necessary. Thus, by the processing of step S10, the FM calculation in the operator OP2 and the generation processing of the waveform data synthesized by the FM based on this are performed.

The waveform data (that is, the FM synthesized waveform data) of the operator OP2 composed of the logarithmic expression selected via the β input of the selector 64 passes through the shift / log-linear converter 65 as it is, and Circuit 5
At the timing of step S14 after a total of four clock delays of 3, 55, 61, and 63, the data is written to the register REG4 (see FIG. 16D). Of course, depending on the FM operation algorithm to be realized, the operator O
In some cases, the FM operation is not performed in P2. In this case, in step S10, control is performed such that the waveform data TR1 is not read from the RAM 4 or the selector 51 does not select any input data.
Thereby, the arithmetic unit ALU4 outputs the phase data P of the OP2.
Gf2 is output without change, and waveform data that is not subjected to FM synthesis is read from the log sin table 62.

(5) Operation of DSP 4 in Step S15 In Step S15, an operation for controlling the amplitude level of the waveform data generated by the operator OP2 is performed in the same manner as in Step S5. The processing procedure in step S15 is almost the same as step S5. However, in step S15, logarithmic amplitude level data LVL2 for setting the amplitude level of the operator OP2 for the channel is read from the RAM 2 of the DSP 2 and the data #RAM
2 is selected by the selector 50 and A of the arithmetic unit ALU4
Input to the register REG in step S14.
4, the logarithmic value data of the generated waveform data of the operator OP2 is selected as the data # REG4 by the selector 51 and supplied to the B input of the arithmetic unit ALU4. Therefore, the generated waveform data of OP2 expressed by logarithmic expression (FM synthesized waveform data) and the amplitude level data LVL2 are added by the arithmetic unit ALU4. Will be performed. The amplitude level data LVL2 is composed of envelope data that changes over time, and functions as volume level setting data for setting the output volume level of waveform data generated from the operator OP2.

In response to the processing of step S15, the selector 64 in FIG.
The data obtained by converting the calculation result of No. 4 into an exact number by the log-linear converter 58 is selected and output by the selector 64. Generated waveform data (FM composite waveform data) of the OP2 whose amplitude level has been controlled and composed of an antilogarithmic expression output from the selector 64
After a delay of a total of four clocks by each of the delay circuits 53, 55, 57, 59, a shift / log-linear converter 65
And is written into the register REG4 at the timing of step S19 (see FIG. 16D). In this way, the generated waveform data (FF) of the OP2 whose amplitude level has been controlled and is represented by an antilogarithm and stored in the register REG4.
M synthesized waveform data) is subjected to arithmetic processing as will be described later in step S1 for the next channel three clocks later, and is further processed in step S4 three clocks later.
It is stored in the storage area of the waveform data TR2 of OP2 of the corresponding channel of AM4 (see FIGS. 16C and 16E).

(6) Operation of DSP 4 in Steps S20, S1, and S4 In step S20, the storage area of the waveform data TR1 of the OP1 of the corresponding channel in the RAM 4 on the condition that a specific FM operation algorithm is selected. , The data TR1 is read from the memory, input as data # RAM4 to the selector 51, and the selector 51 performs a process of selecting the data TR1.
At this time, nothing is input to the A input of the arithmetic unit ALU4. Therefore, the waveform data TR1 of OP1 is
4, the signal passes through the arithmetic unit ALU4 as it is, and the delay circuit 5
5 and overflow / underflow controller 5
6, after a delay of a total of two clocks, is output as data # 4 at the timing of step S1 of the next channel (see FIG. 16C).

In the step S1 of the next channel, FIG.
As shown in FIGS. 6 (a) and 6 (b), data # 4 (that is, the waveform data TR
1) is selected and inputted, and data # REG4 (that is, generated waveform data of the OP2 whose amplitude level is controlled and stored in the register REG4 at the timing of step S19 and whose amplitude level is controlled) is selected as the B input of the arithmetic unit ALU4. input. Therefore, the waveform data TR1 of OP1 and OP2
Are added by the arithmetic unit ALU4. The selector 64 selects the γ input corresponding to the processing in step S1. Therefore, the result of the arithmetic unit ALU4 is output from the selector 64 as it is via the delay circuit 55 and the overflow / underflow controller 56, passes through the shift / log-linear converter 65 as it is, and is sent to the RAM 4 via the delay circuit 67. Is entered. Therefore, the result of the arithmetic unit ALU4 corresponding to the processing of step S1 is
After a total of three clock delays by the delay circuits 53, 54, 55 and 67, the RAM 4
(See FIG. 16 (e)).

If the specific FM operation algorithm has not been selected, the reading of the OP1 waveform data TR1 from the RAM 4 is not performed or the selector 51 does not select any input data in step S20. Control. As a result, in the operation of the arithmetic unit ALU4 in step S1, the generated waveform data (FM synthesized waveform data) of OP2 is output as it is without change, and this is output at the timing of step S4.
M4 is stored in the storage area of the waveform data TR2 of the channel. Thus, finally, the waveform data TR2 stored in the predetermined storage area in the RAM 4 is
It is used as waveform data of a tone signal synthesized by the FM synthesis method.

The above steps S10, S14, S15,
Operator O by the processing of S19, S20, S1, S4
The generation processing of the FM synthesized waveform data in P2 is shown in FIG.
In the operation function development diagram of FIG. 7, the phase data PGf2 is input to the noise applicator 52 (S0, S10), and the register ALU4 & RAM4 (S17, S2)
(0, S1) corresponding to the path to be stored as the waveform data TR2. In this case, the selector SEL2
Is the register RAM4 (S7), that is, OP from RAM4.
1 is read and the adder ALU4 (S
0, S10).

(7) Other Descriptions In steps S13, S16, S18, and S2 of FIG.
Similar to the same steps in FIG. 13, noise formant sound waveform data creation processing is performed, and the noise waveform data TRu of the channel is stored in a predetermined storage area of the RAM 4. In steps S2 and S12 in FIG.
3 is related to the calculation processing of the window function phase data PGw1 and PGw2 as in the corresponding step in FIG.
Since these phase data are not used at all in the synthesis, it is meaningless processing. For the sake of simplicity of program creation, the program only partially overlaps with the formant sound synthesis program. Therefore, a program in which the operation contents of these steps are completely omitted may be used.

The waveform data TR2 and TRu (and TR1 if necessary) for each channel created by the above-described FM synthesis operation processing in the DSP 4 and stored in the RAM 4 are used in the “mixing operation” in the DSP 1 described above. For this purpose, the data is read out from the RAM 4 of the DSP 4 and supplied to the DSP 1 via the data bus DBUS.
The steps S11, S12,
Through the processing of S19 and S20, the left and right levels are controlled according to the panning parameters PAN and uPAN, and the sum is added for all channels, and output as left and right musical tone mixed data MIXL and MIXR, respectively. DA via
It is sent to the converter DAC and given to the sound system SS.

For reference, each DSP1 as described above
FIG. 20 shows a functional block diagram of the operators OP1 and OP2 for FM synthesis realized by the cooperation of the DSP4.
FIG. 21A and FIG. 21B show an example of the FM operation algorithm in a functional block diagram. In FIG. 20, the phase data PGf1 or PGf of the modulated wave or the carrier wave according to the pitch frequency number FNUM.
The function of the phase generator PG for generating f2 is D
This is realized by SP1. Also, this phase data PGf1 or PGf2 is used as feedback waveform data F
A portion including an adder AD that modulates with R or modulated wave waveform data TR1, a waveform memory SWM that reads waveform data by the added output, and a multiplier MUL that multiplies the read waveform data by the amplitude level data LVL1 or LVL2. The function is realized by the DSP 4 as described above. Further, the amplitude level data LVL1 or LV
The function of the envelope generator EG for generating L2 is DSP
2 is realized.

FIG. 21A shows an FM designated when the value of the tone synthesis algorithm parameter ALG is “1”.
4 shows an operation algorithm. In this algorithm, the operator OP1 performs a self-feedback FM operation, uses the generated waveform data TR1 as modulated waveform data, modulates the phase of the phase data PGf2 of the operator OP2, and generates the FM synthesized waveform data as the generated waveform data TR2 of the operator OP2. Is output as for that purpose,
In step S0 in FIG. 16, the feedback waveform data FR is supplied as the B input of the ALU4, and the operator OP
1 performs a self-feedback FM operation. In step S10, the waveform data T
R1 is supplied and the operator OP2 supplies the phase data PGf2
Is added to the waveform data TR1 in step S2.
At 0, the waveform data TR1 is not supplied as the B input of the ALU4, and TR1 and T1 are set at the subsequent step S1.
The addition of R2 is substantially not performed.

FIG. 21B shows an FM designated when the value of the tone synthesis algorithm parameter ALG is “2”.
4 shows an operation algorithm. In this algorithm, the operator OP1 performs the self-feedback FM operation, but the operator OP2 does not perform the FM operation, and outputs the generated waveform data TR1 and TR2 of both.
To this end, in step S0 of FIG. 16, the feedback waveform data FR is supplied as the B input of the ALU4 so that the operator OP1 performs the self-feedback FM operation. In step S10, the waveform data TR1 is supplied as the B input of the ALU4. Then, the modulation of the phase data PGf2 is not performed by the operator OP2, and in step S20, the waveform data TR1 is supplied as the B input of the ALU4.
And TR2 are substantially added. In addition,
21A and 21B, the noise formant sound generation unit NFG corresponds to the processing function of generating noise waveform data TRu in the DSP3 and DSP4. The process of adding the noise waveform data TRu to the tone waveform data obtained by the FM synthesis corresponds to the processing function of the “mixing calculation” of the DSP 1. Of course, whether to add the noise waveform data TRu can be appropriately selected. Needless to say, any FM operation algorithm other than the above can be appropriately realized.

[Explanation of Modification] As described above, in the digital signal processing device according to the present invention, the musical tone waveform synthesis operation is performed based on the cooperation of the plurality of digital signal processors DSP1 to DSP4. In the above embodiment, the calculation and processing for digital musical tone waveform synthesis are performed as follows.
The four digital signal processors are assigned and assigned, however, the present invention is not limited to this, and an arbitrary plurality of digital signal processors may assign and process. In this embodiment, the operations and processes for synthesizing digital musical tone waveforms are classified into five types: "phase operation", "envelope operation", "noise operation", "waveform generation operation", and "mixing operation". However, the present invention is not limited to this, and may be classified into appropriate types of calculations.

That is, in the above-described embodiment, a series of arithmetic processing for synthesizing digital musical tone waveforms is performed by “phase arithmetic”,
It is classified into five types of “envelope calculation”, “noise calculation”, “waveform generation calculation”, and “mixing calculation”,
The DSP 1 to DSP 4 are assigned to each other, and how to divide the arithmetic processing and the number of DSPs to be used depend on the use of the tone processing to be realized, the number of tone generation channels, and the
It can be appropriately determined according to the ability of P. For example, when increasing the number of musical tone generation channels, a plurality of DSPs that perform the same arithmetic processing may be provided in association with different channel groups. In addition, the number of DSPs incorporated in one system according to the present invention may be appropriately increased or decreased. For example, the parameter bus PBUS and the data bus DBUS in FIG. 1 may be configured to be extended or expanded so as to be able to cope with an increase in DSPs, so that a required number of DSPs can be added. In that case, not only the DSP but also a control processor (CPU) and a memory on the microcomputer COM side for performing parameter supply control, a memory, various input / output interfaces, and the like may be added as necessary. Thereby, it is possible to cope with the addition of the arithmetic processing function and the increase of the musical tone generation channels.

Further, in the above embodiment, two types of tone synthesis methods, a formant sound synthesis method and an FM synthesis method, can be realized, and the corresponding microprograms are stored in the digital signal processor. However, the present invention is not limited to this, and further stores a microprogram based on another musical tone waveform synthesizing method, or stores a microprogram based on another two kinds of musical tone waveform synthesizing methods, or uses any one of the musical tone waveform synthesizing methods To store only microprograms, etc.
It may be arbitrarily deformed. In addition, the present invention is not limited to the example in which the arithmetic and processing for synthesizing the digital musical tone waveform are performed by sharing a plurality of digital signal processors as in the above-described embodiment. The arithmetic and processing functions for imparting a musical sound effect may be shared by a plurality of digital signal processors, and the processing for imparting each musical sound effect or sound effect may be performed by their cooperation. In that case, a digital tone signal or sound signal to be processed is input to the digital signal processing unit and processed. Of course, a configuration may be adopted in which the digital musical sound waveform synthesis processing and the processing for imparting a musical sound effect are performed in combination. Furthermore, the present invention can be applied to an apparatus for synthesizing or processing voice sounds such as human voices, and an apparatus for synthesizing or processing sound effects such as onomatopoeia used in video games and video / audio software. In other words, the present invention can be applied to any of the above, and in short, the present invention can be applied to overall synthesis and / or processing of a sound signal.

The microprogram storing method in the microprogram supply unit 5 (FIG. 3) in each of the DSP1 to DSP4 is such that all necessary microprograms are fixedly stored in a gate array, and the tone synthesis algorithm is used. An arbitrary microprogram may be selectively read according to the designation, or the contents of the stored microprogram may be stored in the microcomputer C
The data may be arbitrarily rewritten under the control of the OM. When the latter program rewriting method is adopted, instead of rewriting all steps, for example, there is a common part or a negligible part between the formant sound synthesis method and the FM synthesis method described above. It is preferable to rewrite only a part of a necessary part without rewriting a program of a common part or an ignorable part. Then, the time required for rewriting the program can be shortened, and the rewriting microprogram data to be prepared in the microcomputer section COM does not need to be data of all steps, so that the storage capacity can be saved. it can. In the above embodiment, the microprogram supply unit 5 is provided for each of the DSP1 to DSP4. However, the present invention is not limited to this, and a memory (or a gate array) storing microprograms corresponding to each DSP may be provided with a common program counter (Or, a timing signal generator similar to a program counter) may be sequentially read in accordance with the operation step, and a corresponding microprogram may be supplied to each DSP.

In the above embodiment, a certain DSP
When the data created in (for example, DSP1) and stored in the RAM is used in another DSP (for example, DSP4), each read operation or capture operation is performed according to a microprogram for each DSP, and as a result, Multiple DS
P can perform cooperative processing. However, the present invention is not limited to the embodiment in which the reading operation and the fetching operation are performed in accordance with the microprogram for each DSP as described above.
When the data created by the P (for example, DSP1) and stored in the RAM is desired to be used by another DSP (for example, DSP4), a certain DSP (for example, DSP4)
A request signal is sent to the SP (for example, DSP1), and in response to the request signal, a certain DSP (for example, DSP1) reads necessary data from its RAM, and
P (for example, DSP4).

[Additional Explanation of Channel Synchronous Operation] An example of synchronous tone control according to the value of the channel synchronous operation flag RBP for each channel will be further described. FIGS. 22 and 23 show the tone generation channels CH1 realized in a time-sharing manner by the cooperation of the DSPs 1 to 4 as described above.
FIG. 3 is a functional block diagram conceptually illustrating -CH18 in parallel. FIG. 22 shows a state where the values of the channel synchronization operation flags RBP of all the channels CH1 to CH18 are “0”;
That is, a state is shown in which none of the channels performs synchronous tone generation control with other channels. KON1 to KON18 are key-on signals KON for each channel.
UM1 to FNUM18 are pitch frequency numbers FNUM for each channel. In this state, the key-on signals KON1 to KON18 and the pitch frequency number FNU which are independently supplied to the respective channels via the microcomputer section COM and the interface CIF.
M1 to FNUM18 are individually applied to each of the channels CH1 to CH18. Further, other parameter groups corresponding to the respective channels CH1 to CH18 (FNUM shown in FIG. 19)
And parameters other than KON) are also provided for the respective channels via the microcomputer COM and the interface CIF. Each channel CH1 ~
In CH18, based on these parameters, tone signals having timbre characteristics according to a designated tone synthesis algorithm are generated at original pitches and tone generation timings. FIG. 23 exemplarily shows a state in which the value of the channel synchronization operation flag RBP is "1" for some channels, that is, a state in which synchronous sounding designation with another channel is performed. In the example of the figure, the channel CH1 is RBP =
0, channels CH2 to CHk are RBP = 1, channels CHk + 1 and CHk + 2 are RBP = 0, channel C, respectively.
Hk + 3 shows an example in which RBP = 1 and channel CH18 shows RBP = 0. Note that k is an appropriate number.

As described above, in the channel of RBP = 1, the sound is controlled so as to synchronize with the adjacent channel having the smaller channel number. Therefore, in the example of FIG. 23, the channel CH2 is controlled so as to synchronize with the sound of the channel CH1. In channels CH2 to CHk, R
Since BP = 1, eventually these channels CH2
To CHk are channel synchronization operation flags R among sequentially adjacent channels having channel numbers smaller than that.
It is controlled so as to synchronize with the sound of the channel CH1 whose BP value is "0". Thus, channels CH2 to CHk
Is specified to be synchronized with the sound of the channel CH1, and the key-on signal KON1 and the pitch frequency number FNUM1 of the same channel CH1 are supplied to all of the channels CH2 to CHk, and tone signals are generated at the same pitch and sounding timing. Is done. The other parameter groups (parameter groups other than FNUM and KON shown in FIG. 19) are composed of individual data independently given to each of the channels CH1 to CHk, and thus are generated in each of the channels CH1 to CHk. Pitch and tone generation timing are common, but other tone characteristics such as timbre
It is unique for each channel. Therefore, for example, when a formant sound synthesis method is adopted as a tone synthesis method for each of the channels CH1 to CHk, the pitch and the sounding timing are the same by making the respective formant frequency numbers FORM different, but
A plurality of tone signals having different formant center frequencies can be synthesized in each of the channels CH1 to CHk, which is equivalent to synthesizing one tone signal having a multi-formant structure. Of course, each channel C to be synchronized
The tone synthesis method for H1 to CHk is not limited to the formant sound synthesis method, but may be the FM synthesis method. Alternatively, a certain channel may use the formant sound synthesis method and another channel may use the FM method. They may be mixed, and in such a case, a tone signal composed of a combination of a plurality of harmonic components can be easily synthesized.

Further, in the example of FIG. 23, the channel CHk +
1 and CHk + 2 each have RBP = 0, so that these channels CHk + 1 and CHk + 2 have their own key-on signals K
ONk + 1, KONk + 2 and pitch frequency number FNUMk +
1, a tone signal is generated independently based on FNUMk + 2 and other parameters. Also, channel CHk +
3, since RBP = 1, the previous channel CHk
Controlled so that the sound is synchronized with +2. Hereinafter, similarly, the remaining channels are controlled to be sound-synchronized or asynchronous with the adjacent channels according to the value of each channel synchronization operation flag RBP. In the above embodiment,
Certain channel CHk specified to be synchronized
Key-on signal KONk and pitch frequency number FNU
Mk is a predetermined channel CHk-1 (that is, an adjacent channel)
The process of changing or matching, that is, synchronizing, to any one of the components may be performed in any part of the configuration of FIG. For example,
In the computer interface CIF, the parameters of each channel provided from the microcomputer COM are buffered, and the contents of the flag RBP of each channel are checked. The key-on signal KON and the pitch frequency number FNUM of each channel may be supplied so as to satisfy the condition. Or,
The flag R of each channel inside the DSP1 and the DSP2
The content of the BP is checked, and the key-on signal KON and the pitch frequency number FN of each channel are checked according to the content so as to satisfy the sounding synchronization operation condition as described above.
UM may be supplied.

As is clear from the above, the value of the channel synchronization operation flag RBP for each channel can be arbitrarily varied, so that the value of the flag RBP for each channel is arbitrarily set variably for each musical tone generation opportunity. This makes it possible to easily synthesize a tone signal composed of various formant configurations or harmonic component group combinations by synchronizing the sound generation of a plurality of channels in various combinations, easily and using a limited tone generation channel configuration. The effect is that it can be performed. In the above example, the sound generation timing and the pitch are shared by a plurality of channels designated to be synchronized by the channel synchronization operation flag RBP. However, the present invention is not limited to this. Appropriate deformation such as shifting the height slightly or shifting by an integral multiple may be performed. Alternatively, not only the tone generation timing and pitch but also some tone color setting or volume setting parameters may be used in common. Alternatively, the sound generation start timing may be slightly or appropriately shifted.

In the above embodiment, when the value "1" of the channel synchronization operation flag RBP designates that the sound should be synchronously output with another channel, the channel is synchronized with the adjacent channel having a smaller channel number. On the other hand, on the other hand, it is also possible to synchronize successively with an adjacent channel having a larger channel number. Further, it is also possible to make a change so that only one adjacent channel is synchronized, instead of being sequentially synchronized with the adjacent channel as in the above embodiment. Further, in the above embodiment, the control is performed using only the flag RBP as the synchronous sounding designation data, which has the advantage of being easy to control. However, the present invention is not limited to this, and other data may be used. Is also good. For example, channel data designating a desired channel to be synchronized may be added to the channel synchronization operation flag RBP, so that not only adjacent channels but also arbitrary channels can be synchronized. Further, as a modified example, in the sound generation synchronous operation mode, a predetermined one channel may be determined as a basic channel, and an arbitrary channel designated to be synchronously generated may be synchronized with the basic channel. In addition, various modifications are allowed.

In the above-described embodiment, the digital signal processing unit DSPS as shown in FIG. 1 is used as a tone signal generator having a plurality of tone generating channels to realize the above-described channel synchronization operation. However, the present invention is not limited to this, and a tone signal generating device having any other configuration may be used. For example, the present invention is not limited to a multi-DSP having a parallel configuration as shown in FIG.
At that time, the above-described channel synchronization operation may be performed. Alternatively, the above-described channel synchronization operation may be performed in a tone signal generation device that realizes an arbitrary tone synthesis algorithm by software processing using a microcomputer. Alternatively, the above-described channel synchronization operation may be performed in a device using a tone signal generating circuit of a multi-channel time-division processing method having a pure hardware configuration. Alternatively, the above-described channel synchronization operation may be performed in a circuit having a plurality of individual tone signal generation circuits in parallel.

Some of the present invention and embodiments are listed as follows. (Item 1) Parameter supply means for supplying a plurality of parameters necessary for target sound signal processing;
A plurality of independent digital signal processing means, each one of which inputs parameters necessary for arithmetic processing and processes digital input data in accordance with the input parameters and a set program; The plurality of digital signal processing means, and a first bus commonly connected to each of the digital signal processing means, for outputting the processed data. Parameter input means for distributing and inputting each of the plurality of parameters supplied from the supply means to a predetermined digital signal processing means via the first bus, and commonly connected to each of the digital signal processing means; A data bus for transmitting output data of each of the digital signal processing means via the second bus. The at least one predetermined digital signal processing means captures output data from another digital signal processing means via the second bus, and uses the captured data as input data to perform the predetermined data processing. In this manner, the target sound signal processing is performed by a combination of the arithmetic processing by each of the plurality of digital signal processing means. As a result, the processed sound signal is processed by the plurality of digital signal processing means. A digital signal processing device, which is provided to the second bus as output data of predetermined digital signal processing means. (Item 2) In each of the digital signal processing means, the predetermined arithmetic processing is performed by executing the program in a time-division manner in a plurality of steps.
2. The digital signal processing device according to item 1, wherein each of the predetermined arithmetic processes is performed simultaneously and in parallel between the digital signal processing means. (Item 3) Each of the digital signal processing means includes an operation unit, a storage unit for storing the operation result, a program storage unit storing a microprogram that defines a procedure of the predetermined operation process, and the microprogram. A control unit that controls the arithmetic unit and the storage unit according to the control unit and executes the predetermined arithmetic processing. (Item 4) Each of the digital signal processing means is 1
4. The digital signal processing device according to item 1 or 3, wherein the digital signal processing device is configured by a plurality of integrated circuits. (Item 5) The digital signal processing device according to item 1, wherein at least one of the digital signal processing means performs arithmetic processing for generating tone waveform phase data corresponding to a desired pitch frequency. (Item 6) The digital signal processing device according to item 1 or 5, wherein at least one of the digital signal processing means performs arithmetic processing for generating envelope signal data for temporally controlling a musical tone. (Item 7) At least one of the digital signal processing means fetches the phase data and the envelope signal data output from the other digital signal processing means via the second bus, and generates a tone waveform based on these data. 7. The digital signal processing device according to item 1, 5 or 6, wherein the digital signal processing device performs arithmetic processing for generating data. (Item 8) The digital signal processing according to item 1, wherein the target sound signal processing is at least one of a processing of synthesizing a digital sound waveform signal and a processing of adding an acoustic effect to the digital sound waveform signal. apparatus.

(Item 9) In a sound signal synthesizing apparatus for synthesizing sound signals on a plurality of channels, a series of signal processing for sound synthesis is divided into a plurality of signal processing portions, each of which corresponds to one of the signal processing portions. A plurality of arithmetic processing means for executing the respective arithmetic processing,
The arithmetic processing means are provided in parallel, perform the corresponding arithmetic processing in parallel, and
Each one of the arithmetic processing means executes the arithmetic processing for each channel in a time-division processing timing unique to the individual arithmetic processing means in a time-division manner, and outputs the arithmetic processing result, and A plurality of arithmetic processing units, wherein at least one of the arithmetic processing units performs the arithmetic processing using an arithmetic processing result of another arithmetic processing unit, and a bus to which the arithmetic processing units are commonly connected. Data transmission means for providing the arithmetic processing result of each arithmetic processing means to another arithmetic processing means or an output port of a sound signal via the bus; and synthesizing a sound signal for each channel to each arithmetic processing means. A sound signal synthesizing device comprising: parameter supply means for supplying necessary parameters. (Item 10) The sound signal synthesizing device according to item 9, wherein the channel time-division processing timing in each of the arithmetic processing units is shifted from each other in accordance with a use form of the arithmetic processing result between the arithmetic processing units. . (Item 11) One of the arithmetic processing means performs arithmetic processing for generating envelope signal data for temporally controlling a musical tone, and another one of the arithmetic processing means includes: Item 10. The sound signal synthesizing apparatus according to Item 9, wherein the sound signal synthesizing apparatus performs arithmetic processing for generating a controlled tone waveform signal in accordance with the generated envelope signal data. (Item 12) The sound signal synthesizing device according to item 9 or 11, wherein one of the arithmetic processing means performs arithmetic processing for generating phase data of a musical tone waveform corresponding to a desired pitch frequency. (Item 13) One of the arithmetic processing means performs arithmetic processing for synthesizing a first sound waveform signal according to a predetermined first sound synthesis algorithm. A second arithmetic processing means for performing arithmetic processing for synthesizing a second sound waveform signal in accordance with a predetermined second sound synthesis algorithm; 3
The arithmetic processing means for generating envelope signal data for temporally controlling the sound, wherein the first and second sound processing means synthesize the first and second sound processing means. Item 10. The sound signal synthesizer according to Item 9, wherein the envelope of the waveform signal is controlled by envelope signal data generated in the third arithmetic processing means. (Item 14) The sound signal synthesizing device according to item 13, wherein at least the first arithmetic processing means can change the first sound synthesis algorithm according to a parameter. (Item 15) The sound signal synthesizing device according to item 9, wherein each of the arithmetic processing units includes a storage unit for storing an arithmetic processing result, and the arithmetic processing result is supplied to the bus via the storage unit. (Item 16) The storage means performs write control of the calculation processing result of the calculation processing means in accordance with the channel time-division processing timing in the corresponding calculation processing means, and performs another calculation using the calculation processing result. Item 16. The sound signal synthesizing device according to Item 15, wherein the processing means controls reading of the arithmetic processing result in accordance with the channel time division processing timing.

(Item 17) A parameter supply means for supplying a plurality of parameters necessary for a target sound signal processing, and a plurality of independent digital signal processing means. One is a processing unit for inputting parameters required for calculation processing and performing a predetermined calculation processing on digital input data in accordance with the input parameters and a set program; and a processing output from the calculation processing unit. A plurality of digital signal processing means, each including a dual port memory having a write port and a read port for storing result data, and a first bus commonly connected to each of the digital signal processing means; , Each of the plurality of parameters supplied from the parameter supply means is transferred to the first bus. Parameter input means for distributing and inputting to predetermined digital signal processing means via
A second common terminal commonly connected to the digital signal processing means;
Data transmission means for transmitting output data read from a read port of the dual port memory of each of the digital signal processing means via the second bus, wherein at least one of the predetermined digital signal The processing means captures output data from the other digital signal processing means via the second bus, and performs the predetermined arithmetic processing using the captured data as input data. A digital signal processing apparatus, wherein each digital signal processing means is operable at an independent timing by providing the processing result data to another digital signal processing means via a port memory.

(Item 18) In a plurality of channels, sound signal generating means for individually generating a sound signal based on independently given parameters, and at least sound generation designation information and another channel corresponding to each channel. Parameter supply means for respectively supplying the parameters including synchronous sounding designation data for specifying whether or not synchronous sounding is to be performed, and synchronous sounding sounding based on the synchronous sounding designation data supplied corresponding to each channel. A sound signal synthesizing device comprising: control means for controlling the sound signal generating means so as to generate a sound in synchronization with sound generation of a predetermined other channel in a designated channel. (Item 19) The item (1), wherein the predetermined other channel is a channel adjacent to the channel for which the synchronous sounding designation is made and for which no synchronous sounding designation is made.
9. The sound signal synthesizer according to 8. (Item 20) The item (18), wherein the control means controls the sound generation timing and the pitch on the channel for which the synchronous sound generation is specified so as to be synchronized with the sound generation timing and the pitch on the predetermined other channel.
Or the sound signal synthesizing apparatus according to 19. (Item 21) The parameters include parameters for tone color setting and control. In the sound signal generating means, the parameters for tone color setting and control are determined by whether or not the synchronous tone generation designation is possible. 21. The sound signal synthesizing apparatus according to item 20, wherein the sound signal synthesizing in each channel is performed using the unique parameters corresponding to each channel.

[0278]

As described above, according to the present invention, a series of arithmetic processing for a target digital sound signal processing is divided into a plurality of arithmetic processing parts corresponding to a plurality of digital signal processing means. Then, the respective arithmetic processing sections are executed in parallel in the respective digital signal processing means, so that even if the total number of arithmetic processing steps is large and the sound signal to be processed is multi-channel, the overall And that the speed of the arithmetic processing can be increased. In addition, since each digital signal processing means is configured to execute only a part of the arithmetic processing part of a series of objective arithmetic processing, the content of the arithmetic processing to be performed is relatively simplified. Not only simplifies the circuit configuration of each digital signal processing means but also makes them similar to each other.
The digital signal processing means can be designed and manufactured easily and at low cost, and the versatility of the device can be improved.

Also, a plurality of digital signal processing means are
Since the configuration is such that the first and second buses are commonly connected, when increasing the number of the digital signal processing means, it is necessary to route input parameter wiring and output data interconnect wiring. Therefore, the number of the digital signal processing means can be very easily increased or decreased since the buses need only be connected to the buses. Therefore, also in this respect, the versatility of the device can be improved and efficient use can be achieved. When a tone synthesis system is configured by mixing a plurality of types of tone synthesis methods, a common digital signal processing means is used for an operation processing portion which can be processed by a common operation algorithm even in different tone synthesis methods. Since it can be used, there is an excellent effect that an efficient system can be configured. In the case where the content of a part of the arithmetic processing for sound signal synthesis or processing is to be changed, only the digital signal processing means corresponding to the arithmetic processing part to be changed requires its program or circuit configuration. Therefore, there is an excellent effect that the design can be changed efficiently and at low cost. Therefore, according to the present invention, it is possible to efficiently respond to a request to change the content of arithmetic processing for sound waveform synthesis or processing. , Or a digital signal processing system for multifunctional sound synthesis or processing can be efficiently constructed.

Further, in the case of synthesizing a sound signal in a time-division manner on a plurality of channels, each one of the plurality of arithmetic processing means performs an arithmetic processing for each channel at a time-division processing timing unique to the individual arithmetic processing means. Is performed in a time-sharing manner, for example, in accordance with the role of the signal processing portion shared by each arithmetic processing means, it is possible to adjust the timing so that the channel time-division processing timing in each arithmetic processing means is shifted from each other. Since it is possible to appropriately shift (or not necessarily shift) each channel time-division processing timing in accordance with the utilization form of the arithmetic processing result of each arithmetic processing means, a certain arithmetic processing can be performed. When the arithmetic processing result output from the means is input to another arithmetic processing means and used, it is appropriately used at an efficient timing. It can be, can proceed arithmetic processing as a whole promptly demonstrates an excellent effect of.

Further, each digital signal processing means inputs a parameter required for the arithmetic processing, and performs an arithmetic processing section for performing a predetermined arithmetic processing on the digital input data according to the input parameter and a set program. Since it includes a dual port memory having a write port and a read port for storing processing result data output from the arithmetic processing unit, writing and reading of the dual port memory can be controlled at independent timings. When a certain first digital signal processing means takes in and uses output data from another second digital signal processing means via the second bus, the second digital signal processing means Means for reading and processing the processing result data through said dual port memory. In this case, the reading can be controlled at a unique timing of the first digital signal processing means on the user side different from the writing operation timing of the second digital signal processing means. Can be operated at independent timings, and the respective digital signal processing means can form their respective operation programs without being excessively restricted while being related to each other, which is extremely efficient.

Furthermore, synchronous tone designation data for designating whether or not to make a synchronous tone with another channel is given independently for each channel, and based on this, tone synchronization control is performed between a plurality of arbitrary channels. Therefore, a plurality of channels can be sound-synchronized and controlled in various combinations, so that one complex tone signal can be synthesized as a whole by combining sounds having different formant configurations or harmonic components in the channels to be sound-synchronized. Therefore, simply by arbitrarily setting synchronous tone designation data for each channel, synthesizing a tone signal composed of various formant configurations or combinations of harmonic components by synchronizing the tone generation of a plurality of channels in various combinations. Can be realized easily and with a limited musical tone generation channel configuration. It exhibits an excellent effect that.

[Brief description of the drawings]

FIG. 1 is an overall configuration block diagram of an embodiment of an electronic musical instrument employing a digital signal processing device according to the present invention.

FIG. 2 is a functional block diagram showing the flow of signals and information between DSPs in FIG.

FIG. 3 is a block diagram showing a basic structure example of one DSP.

FIG. 4 is a view showing an example of a storage map of a dual port RAM provided in each DSP in FIG. 1;

FIG. 5 is a block diagram showing a hardware configuration example of a DSP 1 in FIG. 1;

FIG. 6 is a block diagram showing a hardware configuration example of a DSP 3 in FIG. 1;

FIG. 7 is a block diagram showing a hardware configuration example of a DSP 4 in FIG. 1;

FIG. 8 is a time chart illustrating the relationship between the time-division processing channel timings of each DSP.

FIG. 9 is a time chart showing an operation example of each step of the microprogram of the DSP 1 when performing processing in accordance with the formant sound synthesis method.

FIG. 10 is a functional block diagram showing the arithmetic processing functions executed by the DSP 1 in an expanded manner.

FIG. 11 is a time chart illustrating an operation example of each step of the microprogram of the DSP3.

FIG. 12 is a functional block diagram showing the arithmetic processing functions executed by the DSP 3 in an expanded manner.

FIG. 13 is a time chart showing an operation example of each step of the microprogram of the DSP 4 when processing is performed according to the formant sound synthesis method.

FIG. 14 is a functional block diagram showing the arithmetic processing functions executed by the DSP 4 in an expanded manner.

FIG. 15 shows DS when processing is performed according to the FM synthesis method.
6 is a time chart showing an operation example of each step of the microprogram of P1.

FIG. 16 shows DS when processing is performed according to the FM synthesis method.
6 is a time chart illustrating an operation example of each step of the microprogram of P4.

FIG. 17 is a waveform chart showing an example of various phase data created by the DSP 1 at the time of formant sound synthesis.

FIG. 18 is a waveform chart showing an example of various tone waveforms generated by the DSP 4 at the time of formant sound synthesis.

FIG. 19 is a list showing an example of parameter data given to each DSP from the microcomputer unit of the electronic musical instrument.

FIG. 20 is a functional block diagram schematically showing an arithmetic processing function of one operator for FM synthesis operation realized by cooperation of a predetermined plurality of DSPs.

FIG. 21 is a functional block diagram showing an example of an FM synthesis operation algorithm realized by a combination of a plurality of operators for FM synthesis operation.

FIG. 22 is a functional block diagram showing an example of a channel synchronization operation in which channels are conceptually arranged in parallel when the values of channel synchronization operation flags RBP of all channels are “0”.

FIG. 23 shows another example of the channel synchronization operation in which the channels are conceptually arranged in parallel when the value of the channel synchronization operation flag RBP of a certain number of channels is “1”; The functional block diagram shown.

[Explanation of symbols]

DSPS Digital Signal Processor DSP1, DSP2, DSP3, DSP4 Digital Signal Processor COM Microcomputer OPS Controller CIF Computer Interface PBUS Parameter Bus DBUS Data Bus DIF Data Interface DAC Digital / Analog Converter SS Sound System CLKG Clock Generator MIF Memory Interface WM Waveform memory 5 Microprogram supply unit 6 Control signal generation unit 7 Operation and storage unit 8 Operation unit ALU1, ALU2, ALU3, ALU4 Arithmetic unit RAM1 to RAM4 Dual-port random access memory REG1, REG2, REG3, REG4, AREG
register

Claims (4)

(57) [Claims] 1. A parameter supply means for supplying a plurality of parameters necessary for a target sound signal processing, and a plurality of independent digital signal processing means, each one of these digital signal processing means comprising: Inputting parameters necessary for arithmetic processing, performing predetermined arithmetic processing on digital input data in accordance with the input parameters and a set program, and outputting the processed data. Digital signal processing means; a first signal processing means connected in common to each of the digital signal processing means;
Parameter input means for distributing and inputting each of the plurality of parameters supplied from the parameter supply means to a predetermined digital signal processing means via the first bus; and each of the digital signals A second commonly connected processing means
And a data transmission means for transmitting output data of each of the digital signal processing means via the second bus, wherein at least one predetermined digital signal processing means performs the other digital signal processing. Means for receiving the output data from the means via the second bus, and performing the predetermined arithmetic processing using the captured data as input data, whereby the arithmetic processing by the plurality of digital signal processing means is combined. The target sound signal processing is performed, and the processed sound signal is supplied to the second bus as output data of a predetermined digital signal processing unit of the plurality of digital signal processing units. Digital signal processor. 2. A sound signal synthesizing apparatus for synthesizing sound signals on a plurality of channels, wherein a series of signal processing for synthesizing sound signals is divided into a plurality of signal processing portions, each of which corresponds to one of the signal processing portions. A plurality of arithmetic processing means for respectively executing arithmetic processing, wherein each of the arithmetic processing means is provided in parallel, and performs each of the corresponding arithmetic processing in parallel, and Each one of the arithmetic processing means executes the arithmetic processing of each channel in a time-division processing timing unique to the individual arithmetic processing means in a time-division manner, and outputs the arithmetic processing result; The plurality of arithmetic processing means, wherein at least one of the processing means performs the arithmetic processing using the arithmetic processing result of the other arithmetic processing means, A data transmission means for providing the operation processing result of each operation processing means to another operation processing means or a sound signal output port via the bus; and A sound signal synthesizing device, comprising: parameter supply means for supplying parameters necessary for sound signal synthesis. 3. The arithmetic processing means according to claim 1, wherein :
A write port for storing the result of the arithmetic processing of the stage;
Readout port for reading out the stored processing results
Claims that include a dual port memory having
Item 3. The sound signal synthesizing device according to Item 2. 4. A parameter supply means for supplying a plurality of parameters necessary for a target sound signal processing, and a plurality of independent digital signal processing means, each one of these digital signal processing means comprising: An arithmetic processing unit for inputting parameters required for arithmetic processing, performing predetermined arithmetic processing on digital input data according to the input parameters and a set program, and processing result data output from the arithmetic processing unit A plurality of digital signal processing means, each of which includes a dual port memory having a write port and a read port for storing the first and second digital signal processing means.
Parameter input means for distributing and inputting each of the plurality of parameters supplied from the parameter supply means to a predetermined digital signal processing means via the first bus; and each of the digital signals A second commonly connected processing means
Data transmission means for transmitting output data read from a read port of the dual port memory of each of the digital signal processing means via the second bus, wherein at least one of the predetermined digital signal The processing means captures output data from the other digital signal processing means via the second bus, and performs the predetermined arithmetic processing using the captured data as input data. A digital signal processing apparatus, wherein each digital signal processing means is operable at an independent timing by providing the processing result data to another digital signal processing means via a port memory.