JP2809949B2 - MOS integrated circuit device having complementary inverter output stage - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS integrated circuit device, and more particularly to an output stage in which a pair of complementary FETs having mutually opposite conductive channels are connected in a push-pull manner (hereinafter simply referred to as a complementary inverter output stage). ).

[0002]

2. Description of the Related Art FIG. 1 shows an example of a MOS integrated circuit device having a complementary inverter output stage. This MO
The S-type integrated circuit device has a function of relaying an LCD data signal for driving a liquid crystal display (hereinafter abbreviated as LCD) to a substrate terminal only in the presence of an LCD enable signal.

That is, an LCD data signal is a NAND data signal.
The LCD enable signal is supplied directly to the other input terminal of the NAND gate, while the LCD enable signal is supplied to the other input terminal of the NOR gate 2 via the inverter 3. You. The logic gate 4 including the NAND gate 1, the NOR gate 2, and the inverter 3 is driven by the high-potential power supply voltage VDD and the low-potential power supply voltage VSS supplied to the integrated circuit.

The power supply voltages VDD and VSS are converted by the power supply circuit 5 into power supply voltages V3 and V3SS whose magnitudes are three times the absolute values of VDD and VSS.
It is supplied to the high potential side terminal and the low potential side terminal of the complementary inverter output stage constituted by 6 and 7, respectively. The output of the NAND gate 1 among the outputs of the logic gate 4 is supplied to the gate terminal of the FET 6 via the level shift circuit 8. The output of the NOR gate 2 is supplied directly to the gate terminal of the FET 7. Note that the level shift circuit 8 is connected to the high voltage level VD from the NAND gate 1.
Convert D to V3.

The output line of the complementary inverter output stage is connected to a port (not shown) via a so-called pad or substrate terminal 9. This port is connected to an input terminal (not shown) of the LCD. The input terminal of the inverter 10 is connected to this board terminal, and the port is L
It is used not only as a CD output port but also as an input port.

[0006]

In such a conventional MOS type integrated circuit device, if the LCD output port is not used for the I / O output port, the LCD output voltage and the I / O output are not used.
Because of the voltage difference from the output voltage, a reverse bias is applied to the FET constituting the output stage, which causes a problem.

Accordingly, an object of the present invention is to provide an integrated circuit that can relay two output signals having different output voltage levels through the same port.

[0008]

SUMMARY OF THE INVENTION A MOS integrated circuit device according to the present invention comprises a first FET comprising a pair of FETs provided on a substrate and each having a conductive channel of opposite conductivity to each other.
A complementary inverter output stage and a pair of Fs, each having a conductive channel on the substrate and oppositely conductive.
A second complementary inverter output stage comprising ET;
And the output line of the second complementary inverter output stage is connected in common.
And a single board output terminal continues, the saw including a first and a second driving stage the first and second complementary inverter output stage is driven independently, the inner from the substrate output terminals of two signals of
A MOS-type integrated circuit device to selectively output either, before Symbol first and second high-voltage power source should leave each applied to the power supply terminals of the first and the high potential side of the second complementary inverter output stage The power supply voltage having a higher potential is selected from the higher potentials of the first and second complementary inverter output stages.
First bias voltage applying means for supplying to the conductive channel of ET, and a lower one of first and second low-voltage power supply voltages to be applied to a low-potential power supply terminal of the first and second complementary inverter output stages. The power supply voltage of the first
And second bias voltage applying means for supplying a conductive channel of the FET on the low potential side of the second complementary inverter output stage.

[0009]

In the MOS integrated circuit device according to the present invention, independent information signals are relayed via two complementary inverter output stages whose output lines are connected to a common substrate terminal.

[0010]

2 is different from the conventional circuit shown in FIG. 1 in the following points. That is, the logic gate 4
Is output through the level shift circuits 8A and 8B to the FETs.
It is relayed to gates 6 and 7. Level shift circuit 8
A and 8B respectively convert a VDD input to a V3 output,
Convert SS input to V3SS output. A logic gate 20 driven by the power supply voltages VDD and VSS is provided. The logic gate 20 is the logic gate 4
In the same manner as described above, the circuit comprises a NAND gate 21, a NOR gate 22, and an inverter 23. The output terminals of the NAND gate 21 and the NOR gate 22 are provided on the same substrate as the FETs 6 and 7 and have conductive channels of opposite conductivity types to form a second complementary inverter output stage.
It is connected to the gate terminals of ET24 and ET25.

The FETs 6, 7, 24, and 25 are of the type shown in FIG.
N provided P type substrate, as shown in ^-, p ^-, n ^-,
p ^-, it is formed in the well region. Therefore, FE
Conductive channel T6,24 each n ^- is in the form, FE
Conductive channel T7,25 each p ^- is a form. The voltage V is applied to the n ^-type conductive channels of the FETs 6 and 24.
H is applied as a bias voltage, and the p
^The voltage VL is applied to the negative conductive channel.

The power supply voltage VH is generated by the high-voltage power supply circuit 26 and is equal to the higher of the high-potential power supply voltages VDD and V3. Further, the power supply voltage VL is controlled by the low voltage side power supply circuit 27.
And the low-potential-side power supply voltages VSS and V3S
S is set equal to the lower voltage of S.

FIGS. 4A and 4B show a high-voltage power supply circuit 26 and a low-voltage power supply circuit 27, respectively.
3 shows a specific circuit example. That is, the high-side power supply circuit 26 supplies the high-side power supply voltages V3 and V3 to the anode, respectively.
The diodes 30 and 31 are supplied with DD, and the cathodes of the diodes 30 and 31 are connected together to output a voltage VH. That is, V3
VH = V3 when> VDD, and VH = VDD when V3 ≦ VDD.

The low-voltage power supply voltage supply circuit 27 is composed of diodes 32 and 33 whose cathodes are supplied with the low power supply voltage V3SS and VSS, respectively. VL is output. That is, V3SS <VS
When S, VL = V3SS, and when V3SS ≧ VSS, VL = VSS.

Due to the operation of the high voltage side power supply circuit 26, even if VDD is higher than V3, the FET 6,
No forward bias is applied between the source and drain regions of 24 and the conductive channel. Similarly, by the operation of the low-voltage side power supply circuit 27, even if VSS is lower than V3SS, there is no possibility that a forward bias is applied between the source and drain regions of the FETs 7, 25 and the conductive channel. is there.

In the above-described embodiment, the substrate terminal for relaying the LCD drive signal using V3 and V3SS as the output power supply voltage is connected to the I / O terminal using the power supply voltages VDD and VSS as the output power supply voltage.
Although this example is also used for relaying 0 data, it is clear that the MOS integrated circuit device according to the present invention is effective if the output power supply voltages are different from each other.

[0017]

As is apparent from the above description, the MOS type integrated circuit device according to the present invention comprises two output stages each comprising a pair of FETs having a pair of conductive channels of opposite conductivity type. Output line is commonly connected to a single substrate terminal, but the higher of the high-potential-side power supply voltage of the complementary inverter output stage is used as the high-potential-side bias voltage as the bias voltage to be applied to the conductive channel of each FET. Since the lower one of the low-potential-side power supply voltages is used as the low-potential-side bias voltage, the high-potential-side power supply voltage and the low-potential-side power supply voltage supplied to the two complementary inverter output stages are different from each other. However, no forward bias is applied between the conductive channel of the FET and the source / drain, and no problem occurs.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a conventional example.

FIG. 2 is a circuit diagram showing a MOS integrated circuit device according to an embodiment of the present invention.

3 is a cross-sectional view showing an example of an arrangement in a substrate of FETs constituting a complementary inverter output stage of the MOS integrated circuit device of FIG. 2;

4 is a circuit diagram showing a specific circuit example of the high-voltage power supply circuit 26 and the low-voltage power supply circuit 27 of FIG.

[Description of Signs of Main Parts]

4,20 Logic gate 6,7 FE forming first complementary inverter output stage
T 9 Common substrate terminal 24, 25 FET forming second complementary inverter output stage 26 High voltage side power supply circuit 27 Low voltage side power supply circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 27/092 H03K 19/0185

Claims (4)

(57) [Claims] 1. A first FET comprising a pair of FETs provided on a substrate and each having a conductive channel of opposite conductivity to each other.
A complementary inverter output stage and a pair of Fs, each having a conductive channel on the substrate and oppositely conductive.
A second complementary inverter output stage comprising ET;
And the output line of the second complementary inverter output stage is connected in common.
And a single board output terminal continues, the saw including a first and Atsushi second driving stage the first and second complementary inverter output stage is driven independently, the inner from the substrate output terminals of two signals of
A MOS-type integrated circuit device to selectively output either, before Symbol first and second high-voltage power source should leave each applied to the power supply terminals of the first and the high potential side of the second complementary inverter output stage First bias voltage applying means for selectively supplying a higher potential power supply voltage among the voltages to the conductive channel of the FET on the higher potential side of the first and second complementary inverter output stages; The power supply voltage having a lower potential is selected from the first and second power supply voltages to be applied to the power supply terminal on the low potential side of the output stage of the two complementary inverters.
A MOS type integrated circuit device, comprising: a second bias voltage applying means for supplying a conductive channel of a low-potential side FET of a complementary inverter output stage. 2. The first and second driving stages are connected to one of the first and second complementary inverter output stages.
The enable signal is relayed to the gate terminal of ET, and the other F
2. The MOS integrated circuit device according to claim 1, further comprising a relay circuit for relaying a data signal to a gate terminal of the ET. 3. The MOS integrated circuit device according to claim 1, wherein each of said FETs is formed in a well region provided in said substrate. 4. The MOS integrated circuit device according to claim 1, further comprising a gate circuit provided in said substrate and having an input terminal connected to said substrate terminal.