JP2805888B2 - Thin film transistor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) having a staggered structure using polycrystalline silicon for a channel film, and more particularly to an improvement in a planar shape of a channel film and a gate electrode film. .

[Conventional technology]

Conventionally, the structure of a polycrystalline silicon thin film transistor having a staggered structure applied to a TFT low-temperature process or the like is formed on a transparent insulating substrate 1 such as quartz glass or hard glass with a space therebetween, as shown in FIG. A phosphorus-doped source film 2 and a drain film 3, a channel film 4 as an undoped polycrystalline silicon film having a margin between the source film 2 and the drain film 3, and a MOS film on the channel film 4.
(MIS) A thin silicon oxide film 5 as an insulating film to be formed and a gate electrode 6 of N-type high-concentration polycrystalline silicon or the like.
And an aluminum source electrode 7 and a pixel electrode (drain electrode) 8 as a transparent electrode, which are in conductive contact with the source film 2 and the drain film 3 via contact holes.

As shown in FIG. 5 (a), a process for obtaining a channel film 4 in a thin film transistor (TFT) having such a structure is as follows. First, a phosphorous film is formed on a transparent insulating substrate 1 such as hard glass by a low pressure CVD method or an ion implantation method. After covering the doped polycrystalline silicon film, the film is patterned and etched to form the source film 2 and the drain film 3 which are separated from each other. Next, as shown in FIG. 5 (b), after polycrystalline silicon 4 'is entirely covered on the source film 2 and the drain film 3, as shown in FIG. 5 (c), resist coating and patterning are performed. A resist pattern 9 whose side surface is located above the source film 2 and the drain film 3 is formed. Thereafter, as shown in FIG. 5 (d), the exposed region of the polycrystalline silicon film 4 'is removed by plasma etching with CF _4, underlying source layer 2 and the drain layer 3
Then, as shown in FIG. 5E, the resist pattern 9 is removed by a normal resist removing step (O ₂ plasma, hot sulfuric acid) to obtain the channel film 4.

However, in the step of obtaining the channel film ₄ by plasma etching of the thin polycrystalline silicon film 4 'with CF4 (FIG. 5D), the necessity of leaving the source film 2 and the drain film 3 makes the two films 2, 2 The plasma etching must be terminated moderately in the middle of the etching of 3,
The reaction product (silicon fluoride compound) 10 of CF ₄ adheres to the side surface of the resist 9 serving as an etching mask. The adhered reaction product 10 is extremely difficult to remove by the ordinary resist removal step (O ₂ plasma, hot sulfuric acid) shown in FIG. 5 (e), and adheres to the surface of the channel 4 as residue as it is, resulting in an abnormal MOS interface. As a result, the transistor characteristics are deteriorated.

Therefore, as a measure for preventing the surface contamination of the channel film 4 by such a reaction product, the following manufacturing method has been proposed.

First, as shown in FIG.
20 is formed on the source film 2 and the drain film 3, and the resist pattern 20 completely covers both the films 2 and 3, including the side surfaces 20 a of the source film 2 and the drain film 3, including the outer steps 2 a and 3 a. It is formed as follows. Next, as shown in FIG. 6 (b), plasma etching with CF ₄ is performed to remove the exposed region 4′a of the polycrystalline silicon film 4 ′. This plasma etching step is performed until the surface of the substrate 1 is completely exposed, without being completed in the middle of the etching of the polycrystalline silicon film 4 ', and then a slight overetch is performed. In this plasma etching step, the silicon of the polycrystalline silicon film 4 'to be etched and CF ₄ as an etchant are used.
Reacts to produce a reaction product that appears to be a silicon fluoride compound. However, plasma etching is not terminated during the etching of the exposed region 4′a of the polycrystalline silicon film 4 ′, and after the exposed region is completely removed. Since the overetch is performed, the reaction products generated before that are wiped out.
Therefore, after the overetch is performed, the reaction products do not adhere to the side surfaces of the resist pattern 20 or the like.

Next, as shown in FIG.
Is removed by an ordinary method (O ₂ plasma, hot sulfuric acid) to obtain a channel film 4 ″ having an outer step covering portion 4 ″ a also on the outer edges 2b, 3b of the source film 2 and the drain film 3. The residue of the reaction product does not adhere to the surface of the channel film 4 ″, and a clean MOS interface is obtained. Therefore, the problem of deterioration of transistor characteristics due to MOS interface contamination is solved.

[Problems to be solved by the invention]

FIG. 7 (a) shows a cross-sectional structure of the thin film transistor thus manufactured, and FIG. 7 (b) shows a planar structure thereof.
Since each of the source film 2 and the drain film 3 is covered with the channel film 4 ″ without the exposed region,
A new problem arises.

That is, due to the variation in the alignment accuracy of the channel film 4 ", the channel film 4" may be displaced in a direction perpendicular to the effective channel length L as shown in FIG. 8 with respect to the normal position shown in FIG. 7B. is there. Here, if the width dimension of the channel film 4 ″ is W ₁ and the protruding widths are d ₁ and d ₂ , W ₁ = W + d
₁ + Although the relation d ₂ is always satisfied, the alignment accuracy of the variation, non-uniform of d ₁ ≠ d ₂ occurs inevitably.
For example, as shown in FIG. 8, d ₁ <Once aligned as d _2, with the channel inversion layer that bulges in the region 4 "a width d ₂ protruding is formed, the source layer 2 and the drain Electric field concentration occurs at the corner edge of the film 3. Therefore, variations in the on-current capacity and a decrease in the withstand voltage due to a change in the region where the channel inversion layer is formed occur, resulting in a decrease in the yield of the thin film transistor.

The present invention has been made to solve the above problems, and the problem is to improve the planar shape of the channel film and the gate electrode film so that a reaction product in patterning by plasma etching of the channel film itself can be transferred to the channel film. In addition to minimizing the adhesion, the effective channel length and effective channel width of the channel inversion layer do not vary with respect to the unavoidable variation in alignment accuracy, and the variation in the on-current capacity is suppressed. To provide a thin film transistor.

[Means for solving the problem]

According to the present invention, there is provided a thin film transistor formed on a substrate, comprising: a first region and a second region formed of a first silicon thin film having a high concentration of impurities formed in an island shape on the substrate so as to be separated from each other; A second silicon thin film formed between and on the first region and the second region, and a channel region of the thin film transistor is formed of the second silicon thin film formed between the first region and the second region. A gate electrode is disposed on the channel region via a gate insulating film, and the width of the channel region made of the second silicon thin film is
The second silicon thin film is formed to be thinner than the width of the first region and the second region, and the second silicon thin film is formed so as to cover the first region and the second region. A low impurity concentration region made of the second silicon thin film is formed between the region and the first region and the second region.

[Action]

According to such a configuration, the following operation is exhibited. In other words, when the alignment accuracy varies in a direction perpendicular to the effective channel length direction, the effective channel width is smaller than the length of the inner edge of the source film or the drain film in the width of the equal width connection portion. Since the dimensions are uniquely defined, there is no variation in the effective channel width. Further, when the alignment accuracy varies in the effective channel length direction, the effective channel length is uniquely limited by the width dimension of the equal width gate electrode film which is narrower than the length of the equal width connection portion. Therefore, there is no variation in the effective channel length. For this reason, the channel inversion layer formed by the MOS effect always has an effective channel width as the width dimension of the equal-width connection portion and an effective channel length as the width dimension of the equal-width gate electrode film. Accuracy dependence can be eliminated.

In this means, a low impurity concentration region for forming a current path is provided on both sides immediately below the gate electrode film in the equal width connection portion of the channel film, and this region is a high impurity concentration region. It becomes a drift region as a high resistance region for the source film and the drain film.

As described above, in a short channel limited by a relatively narrow gate electrode film having a relatively small width, the generation of hot carriers and a decrease in breakdown voltage due to a decrease in a breakdown voltage pose a problem. Because of the existence, a so-called LDD structure is formed at the same time as the formation of the current path, so that the withstand voltage can be increased by relaxing the drain electric field.

On the other hand, since the source film and the drain film are hidden by the enlarged covering portion, there is no risk of reaction products adhering in the patterning step of plasma etching of the channel film itself, and the quality of transistor performance is improved.

〔Example〕

Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1A is a sectional view showing a structure of a thin film transistor according to an embodiment of the present invention, and FIG. 1B is a plan view of the same structure. In FIG. 1, the same portions as those shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

Polycrystalline silicon channel film 14 in this embodiment
A pair of left and right enlarged covering portions 12 and 13 covering the entire surface of the phosphorus-doped N-type high concentration source film 2 and the drain film 3;
And a narrow equal-width connecting portion 15 for connecting them. The enlarged covering portions 12 and 13 have a margin for completely covering the source film 2 and the drain film 3. The width of the equal-width connecting portion 15 is set to be smaller than the difference between the lengths of the opposed inner edges 2a, 3a of the source film 2 and the drain film 3 and twice as long as the matching margin of the channel film 14 itself. Have been.

On the other hand, the gate electrode 16 is formed to have a narrow width and an equal width, and its width dimension is set to be smaller than the difference between the length of the equal width connection portion 15 and twice the length of the allowance of the gate electrode itself. . The gate electrode 16 is made of a silicon oxide film 5 as a gate insulating film.
, The center of the equal-width connecting portion 15 is orthogonal to the other.

Polycrystalline silicon channel width 14 is equal width gate electrode
Using the mask 16 as a mask, the region is divided into an intrinsic semiconductor region and an N-type impurity semiconductor region by ion implantation or the like. That is, a region immediately below the gate electrode 16 is an effective channel portion 15a as an intrinsic semiconductor region, and the remaining region is an N-type low concentration region. The equal-width connecting portion 15 of the channel film 14 has an effective channel portion 15a formed at the intersection with the equal-width gate electrode 16.
And the low-concentration region 15 formed at the non-intersecting portions on both sides thereof
b, 15c. The low-concentration regions 15b and 15c correspond to the source film 2
And conductive contact with the drain film 3.

In a thin film transistor having such a structure, for example, even when the alignment accuracy of the channel film 14 varies in the direction of the arrow (the direction perpendicular to the effective channel length direction) in FIG. Since the width of the connecting portion 15 is smaller than the width of the inner edges 2a and 3a of the source film 2 and the drain film 3, and the gate electrode 16 has the same width, the channel inversion layer formed by the MOS effect is It always matches the shaded portion of the effective channel 15a. That is, the effective channel length and the effective channel width of the formed channel inversion layer are equal to those of the regular channel shown in FIG. In addition, even when the channel film 14 is displaced in the direction of the arrow (effective channel length direction) in FIG. 2B, the effective channel portion 15a is determined at the intersection of the equal-width connecting portion 15 and the equal-width gate electrode 16. Therefore, the effective channel length and the effective channel width of the formed channel inversion layer do not change. Further, even if the gate electrode 16 is displaced in the direction of the arrow in FIG. 2 (c), the effective channel length and the effective channel width remain unchanged since they are formed in the same width. Therefore, even if a normal variation in the alignment accuracy inevitably occurs in the manufacturing process (the patterning step of the channel film 14 and the gate electrode 16), the variation is effective if the channel film 14 and the gate electrode 16 have such a shape. The length and width of the channel portion 15a do not vary. In other words, a function of cutting off the causal relationship between the variation in alignment accuracy and the variation in the shape and size of the effective channel portion, which inevitably results in an orthogonal relationship between the equal-width connecting portion 15 of the channel film 14 and the equal-width gate electrode 16. Having. Therefore, a thin film transistor in which the variation in the on-current capacity is suppressed is realized, and therefore, the yield is improved.

In order to secure an effective channel portion 15a in which the shape and dimensions do not vary even if the alignment accuracy varies,
Although it is necessary to provide the marginal area on both sides of the effective channel portion 15a, the significance of forming the marginal area as the N-type low concentration regions 15a and 15b is that the current between the source film 2 and the drain film 3 is left as it is. Since no path is formed, a current path is formed by connecting the high resistance regions in series. The reason why the low-concentration region is formed instead of the high-concentration low-resistance region is that the purpose is not only to simply form a current path but also to increase the breakdown voltage. That is, the high concentration source film 2
And the low concentration regions 15b and 15c in contact with the drain film 3
The existence of a thin film transistor provides a thin film transistor having a lightly doped drain (LDD) structure. Therefore, the drain electric field particularly generated in the drain film 3 near the gate electrode is reduced, and the withstand voltage is improved.

Here, when the channel width 14 and the gate electrode 16 shown in FIG. 1 (b) are normal (the same applies to the state shown in FIG. 2 (a)), the equal width connection portion 15 of the channel film is equivalent to an equivalent circuit. FIG. 3 (a). R _ON is the on-resistance of the channel inversion layer formed in the effective channel portion 15a, and R _SG is the low concentration region.
The series resistance of 15b and _RGD are the series resistance of the low concentration region 15c. The equivalent circuit in the state shown in FIG. 2 (b) is shown in FIG. 3 (b) while the equivalent circuit in the state shown in FIG. 3 (b) is formed in the effective channel portion 15a as described above. Since the channel inversion layer is substantially unchanged, the on-resistance R _ON is also unchanged. The series resistance R 'of the low concentration regions 15b and 15c
The resistance values of _SG and _R'GD change with the change of the resistance length. In FIG. 3 (a), it can be expected that R _SG ≒ R _GD , but in FIG. 3 (b), the resistance length of the low-concentration region 15b becomes shorter, and accordingly, that of the low-concentration region 15c becomes smaller. Since the length is longer, R ′ _SG <R ′ _GD . However, the relationship R _SG + R _GD ≒ R ′ _SG + R ′ _GD holds. Therefore, the series resistance between the source and the drain can be considered to be constant, and the variation in the on-current capacity hardly occurs. FIG. 3 (c) shows an equivalent circuit corresponding to FIG. 2 (c). In such a case, FIG. 3 (a)
And the variation of the on-current capacity hardly occurs.

On the other hand, in the above embodiment, since the channel film 14 has the enlarged covering portions 12 and 13 that cover the source film 2 and the drain film 3, the channel of the reaction product in patterning the channel film 14 itself by plasma etching. Needless to say, adhesion to the film can be prevented.

〔The invention's effect〕

As described above, the present invention has a pair of enlarged covering portions covering both the source film and the drain film as shape elements of the channel film, and an equal width connecting portion connecting these, and furthermore, the gate electrode film has While keeping the shape equal in width, this was made orthogonal to the equal width connecting portion of the channel film with the gate insulating film interposed, and both sides of the equal width connecting portion immediately below the gate electrode film were made light concentration regions. Therefore, the following effects can be obtained.

Since the source film and the drain film are completely covered by the enlarged covering portion due to the presence of the enlarged covering portion of the channel film, reaction products generated in a patterning step by plasma etching of the channel film do not occur, and the transistor is not formed. The quality of the characteristics can be improved.

Even if the alignment accuracy varies due to the existence of the equal width connection portion of the channel film and the equal width gate electrode film almost perpendicular thereto, the shape and size of the formed channel inversion layer do not change. Variations in the on-current capacity due to this can be solved. In other words, the intersecting relationship between the channel film and the gate electrode film according to the above shape effectively absorbs variations in alignment accuracy.

Since a low concentration region where a current path is to be formed is formed on both sides of the channel film immediately below the gate electrode film,
While satisfying the above-mentioned effect, the withstand voltage of the thin film transistor can be increased at the same time.

[Brief description of the drawings]

FIG. 1A is a sectional view showing a structure of a thin film transistor according to an embodiment of the present invention, and FIG. 1B is a plan view of the same structure. 2 (a), 2 (b) and 2 (c) are schematic plan views showing a state in which the channel film or the gate electrode film is shifted due to the variation in alignment accuracy in the embodiment. FIGS. 3 (a), (b) and (c) show FIGS.
It is an equivalent circuit diagram of the example in the state corresponding to (b) and (c), respectively. FIG. 4 is a sectional view showing the structure of a conventional thin film transistor. 5 (a) to 5 (e) are cross-sectional views for explaining processes up to obtaining a channel film in the conventional structure. 6 (a) to 6 (c) are cross-sectional views illustrating a process in which the patterning step of the channel film in the conventional structure is improved. FIG. 7A is a cross-sectional view showing a structure of a thin film transistor obtained by the improvement process, and FIG. 7B is a plan view of the same structure. FIG. 8 is a plan view showing a state in which the channel film is displaced due to variation in alignment accuracy in the thin film transistor obtained by the improved process. [Explanation of Symbols] 1 ... Transparent insulating substrate 2 ... Source film 2a, 3a ... Inner edge 2b, 3b ... Outer edge 3 ... Drain film 5 ... Silicon oxide film 7 ... Source electrode 8 … Pixel electrode (drain electrode) 12,13… Enlarged covering part 14… Channel film 15… Equal width connecting part 15a… Effective channel part 15b, 15c… Low concentration region 16… Equal width Gate electrode.

Claims (1)

(57) [Claims] 1. A thin film transistor formed on a substrate, comprising: a first region and a second region formed of a first silicon thin film having a high concentration of impurities and formed in islands on the substrate so as to be separated from each other; A second silicon thin film formed between and above the island-shaped first region and the second region, wherein a channel region of the thin film transistor is formed between the first region and the second region. A gate electrode is disposed on the channel region via a gate insulating film. The width of the channel region made of the second silicon thin film is the width of the first region and the second region. It is formed thinner than
The second silicon thin film is formed so as to cover the first region and the second region, and the second silicon thin film is provided between the channel region of the second silicon thin film and the first region and the second region.
A thin film transistor comprising a low impurity concentration region formed of a silicon thin film.