JP2803295B2 - SOI substrate, semiconductor device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Outline Industrial application Field of the Invention Prior Art Problems to be Solved by the Invention Means for Solving the Problems Action Example Example of buried conductive film oxidized (FIG. 1) Lift-off Example (FIG. 2) Example using selective oxidation (FIG. 3) Example using etching mask (FIG. 4) Example using selective epitaxial (FIG. 5) Effect of the Invention [Overview] Conductive layer or conductive (Silicon on Insulator) substrate having an element formation layer on an insulating substrate via an insulating film and a method of manufacturing a semiconductor device using the same. The purpose of the present invention is to prevent charge-up of an element formation layer and to allow an arbitrary potential to be applied to the element formation layer. 1) An insulating film (3) on a conductive layer (4) or a conductive substrate
SOI substrate having an element formation layer (2) through
The element forming layer (2) is configured to be isolated in an island shape and to be electrically connected to the conductive layer (4) or the conductive substrate.

2) Insulating film (3) on conductive layer (4) or conductive substrate
A semiconductor device having an element forming layer (2) through the substrate, wherein the element forming layer (2) is separated into an island shape and is electrically connected to the conductive layer (4) or a conductive substrate. The configuration is as follows.

3) The device forming layer (2) and the insulating film (3) have a groove reaching the conductive layer (4), and a polishing stopper layer (1) or (14) is formed at the bottom of the groove. In the gap between the layer (2) and the polishing stopper layer (1),
It has a buried conductive layer (5) for electrically connecting the conductive layer (4) and the element forming layer (2).

4) a step of forming a groove reaching the conductive layer (4) in the element forming layer and the insulating film (3); and forming a polishing stopper layer (1) or (14) having a desired thickness at the bottom of the groove. Forming and forming a buried conductive layer (5) made of a material having a polishing rate close to that of the element forming layer (2) in a gap between the element forming layer (2) and the polishing stopper layer (1). And polishing the element forming layer (2) to a thickness defined by the polishing stopper layer (1).

[Industrial applications]

The present invention relates to an SOI (Silicon on Insulator) substrate having an element formation layer on a conductive layer or a conductive substrate via an insulating film, and a method for manufacturing a semiconductor device using the same.

[Conventional technology]

SOI with device formation layer on supporting substrate via insulating film
When an element is formed using a substrate, it is possible to increase the speed of the element and reduce soft errors due to radiation of the element.

Furthermore, since the elements can be easily electrically separated, CMO
It is also possible to prevent latch-up and noise reduction seen in S and the like.

In order to enhance the above effects, it is necessary to reduce the thickness of the element formation layer.

Conventionally, as a method of thinning the element formation layer, the surface of the element formation layer has been shaved by polishing.

In this case, since the thickness of the element forming layer varies greatly, a groove is formed to reach from the surface of the element forming layer to the bottom, and a polishing stopper layer having a desired thickness is formed in the groove, and then polishing is performed. A method of increasing the accuracy of the thickness of the element forming layer has been used.

Further, in order to obtain a uniform and high-precision thin film, a polishing stopper layer is grown in the groove, and then the inside of the groove is polished with a material having a polishing rate substantially equal to that of the element forming layer to perform polishing.

In the case of a substrate having a conventional structure, the element formation layer is electrically insulated from the conductive layer or the conductive substrate below the insulating film. In addition, the potential of each layer, which may charge up the element formation layer and hinder the injection or affect the element characteristics,
It has to be applied independently to the element forming layer and the conductive layer below the insulating film. In particular, it has been difficult to apply an arbitrary potential to the element formation layer.

[Problems to be solved by the invention]

The present invention prevents stable and highly accurate thinning of the element formation layer and prevents charge-up of the element formation layer during the manufacturing process.
Another object is to allow an arbitrary potential to be applied to the element formation layer.

[Means for solving the problem]

In order to solve the above-mentioned problem, an SOI substrate having an element formation layer provided over a conductive layer or a conductive substrate with an insulating film interposed therebetween, the element formation layer and the insulating film being provided with the conductive layer or the conductive substrate. A polishing stopper layer having an area smaller than the bottom surface is formed on a bottom surface of the groove, and a gap between the element forming layer and the polishing stopper layer is provided between the conductive layer or the conductive substrate and the element. This can be achieved by an SOI substrate having a buried conductive layer that electrically connects the forming layers.

The above-described SOI substrate is also achieved by an SOI substrate in which a structure in which the element formation layer is electrically connected to the conductive layer or the conductive substrate is formed at least in a dicing line region.

In a semiconductor device formed using an SOI substrate having an element formation layer provided over a conductive layer or a conductive substrate with an insulating film interposed therebetween, the element formation layer and the insulating film may be formed of the conductive layer or A polishing stopper layer having an area smaller than the bottom surface is formed on the bottom surface of the conductive substrate or the groove, and the conductive layer or the conductive layer is formed in a gap between the element forming layer and the polishing stopper layer; This is achieved by a semiconductor device formed using an SOI substrate having a buried conductive layer for electrically connecting a conductive substrate and the element formation layer.

The present invention is also achieved by the semiconductor device described above, wherein a lithographic alignment mark is formed on the polishing stopper layer or on the polishing stopper layer.

Further, a step of forming an element formation layer on the conductive layer or the conductive substrate via an insulating film, and a step of forming a groove reaching the conductive layer or the conductive substrate in the element formation layer and the insulating film. Forming a polishing stopper layer having a desired thickness with an area smaller than the bottom surface on the bottom surface of the groove, and a gap between the element forming layer and the polishing stopper layer being close to the polishing rate of the element forming layer and the polishing rate. The present invention is also attained by a method of manufacturing a semiconductor device including a step of forming a buried conductive layer made of a substance and a step of polishing the element forming layer to a thickness specified by the polishing stopper layer.

[Action]

According to the present invention, a conductive material is buried in a gap between a polishing stopper layer and an element forming layer to provide a connection portion for electrically connecting the element forming layer and a conductive layer below the insulating film. By applying a potential, an arbitrary potential can be given to the element formation layer.

As a result, during the manufacturing process, the charge-up phenomenon of the element formation layer at the time of high dose ion implantation can be prevented even if the element formation layer is thinned due to the presence of the connection portion.

Further, by forming a connection region between the conductive layer under the insulating film and the element formation layer simultaneously with the polishing stopper layer in the groove, the process can be shortened. Further, a decrease in the area of the element formation region on the support substrate is suppressed.

Further, by converting the conductive film of the connection portion into an insulating film after polishing, the interface of the element forming layer adjacent to the polishing stopper layer is stabilized, and improvement in element characteristics such as reduction in leakage current of the element is expected. it can.

Furthermore, when the conductive film of the connection portion is changed to an insulating film by oxidation, only the periphery of an arbitrary element forming layer is oxidized, so that the arbitrary element forming layer and the conductive layer below the insulating film can be insulated. .

Further, by forming the conductive film of the connection portion on the dicing line, the polishing stopper layer can be formed widely and uniformly on the substrate surface, so that a more stable connection portion can be formed.

In addition, by inserting alignment marks used in the photolithography process into the polishing stopper layer,
Since the polishing stopper layer remains even after the polishing, it is possible to accurately position the polishing stopper layer and each film formed after the polishing.

〔Example〕

Conductive layer 4 made of p-type silicon (p-Si) having a resistivity of 10 Ωcm
Over, an embodiment in which the thickness of the thickness 1μm silicon dioxide (SiC ₂₎ having a thickness of 3μm was formed through the insulating film 3 made of p-Si consists element type layer 2 to 3000Å First to fourth
Shown in the figure.

Further, a 30 μm thick insulating film 3 made of SiO ₂ having a thickness of 1 μm is formed on a conductive layer 4 made of p-Si having a resistivity of 10 Ωcm.
FIG. 5 shows an example in which the element formation layer 2 and the conductive layer 4 are connected to each other on the substrate on which the element formation layer 2 made of p-Si of 00 ° is formed by using p-type epitaxial Si.

FIGS. 1A to 1G are cross-sectional views of an embodiment in which the buried conductive film 5 at the connection portion is oxidized and the element forming region is surrounded by an insulating layer.

In FIG. 1 (a), an element forming layer 2 is formed on a conductive layer 4 with an insulating film 3 interposed therebetween. A groove is formed and the conductive layer 4 is exposed.

In FIG. 1B, a 1.3 μm-thick SiO ₂ film is used as a polishing stopper layer by using a vapor phase growth (CVD) method.
The film 1 is grown.

Next, the SiO ₂ film is left only at the bottom portion away from the side wall of the groove by ordinary lithography and reactive ion etching (RIE) using a fluorine-based gas, or wet etching.

The formation of the SiO ₂ film 1 as the polishing stopper layer may be achieved by growing polycrystalline silicon (poly Si) and oxidizing it.

In FIG. 1C, a p-type poly-Si film having a sheet resistance of 1 KΩ / □ is formed as a buried conductive film 5 for filling a gap (connection portion) between the element forming layer 2 and the polishing stopper layer 1 by a CVD method. It grows about 2 μm.

In FIG. 1D, the polishing stopper layer Si
The element formation layer 2 is polished using the O ₂ film 1 as a stopper.

As a result, the thickness of the element forming layer 2 is determined by the thickness of the polishing stopper layer 1, and is 3000 °.

Further, since the polishing stopper layer 1 is formed on the dicing line, the polishing stopper layer 1 can be uniformly arranged on the entire surface of the wafer, so that a thin film can be stably and highly accurately formed.

Using the substrate obtained as described above, an element is formed by a normal wafer process.

Here, an element can be formed in a state where the conductive layer 4 and the element forming layer 2 are electrically connected to the buried conductive film 5.

FIG. 1 (e) shows a case where the buried conductive film 5 is oxidized and a part of the buried conductive film 5 is changed to an insulating film 10 as an example of element formation.

In FIG. 1 (e), a MOS FET is formed by a normal MOS FET manufacturing process.

In the figure, 6 is a gate electrode, a poly-Si film, 7 is a gate oxide film, a thermally oxidized SiO ₂ film, 8 is an impurity introduction layer (source region), 9 is an impurity introduction layer (drain region), 10 is an insulating film, This is a film obtained by thermally oxidizing a part of the buried conductive film 5.

Next, FIG. 1 shows an embodiment in which a part of each element forming layer is connected to a conductive layer under an insulating film, and another element forming layer is insulated from a conductive layer under the insulating film. This will be described using f) and (g).

In this manner, the potential of each element formation layer can be changed.

For example, when a substrate with such a structure is applied to CMOS,
Different potentials can be applied to the p-channel side and the n-channel side, and the threshold voltage of the MOS FET can be controlled independently for the p-channel and the n-channel.

In FIG. 1 (f), after the element forming layer 2 is thinned as shown in FIG. 1 (d), a 1000 .ANG.
An N film 17 is grown, and an opening is formed in the peripheral portion of the element formation layer to be insulated from the conductive film below the insulating film by using lithography. The etching at this time is performed by dry etching using a fluorine-based gas.

1 (g), an SiO ₂ film 18 having a thickness of 6000 ° is formed by thermal oxidation using the SiN film 17 as a mask.

After that, the SiN film 17 is removed by wet etching.

The region covered with the SiN film 17 is not oxidized, and the conductive layer under the insulating film and the element forming layer remain electrically insulated.

Through the above steps, the conductive layer below the insulating film can be electrically connected to an arbitrary element formation layer.

FIGS. 2A to 2D are cross-sectional views of an embodiment in which the polishing stopper layer 1 is formed by lift-off of a resist.

In FIG. 2A, an element forming layer 2 is formed on a conductive layer 4 via an insulating film 3, and a groove is formed by dry etching using a chlorine-based gas or wet etching by a normal lithography process. Then, the conductive layer 4 is exposed.

In FIG. 2B, a resist film 11 is formed by lithography on the entire surface of the substrate except for the bottom of the groove. Also, instead of the resist film 11, phosphosilicate glass (PSG)
At the time of etching for lifting off the polishing stopper layer 1 such as a film, a film made of a material having a high selectivity with respect to the polishing stopper layer may be used.

In FIG. 2 (c), a 1.3 μm thick polishing stopper layer is formed on the entire surface of the substrate by anisotropic sputtering.
To form a SiO ₂ film.

The formation method may be any method other than the anisotropic sputtering, as long as the polishing stopper layer is not formed on the side walls of the grooves of the element forming layer 2 and the insulating film 3.

Thereafter, the polishing stopper layer on the resist is lifted off by removing the resist film 11, and the polishing stopper layer 1 is formed only at the groove bottom.

As a method for removing the resist film, wet processing using an aqueous solution of sulfuric acid can reduce the influence of dust generated by lift-off, as compared with dry processing.

In FIG. 2D, a p-type poly-Si layer having a sheet resistance of 1 KΩ / □ is formed by a CVD method as a buried conductive film 5 for filling a gap (connection portion) between the element forming layer 2 and the polishing stopper layer 1. It grows about 2 μm.

Next, the element formation layer 2 is polished using the SiO ₂ film 1 of the polishing stopper layer as a stopper.

As a result, the thickness of the element forming layer 2 is determined by the thickness of the polishing stopper layer 1, and is 3000 °.

Using the substrate formed as described above, element formation is performed, for example, in the same manner as in FIG.

FIGS. 3A to 3D are cross-sectional views of an embodiment in which the polishing stopper layer 1 is formed by a selective oxidation method.

In FIG. 3 (a), an element forming layer 2 is formed on a conductive layer 4 via an insulating film 3, and a groove is formed by dry etching using a chlorine-based gas or wet etching by a usual lithography process. Then, the conductive layer 4 is exposed.

In FIG. 3 (b), a p-type poly-Si film having a sheet resistance of 3 KΩ / □, which is to be the buried conductive film 5, is grown to a thickness of about 6500 mm by CVD, and a 1500-nm thick silicon nitride (SiN) Membrane 13
Grow.

Next, normal lithography and RI using fluorine-based gas
E or wet etching is used to remove the SiN film 13 only at the bottom portion away from the side wall of the groove.

Next, the poly-Si film 5 is thermally oxidized to form a 1.3 μm-thick SiO ₂ film to be the polishing stopper layer 1.

In FIG. 3 (c), after removing the SiN film 13 with hot phosphoric acid or the like, the gap (connection portion) between the element forming layer 2 and the polishing stopper layer 1 is filled and a sheet resistance of 3 KΩ /
A p-type poly-Si film 12 of □ is grown to a thickness of about 1 to 2 μm.

In FIG. 3D, the element forming layer 2 is polished using the polishing stopper layer 1 as a stopper.

As a result, the thickness of the element forming layer 2 is determined by the thickness of the polishing stopper layer 1, and is 3000 °.

Using the substrate formed as described above, element formation is performed, for example, in the same manner as in FIG.

4 (a) to 4 (d) are cross-sectional views of an embodiment in which the SiN film 14 is used as a polishing stopper layer and the insulating film 3 is etched using the SiN film 14 as a mask.

In FIG. 4 (a), an element forming layer 2 is formed on a conductive layer 4 via an insulating film 3, and is subjected to dry etching using a chlorine-based gas or wet etching by a usual lithography process. 2 is etched to form a groove, and the insulating film 3 is exposed.

In FIG. 4 (b), a 3000 mm thick Si
After growing the N film, the SiN film 14 is formed only on the bottom portion away from the side wall of the groove by ordinary lithography and dry etching using a chlorine-based gas, or wet etching using phosphoric acid or the like. Here, the SiN film 14 functions as a polishing stopper layer and serves as a mask when the insulating film 3 is etched.

Next, using the SiN film 14 as a mask, the insulating film 3 is etched by dry etching or wet etching using a fluorine-based gas to form a groove, and the conductive layer 4 is exposed.

In FIG. 4C, a p-type poly-Si film having a sheet resistance of 1 K.OMEGA./.quadrature. Serving as a buried conductive film 5 is grown to a thickness of about 2 .mu.m over the entire surface of the substrate by the CVD method.

In FIG. 4D, the element formation layer 2 is polished using the SiN film 14 serving as a polishing stopper layer as a stopper.

As a result, the thickness of the element forming layer 2 is determined by the thickness of the polishing stopper layer 14, and is 3000 °.

Using the substrate formed as described above, element formation is performed, for example, in the same manner as in FIG.

FIGS. 5A and 5B are cross-sectional views of an embodiment in which the element formation layer 2 and the conductive layer 4 are electrically connected by using the selective epitaxial method.

In FIG. 5 (a), an element forming layer 2 and an SiO ₂ film 16 serving as a growth mask are formed on a conductive layer 4 with an insulating film 3 interposed therebetween, and are dried using a normal lithography process and fluorine-based gas. Si by etching or wet etching
The O film 16 is etched, then the element formation layer 2 is etched by dry etching using a fluorine-based gas or wet etching, and the insulating film 3 is etched by dry etching or wet etching using a fluorine-based gas. Then, a groove is formed to expose the conductive layer 4.

In FIG. 5 (b), as a buried conductive film of the connection portion,
3,000mm thick, sheet resistance by selective epitaxial method
An epitaxial Si layer 15 of 1 KΩ / □ is grown in the trench, and then the SiO ₂ film 16 is removed by fluorine-based wet etching.

Using the substrate formed as described above, element formation is performed, for example, in the same manner as in FIG.

In the embodiment, an SiO ₂ film, SiN
Although a film is used, any material may be used as long as it has a high polishing stopper selectivity with the element formation layer 2. For example, a PSG film or a TiO film may be used.

In the embodiment, the poly-Si film is used as the buried conductive film. However, a conductive material having the same polishing rate as that of Si and having conductivity may be used. For example, single crystal Si, sputtered Si,
SiC may be used.

〔The invention's effect〕

According to the present invention as described above, the following effects can be obtained.

By applying a potential to the conductive layer below the insulating film, a potential can also be applied to the element formation layer.

Even when a potential is applied to the element formation layer, a decrease in the element formation region with respect to the substrate area can be suppressed.

By forming a connection region between the conductive layer below the insulating film and the element formation layer simultaneously with the polishing stopper layer, the process can be shortened.

Even if the element formation layer is thinned, it is possible to prevent charge-up during high dose ion implantation.

By converting the buried conductive film formed in the gap between the polishing stopper layer and the element formation layer into an insulating film after polishing, the interface of the element formation layer close to the polishing stopper layer is stabilized and the leakage current of the element is reduced. It is expected that the characteristics can be improved.

In the case where the buried conductive film is oxidized into an insulating film after polishing, by oxidizing only the periphery of an arbitrary element forming layer, the arbitrary element forming layer and the conductive layer below the insulating film can be insulated.

By forming the buried conductive film of the connection portion on the dicing line, the polishing stopper layer can be formed widely and uniformly on the substrate surface, so that more stable electrical connection can be formed.

When the positioning mark used in the photolithography process is provided in the polishing stopper layer, the polishing stopper layer remains even after the polishing, so that the polishing stopper layer and each film formed after the polishing can be accurately positioned.

[Brief description of the drawings]

1A to 1G are cross-sectional views of an embodiment in which a buried conductive film 5 of a connection portion is oxidized and an element forming region is surrounded by an insulating layer, and FIGS. 2A to 2D are polishing. 3 (a) to 3 (d) are cross-sectional views of an embodiment in which the stopper layer 1 is formed by lift-off of a resist, and FIGS. 3 (a) to 3 (d) are cross-sectional views of an embodiment in which the polishing stopper layer 1 is formed by selective oxidation. (D) as a polishing stopper layer
5 (a) and 5 (b) are cross-sectional views of an embodiment in which the insulating film 3 is etched using the SiN film 14 as a mask, and FIGS. It is sectional drawing of the Example electrically connected. In the figure, 1 is an SiO ₂ film as a polishing stopper layer, 2 is an element forming layer, 3 is an insulating film, 4 is a conductive layer, 5 is a poly-Si film as a buried conductive film of a connection portion, and 6 is a poly-Si film as a gate electrode. 7, a gate oxide film, a thermally oxidized SiO ₂ film, 8 an impurity introduction layer (source region), 9 an impurity introduction layer (drain region), 10 an insulating film obtained by thermally oxidizing a part of the buried conductive film, 11 is a resist film, 12 is a poly Si film, 13 is an SiN film as an oxidation resistant mask, 14 is a SiN film as a polishing stopper layer, 15 is an epitaxial Si layer as a buried conductive film at a connection portion, and 16 is a SiO ₂ film as a growth mask. It is a membrane.

Claims (5)

(57) [Claims] 1. An SOI substrate having an element formation layer disposed on a conductive layer or a conductive substrate via an insulating film, wherein the element formation layer and the insulating film extend from the conductive layer or the conductive substrate to the conductive layer or the conductive substrate. A polishing stopper layer having an area smaller than the bottom surface is formed on a bottom surface of the groove, and a gap between the element forming layer and the polishing stopper layer is formed between the conductive layer or the conductive substrate and the element formation layer. An SOI substrate having a buried conductive layer for electrically connecting layers. 2. A structure according to claim 1, wherein a structure in which said element forming layer is electrically connected to said conductive layer or conductive substrate is formed at least in a dicing line region.
SOI substrate. 3. A semiconductor device formed using an SOI substrate having an element formation layer provided on a conductive layer or a conductive substrate via an insulating film, wherein the element formation layer and the insulating film have A groove that reaches the conductive layer or the conductive substrate, a polishing stopper layer having an area smaller than the bottom surface is formed on a bottom surface of the groove, and a gap between the element forming layer and the polishing stopper layer includes the conductive layer or A semiconductor device formed using an SOI substrate having a buried conductive layer for electrically connecting the conductive substrate and the element formation layer. 4. The semiconductor device according to claim 3, wherein an alignment mark for lithography is formed on or on the polishing stopper layer according to claim 1. 5. A step of forming an element forming layer on a conductive layer or a conductive substrate via an insulating film, and forming a groove reaching the conductive layer or the conductive substrate in the element forming layer and the insulating film. Forming a polishing stopper layer having a desired thickness of an area smaller than the bottom surface on the bottom surface of the groove; and forming a polishing stopper layer between the element forming layer and the polishing stopper layer,
A semiconductor device comprising: a step of forming a buried conductive layer made of a material having a polishing rate close to that of the element forming layer; and a step of polishing the element forming layer to a thickness defined by the polishing stopper layer. Manufacturing method.