JP2798693B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device such as a digital camera that obtains a digitized video signal from a received video.

(B) Conventional technology In a CCD solid-state imaging device mounted on a solid-state imaging device, video information transferred and output for each pixel from a horizontal register of the CCD is accumulated in a capacitor and converted into a voltage value.
A video signal is obtained in which the video information level and the precharge level are alternately repeated. That is, when electrons are stored as video information, a capacitor provided at the output of the horizontal register is precharged to a predetermined level in advance in synchronization with the driving clock of the horizontal register, and the capacitor is discharged in accordance with the video information. Thus, a voltage corresponding to the video information can be obtained at both ends of the capacitor.

However, during the precharge operation as described above, the reference precharge level fluctuates due to noise mixed in the precharge pulse, noise of the power supply itself, and the like, and the video information level may fluctuate. Need to be removed.

A method of removing noise during the precharge operation is disclosed in Japanese Patent Publication No. Sho 62-55349, for example.

FIG. 6 is a block diagram showing a configuration of a solid-state imaging device including means for removing noise during a precharge operation;
FIG. 7 is a timing chart showing the operation. CCD
(1) Photoelectric charges generated by photoelectric conversion are accumulated as image information in a light receiving section for a certain period of time, this image information is transferred in the vertical direction, introduced into a horizontal register, and output for each horizontal line. At the output end of the horizontal register, there is provided an output section including a capacitor for converting the amount of electric charge as video information into a voltage value and a switching transistor for precharging the capacitor. In the output unit capacitor is precharged to the reference level E ₀ in the precharge period T _P, the video information in the discharge period T _D becomes that capacitor to be incorporated in the capacitor is discharged, the image information is the potential of the capacitor Level E is reached. Accordingly, the CCD (1) outputs a video signal X (t) as shown in FIG.

Video signal X (t) is input to the sample-and-hold circuit (2), the pulse width at the same period as the video signal X (t) is the video signal level E is sampled and held by the sampling pulse SP ₁ cycle T _P. And its hold output Y
₀ (t) is supplied to the inverting input of the differential amplifier (3).

The video signal X (t) is input to the sample-and-hold circuit (4), the reference level E ₀ at the sampling pulse SP ₂ which sampling pulses SP ₁ identical to the phase shifted by the period T _D is sampled and held. Then, the hold output Y ₁ (t) is further supplied to the sample hold circuit (5).
And supplied to it is sampled and held by the sampling pulse SP _1, the hold output Y ₂ (t) is a differential amplifier (3)
Is supplied to the non-inverting input of.

Here, each of the hold outputs Y ₀ (t), Y ₁ (t) and Y
_{2 The} pulses a, b and c appearing in (t) are error voltage components superimposed on the hold values in each of the sample and hold circuits (2), (4) and (5) due to the sampling signals SP ₁ and SP ₂ . Each of the pulses A, B and C has the same pulse width and peak value, respectively.

Hold output Y ₀ (t) of sample hold circuit (2)
Is the sum of the original video signal component and the noise component because it is the sampled value of the discharge period T _D , while the hold output Y ₁ (t) of the sample and hold circuit (4) is the pre-charge period T _P Since the sample value is only the noise component, the noise component can be removed by taking the difference between the two. Therefore, both hold outputs Y ₀ (t) and Y
To synchronize the phase of the ₁ (t) matches timing of Parusui and furnace, and a sample-hold depending on the sampling pulse SP ₁ hold output Y ₁ (t) of the sample and hold circuit (5). Therefore, the output Z (t) of the differential amplifier (3) is equal to the sampling pulses SP ₁ and SP ₂
Are obtained from which the error component and the noise component due to are removed.

The output Z (t) is subjected to processing such as gamma correction and gain adjustment by a signal processing circuit (6), and then converted to a digital signal D by an A / D conversion circuit (7) and output to an external device. Is done.

(C) Problems to be Solved by the Invention In the solid-state imaging device as described above, a video signal is created by extracting only a video information level from a video signal in which a precharge level and a video information level are alternately repeated,
The video signal is configured to be converted into digital data, and complicated signal processing is performed on the image signal. For this reason, the circuit configuration of the signal processing portion becomes complicated, and configuring them on a printed board using analog switches, capacitors, and the like is disadvantageous for miniaturization and increases the cost of the device.

Therefore, an object of the present invention is to provide an inexpensive, high-performance solid-state imaging device with a simplified circuit configuration without impairing the performance of a signal processing portion.

(D) Means for Solving the Problems The present invention is for solving the above-mentioned problems, and the photoelectric charge generated in the light receiving portion by photoelectric conversion is transferred in the vertical direction as video information and introduced into the horizontal register. A solid-state imaging device for obtaining a video signal which is transferred in a horizontal direction for each horizontal line and alternately repeats a video information level and a reference level. The reference level of the video signal is set to a first level in synchronization with a drive clock of the horizontal register. The first to fix to the level of
Clamp circuit for fixing the video information level to the second level for a specific period indicating the black level of the video signal.
An analog-to-digital conversion circuit that converts the video signal, in which the reference level and the video information level in a specific period are fixed at predetermined levels, to a digital signal in synchronization with a driving clock of the horizontal register, A digitized video signal is obtained from the video received by the solid-state imaging device.

(E) Operation According to the present invention, the reference level is fixed by the first clamp circuit for the video signal obtained by alternately repeating the reference level and the video signal level obtained from the solid-state imaging device. After the video signal level representing the black level is fixed by the clamp circuit, the video signal is converted into a digital signal, so that the processing of the video signal is simplified and the configuration is simplified.

Also, by setting the reference voltage of the analog / digital conversion circuit between the black level and the maximum level of the video signal,
The conversion range of the video signal in the analog-to-digital conversion circuit can be effectively used, and the gain of the video signal can be automatically adjusted.

(F) Example An example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the solid-state imaging device of the present invention, and FIG. 2 is a timing chart showing the operation thereof.
CCD (11) is Figure 6 as well as the reference level E ₀ in the precharge period T _P, discharge period T and outputs a video signal X (t) as the video information level E at _D, the video signal X (t ) Is supplied to the first clamp circuit (12). The first clamp circuit (1
The 2), synchronized with the video signal X (t), the clock CK having a pulse width of the precharge period T _P is input as a clamping pulse, a reference level E ₀ is a constant level precharge period T _P E ₁ Fixed to This first clamp circuit (1
In at clamp 2) is clamped to the video signal X (t) is the reference level E ₀ and the reference level E ₀ is the level E _A since it represents the video information by the difference between the video information level E when the video information level E Is also varied by E ₀ −E _A , and the reference level
The difference between E ₀ and the video information level E is configured to be equal before and after the clamp. Thus, clamp output Y of the first clamp circuit (12) (t) is, CCD (11) variations in at the reference level E ₀ in the output portion of the correction, and the reference level E ₀ and the video information level E The difference is kept at the value before clamping. Then, the clamp output Y (t) is supplied to the inverting amplifier (13), and the inverted output Y '(t) is
It is supplied to the clamp circuit (14). The second clamp circuit (14), "1" and the signal OB and the inverted clock CK is supplied to the OPB period, these clamp pulse CL is produced from the video information level OPB period is a predetermined level V _B Fixed. The OPB period is for setting a black level of video information, and is generally obtained based on video information transferred and output from a light shielding area provided at an end of a light receiving section of the CCD (11). Therefore, the video signal X (t) has video information continuous in units of horizontal lines, and has an OPB period between each horizontal line, that is, at both ends of a retrace period of the plain search line. And the second
Clamp output Z of the clamping circuit (14) (t) is supplied to the A / D converter (15) is converted into a digital signal D _1. The A / D conversion circuit (15) is supplied with the inverted clock CK, and outputs the output Z (t) at the rising timing of the clock CK.
Is taken into the A / D conversion circuit (15). Also, the reference voltage V _L of the low voltage side of the A / D converter (15) is given clamp level E _B of the second clamp circuit (14), the reference voltage V _H of the high-voltage side, one screen Minute signal Z (t)
The maximum level of the video information level is given. This maximum level is determined by the signal Z
It is obtained by holding the maximum level of (t). Therefore, the reference voltage of the A / D conversion circuit (15) is
(T) is set between the black level and the highest level,
The conversion range of the analog signal in the A / D conversion circuit (15) can be fully utilized, and the resolution of the A / D conversion circuit (15) increases.

Then, the digital signal D output from the A / D conversion circuit (15)
₁ processing such as gamma correction by the signal processing circuit (17) is applied, the output digital signal D ₂ is outputted to the external device.
This signal processing circuit (17) to the gamma correction in the digital signal D ₁ is present applicant can be adopted "digital correction circuit" of the proposed in Japanese Patent Application Sho 62-263009.

 Next, the configuration of each unit will be described.

FIG. 3 is a circuit diagram of each block, (a) is a first clamp circuit (12), (b) is a second clamp circuit (14),
(C) shows each of the peak hold circuits (16).

The first clamp circuit (12) is composed of two capacitors (21)
(22) and switch (23), and the input signal X
(T) is output as a signal Y (t) via the capacitor (21). The output side of this capacitor (21) is grounded via a switch (23) and a capacitor (22), and when the switch (23) is turned on according to the clock CK, the output side of the capacitor (21) is connected to the capacitor (22). It is configured to be fixed to a potential. Between the switch (23) and a capacitor (22) resistor is supplied a potential power supply voltage is divided by a (24), the clamp potential E _A is set depending on the potential. Thus, the clock CK is output "1" when it comes to the capacitor switch (23) is turned on (21) is set to the potential E _A, signal X when the clock CK is switched (23) becomes "0" is turned off The variation of (t) appears in the potential variation on the output side of the capacitor (21).

The second clamp circuit (14) has the same configuration as the first clamp circuit (12), and includes two capacitors (25).
(26) and a switch (27). The clamp pulse CL that controls the on / off of the switch (27)
Given by a logical sum (28) of the B period and a signal OB "1" and the inverted clock CK, the signal Y 'black level OPB period (t) is fixed to the clamp potential E _B. The clamp potential E _B, similar to the first clamp circuit (12) resistance (2
The power supply voltage is divided according to 9) and given.
The clamp potential E _B is outputted as the reference voltage V _L of the A / D converter (15). Thus, the output side of the switch (27) period capacitor is on (25) is fixed to the clamp potential E _A.

The peak hold circuit (16) is composed of two transistors (30) and (31), a diode (32), a resistor (33) and a capacitor (34), and a second clamp is applied to the transistor (30) connected in an emitter follower type. Upon receiving the clamp output Z (t) of the circuit (14), the emitter of the transistor (30) is connected to the capacitor (34) via a forward diode (32) and a resistor (33) in parallel. The impedance conversion depending on Kodensa connected transistor potential of (34) to the emitter follower (31), and outputs a reference voltage V _H of the A / D converter (15). That is, the capacitor (34) is charged according to the level of the signal Z (t), and if the resistor (33) is set to a high resistance, the capacitor (34) becomes difficult to discharge.
Is equal to the maximum level of the signal Z (t). Accordingly, in the maximum level of the signal Z (t) it is held, the held value is provided to the reference voltage V _H of the A / D converter (15).

FIG. 4 is a circuit diagram showing the configuration of the A / D conversion circuit (15), and FIG. 5 is a timing chart showing the operation thereof. A /
The D conversion circuit (15) is a multiple comparison circuit (C ₁ ) (C ₂ ) ...
(C _n ), and each comparison circuit (C ₁ ) (C ₂ ) ... (Cn)
Is decoded by a decoder (40) to obtain a digital signal D. Each of the comparison circuits (C ₁ ) (C ₂ ) ... (C _n )
The signal Z (t), the comparison voltages V _{R1 to} V _Rn and the clock CK are input, and the comparison voltage is applied at the falling timing of the clock CK.
V _{R1 to} V _Rn are taken into the comparison circuits (C ₁ ) (C ₂ )... (Cn), and the potential of the signal Z (t) is taken in at the rising timing of the clock CK. The comparison voltages V _{R1 to} V _Rn are obtained by equally dividing the range from the reference voltages _VL to V _H by the resistance (R), and change in a constant step from the comparison voltages V _{R1 to} V _Rn . Each of the comparison circuits (C ₁ ) (C ₂ )... (Cn) has the same configuration, and includes three switches (51) (52) (53), a capacitor (54), an inverter (55), and a flip-flop (56). )
Consists of First, at the rising edge of the clock CK, the switches (52) and (53) are turned on, the comparison voltages V _{R1 to} V _Rn are taken in, the capacitor (54) is charged, and the inverter (55) and the switch (53) are connected. The comparison voltages V _{R1 to} V _Rn are stored, and then the switch (51) is turned on and the switch (52) at the rising of the inverted clock CK, that is, at the falling of the clock CK.
Is turned off, the signal Z (t) is taken in, and the capacitor (5
The switch (53) is turned off at the same time that 4) is charged. At this time, if the potential charged in the capacitor (54) is higher than the voltage stored in the inverter (55) and the switch (53), the output of the inverter (55) becomes "0"; Becomes Then, at the timing when the clock CK rises again, the output of the inverter (55) is taken into the flip-flop (56) and outputted to the decoder (40). Here, since the output of the inverter (55) is delayed from the clock CK depending on the delay amount of the inverter (55) itself and the capacitor (54), the flip-flop (56)
There comparison result output will be obtained at the end in the signal Z (t) a little earlier timing than the fall, i.e. the discharge period T _D of the signal Z (t). The signal Z (t) may be superimposed with the clamp noise in the clamp circuits (12) and (14) as shown by the broken line in FIG.
Since (14) is a capacitor, for clamping noise generated in switching timing of the switching of the clamp circuit (12) (14) is made to decay as time elapses, the clamp at the end of the discharge period T _D The effect of noise is reduced. Therefore, the clamp noise superimposed on the signals Y (t) and Z (t) by the clamp circuits (12) and (14) is removed by the A / D conversion circuit (15).

In the A / D converter (15), since the conversion range of the analog signal is set between the reference voltage V _L to V _H, reference voltage the black level of the signal Z (t) V _L
And the maximum level of the signal Z (t) is set to the reference voltage V _H
Then, the A / D conversion circuit (15) can be operated effectively.

Further, the signal Z is output by the peak hold circuit (16) as described above.
Hold the maximum level of (t) and set the reference voltage V _H
To the signal Z in the A / D conversion circuit (15).
The gain adjustment of (t) can be automatically performed (AGC processing). That is, when the level of the signal Z (t) decreases, the reference voltage V _H decreases, and the reference voltage V _L
Each comparator circuit to the difference between V _H decreases _{(C 1) (C 2)} ...
The step of change of the comparison voltages V _{R1 to} V _Rn given to (Cn) becomes smaller, and the input to the decoder (40) changes with a small change of the signal Z (t). Conversely, signal Z
When the level of (t) increases, the reference voltages _VL and _VH
, The step of change of the comparison voltages V _{R1 to} V _Rn increases, and the input to the decoder (40) does not change with a small change of the signal Z (t).

It is also possible to white level adjustment (white clip) performed on the signal Z (t) depending on fixing the reference voltage V _H of the A / D converter (15) to a particular level.

According to the above configuration, the reference level and the black level are fixed to the video signal X (t) obtained from the CCD (11), and further, the adjustment of the gain and the like are applied to the characteristics of the A / D conversion circuit (15). Since the configuration is such that the signal processing is performed together, the signal processing circuit can have an extremely simple configuration.

(G) Effects of the Invention According to the present invention, video signal processing is performed using an extremely simple clamp circuit that can be configured by a capacitor and a switch, so that the circuit configuration of the signal processing portion is simplified without impairing the performance. It is possible to provide an inexpensive and high-performance imaging device.

[Brief description of the drawings]

1 to 5 relate to the present invention, FIG. 1 is a block diagram, FIG. 2 is a timing diagram, FIG. 3 is a circuit diagram of each part, FIG. 4 is a circuit diagram of an A / D conversion circuit, FIG. FIG. 5 is an operation timing chart of the A / D conversion circuit. FIG. 6 is a block diagram of a conventional solid-state imaging device, and FIG. 7 is a timing chart. (1) (11) ... CCD, (2) (4) (5) ... sample hold circuit, (3) ... differential amplifier, (6) (17)
…… Signal processing circuit, (7) (15) …… A / D conversion circuit, (1
2) (14) ... Clamp circuit, (16) Peak hold circuit.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/30-5/335

Claims (1)

(57) [Claims] An optical charge generated in a light receiving section by photoelectric conversion is vertically transferred as video information and introduced into a horizontal register, and is also transferred in a horizontal direction for each horizontal line, and a video information level and a reference level are determined. A solid-state imaging device that obtains a video signal that is alternately repeated; a first clamp circuit that fixes a reference level of the video signal to a first level in synchronization with a transfer operation of the horizontal register; A second clamp circuit for fixing the video information level of the video signal to a second level during a period of time; a peak hold circuit for holding a maximum value of the video information level of the video signal at least for each screen; The low potential side is set according to the video information level of the video signal fixed in the second clamp circuit during a specific period, and the reference voltage The high potential side is set in accordance with the hold level of the peak hold circuit, and the video signal whose reference level and video information level in a specific period are fixed to predetermined levels, respectively, is superimposed with the clamp noise by the first clamp circuit. An analog-to-digital conversion circuit that takes in at a timing excluding a period during which the image is captured and sequentially converts it into a digital signal, and obtains a digitized video signal from the video received by the solid-state imaging device.