JP2798318B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a thin film transistor (TFT).
ilm Transistor).

[0002]

2. Description of the Related Art FIG. 6 is a process sectional view showing a manufacturing process of a conventional semiconductor device (TFT).
Reference numeral 0 denotes a substrate, on which an interlayer insulating film 1 is provided. On the interlayer insulating film 1, a gate electrode 2 obtained by patterning polycrystalline silicon is arranged. Reference numeral 4 denotes polycrystalline silicon which is formed via the gate oxide film 3 and serves as a source, a drain, and a channel of the TFT, and has N-type conductivity here. Reference numeral 5 denotes a channel, 8 denotes a source, and 9 denotes a drain.
Reference numeral 6 denotes a photosensitive resin serving as a mask when boron 7 is injected into the polycrystalline silicon 4.

Next, a manufacturing method will be described. First, FIG.
As shown in (a), after depositing the interlayer insulating film 1 on the entire surface of the substrate 100 by using an oxide film or the like by using the CVD method, polycrystalline silicon is deposited by using the CVD method. Then, a photosensitive resin (not shown) is pattern-formed on the polycrystalline silicon, and the gate electrode 2 is formed by performing anisotropic etching. Next, the gate oxide film 3 is deposited by a CVD oxide film or the like, and the polycrystalline silicon 4 serving as the source, channel and drain of the transistor is deposited by the CVD method.

Next, as shown in FIG. 6B, in the case of a P-channel transistor, a channel portion 5 is covered with a photosensitive resin 6 and a P-type impurity such as boron 7 is implanted. Thereafter, the photosensitive resin 6 is removed to form a source 8 and a drain 9 as shown in FIG. 6C, thereby obtaining a P-type conductive TFT.

[0005]

Since the conventional semiconductor device and the method of manufacturing the same are constructed as described above, in forming the mask for forming the source / drain regions, the masking of the gate electrode and the channel portion is performed. The occurrence of the offset causes a source-drain offset, which causes a problem in that the operation characteristics are affected.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same which can reduce the source / drain offset and simplify the manufacturing process. I do.

[0007]

A semiconductor device according to the present invention is provided.
The method of manufacturing the device is such that a second conductive type impurity is implanted into the first conductive type polycrystalline silicon using a mask formed at a step formed by a gate electrode of the first conductive type polycrystalline silicon. The mold is inverted to form a channel region having a longer channel length than the gate electrode.

Further, a first first conductivity type semiconductor layer, a gate insulating film, and a second first conductivity type semiconductor layer are sequentially laminated on the insulating film, and a mask is provided to implant a second conductivity type impurity. Then, the conductivity type of the predetermined portion of the first first conductivity type semiconductor layer is inverted to form a gate electrode, and the second conductivity type impurity is implanted to perform the predetermined portion of the second first conductivity type semiconductor layer. The channel type is formed by inverting the conductivity type.

In addition, a semiconductor layer is formed on the insulating film, an oxidation-resistant mask is provided in a predetermined region of the semiconductor layer, and oxidized to form a gate electrode below the oxidation-resistant mask. And a gate insulating film covering the gate electrode is formed by an oxidation-resistant mask.

[0010]

According to the present invention, the impurity is implanted by providing a mask in a portion to be the source / drain region of the polycrystalline silicon layer by utilizing a step formed by the gate electrode of the polycrystalline silicon layer. Is covered by the channel, and the alignment between the gate electrode and the channel region can be performed in a self-aligned manner.

A first semiconductor layer of the first conductivity type, a gate insulating film, and a second semiconductor layer of the first conductivity type are sequentially laminated on the insulating film, and the second semiconductor layer is formed using a mask. A conductivity type impurity is implanted in two stages to invert the conductivity type, thereby forming a gate electrode in the first semiconductor layer of the first conductivity type and a channel region in the semiconductor layer of the second first conductivity type. Thus, the gate electrode and the channel region can be formed using the same mask, the alignment can be easily performed by self-alignment, and the manufacturing process can be simplified.

An oxidation resistant mask is provided in a predetermined region of the semiconductor layer on the insulating film, and oxidized to form a gate electrode below the oxidation resistant mask, and the gate electrode is formed by the oxidized semiconductor layer and the oxidation resistant mask. Is formed, the gate electrode and the gate insulating film can be obtained at the same time, and the process can be simplified.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, FIG.
The same reference numerals denote the same or corresponding parts, 10 denotes a photosensitive resin formed on the entire surface of the polycrystalline silicon 4, and 11 denotes arsenic. Here, a P-type polycrystalline silicon 4 is used.

Next, the manufacturing method will be described. First, as shown in FIG. 1A, an interlayer insulating film 1 is deposited on a substrate 100 by a CVD oxide film or the like in the same manner as in the prior art, and then polycrystalline silicon 2 is deposited at 2000 to 3000 angstroms by a CVD method. Then, a photosensitive resin (not shown) is provided on the polycrystalline silicon 2 to form a pattern, and the gate electrode 2 is formed by performing anisotropic etching.
Next, the gate oxide film 3 is deposited at 200 to 300 angstroms by CVD, and then the source
P-type polycrystalline silicon 4 serving as a channel / drain is replaced with C
Deposit 100 to 200 angstroms by VD method.

Next, as shown in FIG. 1B, the photosensitive resin 10 is coated on the entire surface with a thickness of 15,000 to 20,000 angstroms, and then anisotropically etched with O ₂ or the like.
At this time, the photosensitive resin 10 remains only in the source 8 and the drain 9 and the etching is completed in a time that does not cover the channel 5.

Next, as shown in FIG. 1C, arsenic 11, which is an N-type impurity, is implanted. At this time, since the region of the polycrystalline silicon 4 serving as the source / drain is covered with the etched photosensitive resin 10a, arsenic
1 is injected.

[0017] Finally, as shown in FIG. 1 (d), the photosensitive resin 10a is removed by etching such as O _2, 900 ℃,
By performing the driving for 1 to 1.5 hours, an N-type channel 5 is formed.

As described above, according to the present embodiment, the step between the channel of the polycrystalline silicon 4 and the source / drain is utilized,
Arsenic 11 while leaving photosensitive resin 10a at the source / drain
, The length of the channel region 5 becomes substantially equal to the distance in the step portion of the polycrystalline silicon 4 formed on the gate electrode 2, and the gate electrode 2 and the channel 5 can be aligned in a self-aligned manner. The length of the channel 5 is longer than that of the gate electrode 2, so that there is no offset between the gate electrode 2 and the source 8 or the drain 9 or imbalance between left and right.

Next, a second embodiment of the present invention will be described. In the first embodiment, the arsenic 11 is selectively injected by the photosensitive resin 10a.
Arsenic is implanted using a silicon oxide film such as BPSG instead of a. This embodiment will be described with reference to FIG. 2. In this embodiment, as shown in FIG. 2A, an interlayer insulating film 1, a gate electrode 2, a gate oxide film 3, A mold polycrystalline silicon 4 is formed.

Next, as shown in FIG. 2B, the BPSG film 1
2 is deposited by CVD at about 10000 angstroms, and is heat-treated at 900 ° C. for about 30 minutes to perform flattening. Next, this BPSG film 12 is coated with an HF solution (15:
1) Etching, etc., and BPSG as shown in FIG.
The film 12 remains only at the source 8 and the drain 9 of the polycrystalline silicon 4, and the etching is completed in a time that does not cover the channel 5. Using the remaining BPSG film 12a as a mask, arsenic 11, which is an N-type impurity, is implanted to form a source 8, a drain 9, and a channel 5 of the TFT as shown in FIG.
To form

According to this embodiment, the source / drain portion is formed by utilizing the step between the channel 5 and the source / drain.
Leaving the PSG film 12a, because it was so that the ion implantation as a mask, it is possible to adjust the channel position in the gate electrode and the self-aligned, the source and Chi catcher channel
The offset of the drain and the imbalance between the left and right are not caused, and the step between the channel 5 and the source 8 and the drain 9 can be filled with the mask at the time of ion implantation to improve the flatness. It is not necessary to remove the mask at the time of ion implantation in a later process, and the manufacturing process can be simplified.

Next, a third embodiment of the present invention will be described. In this embodiment, SO 2 is used as a mask during ion implantation.
The G film is used. Referring to FIG. 3, first, as shown in FIG. 3A, the interlayer insulating film 1, gate electrode 2, gate oxide film 3, P A mold polycrystalline silicon 4 is formed.

Next, an SOG film 13 is applied to the entire surface of the substrate by a spin coating method. At this time, the SOG film 13 is formed thicker in the stepped recess and thinner in the projecting portion on the substrate, so that the step caused by the gate 2 of the polycrystalline silicon 4 is reduced as shown in FIG. Further, heat treatment is performed at 850 ° C. for about 20 minutes. At this time, SOG is applied to channel 5 above the step.
The film 13 is applied only on the order of 100 angstroms.

Next, as shown in FIG.
Arsenic 11 is implanted using
Arsenic is implanted only into the channel 5 where the film 13 is thin. Finally, by driving at 900 ° C. for 1 to 1.5 hours, an N-type channel 5 is formed as shown in FIG.

By doing so, the same effect as in the first embodiment can be expected, and the step of reflowing the flattening film as in the BPSG film of the second embodiment can be omitted. As a result, the manufacturing process can be simplified.

Next, a fourth embodiment of the present invention will be described. In the above-described embodiment, the channel is formed by the gate and the self-alignment using the step of the source 8 and the drain 9. However, the gate and the channel may be formed by one pattern formation. That is, in FIG. 4, reference numeral 14 denotes a P-type epitaxial silicon layer, reference numeral 15 denotes a photosensitive resin, and reference numeral 16 denotes phosphorus. In this embodiment, first, as shown in FIG.
P-type epitaxial silicon layer 1 on interlayer insulating film 1
4 is formed at 2000 to 3000 angstroms. Next, the gate oxide film 3 and the P-type polycrystalline silicon 4 are sequentially deposited. Next, a photosensitive resin 15 having a channel 5 opened is formed in a pattern, and phosphorus 16 is injected at a high acceleration of about 100 to 200 KeV to form a P-type epitaxial layer.
A region 16a is formed in the silicon layer 14 into which phosphorus 16 which is an N-type impurity is implanted.

Next, as shown in FIG.
5 while leaving the arsenic 11 at 10-20 Ke.
By implanting at a low acceleration of about V, a region 11a in which arsenic 11 is implanted in P-type polycrystalline silicon 4 is formed.

Finally, as shown in FIG. 4C, the photosensitive resin 15 is removed with O ₂ or the like, and driving is performed at 900 ° C. for 1 to 1.5 hours to form an N-type silicon gate electrode 2. And the channel 5 are formed at the same time.

According to this embodiment, since the gate electrode is formed in the P-type silicon film 14 epitaxially grown, the gate electrode 2 and the channel 5 are formed by one patterning of the photosensitive resin. The flatness can be improved and the manufacturing process can be simplified.

Next, a fifth embodiment of the present invention will be described. In this embodiment, the alignment between the gate electrode and the channel is performed in a self-aligned manner, and the gate electrode and the gate insulating film are simultaneously formed. This will be described below with reference to FIG. 5. In FIG. 5, reference numeral 20 denotes polycrystalline silicon formed on the entire surface of the interlayer insulating film 1;
Is a silicon nitride film that becomes a part of the gate insulating film, and 18 is a silicon oxide film obtained by oxidizing the polycrystalline silicon 2. The nitride film 17 and the silicon oxide film 18 form a gate insulating film. I have.

Next, the manufacturing method will be described. First, as shown in FIG. 5A, a polycrystalline silicon 20 is formed on the interlayer insulating film 1 formed on the substrate 100 by the CVD method.
After 3000 Å deposition, the entire surface of the silicon nitride film is deposited by CVD. Then, by patterning a photosensitive resin (not shown) covering the gate electrode region and performing anisotropic etching, a silicon nitride film 17 to be a part of the gate insulating film is formed.

Next, as shown in FIG. 5B, the polycrystalline silicon 20 is thermally oxidized, so that the portion of the polycrystalline silicon 20 not covered with the silicon nitride film 17 becomes the silicon oxide film 18 and the silicon nitride film 18 is formed. The polycrystalline silicon 20 covered by the film 17 becomes the gate electrode 2 without being oxidized. As a result, the gate electrode 2 is covered with the insulating film.

Next, as shown in FIG. 5C, N-type polycrystalline silicon 4 is deposited on the silicon nitride film 17 and the silicon oxide film 18 by 100 to 200 angstroms by CVD. Next, as shown in FIG. 5D, the photosensitive resin is left only in the source / drain regions 8 and 9 (10a) as in the first embodiment of FIG. inject. Then, as shown in FIG. 5E, the photosensitive resin 10a is removed to form a source 8 and a drain 9.

According to this embodiment, the silicon nitride film 17
The gate electrode 2 and the gate insulating film can be simultaneously formed by oxidizing the polycrystalline silicon 20 with the mask as a mask, the flatness can be improved, and the step of depositing the gate oxide film can be omitted. Can be simplified.

In each of the above embodiments, it goes without saying that the conductivity type of each semiconductor layer may be reversed.

[0036]

As described above, according to the present invention, a mask is provided in a portion to be a source / drain region of a polycrystalline silicon layer by utilizing a step formed by a gate electrode of the polycrystalline silicon layer to perform impurity implantation. Since it is performed, the alignment between the gate electrode and the channel region can be accurately performed in a self-aligned manner, and a semiconductor device having excellent operation characteristics can be efficiently obtained without causing offset between the source and the drain. This has the effect.

Further, by using a silicon oxide film such as BPSG as the mask, it is possible to simultaneously perform a process for filling a step between a channel and a source / drain.

Further, by using the SOG film as the mask, the flatness of the step can be improved, the etching step for flattening can be omitted, and the manufacturing process can be simplified. There is.

Further, a first first conductivity type semiconductor layer, a gate insulating film, and a second first conductivity type semiconductor layer are sequentially laminated on the insulating film, and the second first conductivity type semiconductor layer is formed using a mask. The conductivity type impurity is implanted in two stages to invert the conductivity type to form the gate electrode and the channel region. Therefore, the gate electrode and the channel are positioned at predetermined positions by one mask pattern formation. There is an effect that it can be formed with high accuracy, the flatness can be improved, and the manufacturing process can be simplified.

Further, since the gate electrode and the gate insulating film are formed simultaneously by selectively oxidizing the polycrystalline silicon using the oxidation-resistant mask, the step of depositing the gate oxide film can be omitted. effective.

[Brief description of the drawings]

FIG. 1 is a view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a view showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a view showing a manufacturing process of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a process sectional view illustrating a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 interlayer insulating film 2 polycrystalline silicon gate electrode 3 silicon oxide film 4 polycrystalline silicon 5 channel 8 source 9 drain 10 photosensitive resin 10a remaining photosensitive resin 11 arsenic 11a arsenic implanted region 12 BPSG film 12a remaining BPSG film 12a Film 13 SOG film 14 Silicon layer epitaxially grown 16 Phosphorus 16a Phosphorus-implanted region 17 Silicon nitride film 20 Polycrystalline silicon 100 Substrate

Claims (4)

(57) [Claims] 1. A process for forming a gate electrode via an insulating film.
And a polycrystalline silicon layer on the gate electrode via a gate insulating film.
Forming a recon layer, using a mask on the polycrystalline silicon layer;
Conductivity different from the source / drain regions
Forming a channel region of a mold type
Manufacturing method, a first conductivity type polycrystalline silicon film formed via a gate insulating film is formed.
A gate electrode of the first conductivity type is formed on the silicon layer by a gate electrode.
Resist to cover the step formed in the polycrystalline silicon layer.
Depositing the resist and etching the resist so that the polysilicon layer
Resist only in the concave part of the step part that becomes the source / drain region.
And a step of using the resist remaining in the concave portion of the step portion as a mask.
Two-conductivity-type impurity implantation is performed, and the polycrystalline silicon layer is implanted.
A channel length longer than the above gate electrode width is set in the step
The method of manufacturing a semiconductor device which comprises a step of forming a channel region having. A gate electrode formed on the insulating film;
Polycrystal formed on gate electrode via gate insulating film
A silicon layer, and a source
Form a channel region of different conductivity type from the rain region
In the semiconductor device comprising said first conductivity type semiconductor layer formed on the insulating film, and said semiconductor gate insulating formed on layer film, the first conductivity type formed on the gate insulating film multi Crystal silicon
A gate electrode , wherein the gate electrode is formed on the polycrystalline silicon layer of the first conductivity type,
Using a mask having an opening in the region of the second conductivity type
A predetermined region of the first conductivity type polycrystalline silicon layer.
The channel region is formed by inverting the region to the second conductivity type. The channel region is formed by injecting a second conductivity type impurity using the mask.
A predetermined region of the semiconductor layer of the first conductivity type is inverted to the second conductivity type.
Semiconductor device characterized by being formed by
Place. 3. A process for forming a gate electrode via an insulating film.
And a polycrystalline silicon layer on the gate electrode via a gate insulating film.
Forming a recon layer, using a mask on the polycrystalline silicon layer;
Conductivity different from the source / drain regions
Forming a channel region of a mold type
In the method of manufacturing, a semiconductor layer of the first conductivity type, a gate insulating film,
Sequentially laminating a crystalline silicon layer, and having an opening in a predetermined region on the polycrystalline silicon layer.
A mask is provided, and impurities of the second conductivity type are implanted.
A predetermined region of the semiconductor layer of the first conductivity type is inverted to the second conductivity type.
Forming a gate electrode, and implanting impurities of the second conductivity type using the mask,
A predetermined region of the polycrystalline silicon layer is inverted to the second conductivity type.
The method of manufacturing a semiconductor device characterized by not including a step of forming a channel region. 4. A method for manufacturing a semiconductor device according to claim 1, wherein
Oite, forming a gate electrode through the gate insulating film
Forms polycrystalline silicon on a substrate, and
Forming an oxidation-resistant mask on a predetermined portion of the substrate; and performing thermal oxidation using the oxidation-resistant mask,
The gate electrode is removed by leaving polycrystalline silicon under the mask.
And the oxidation resistant mask and the thermal oxidation
The part changed to the oxide film of polycrystalline silicon
Forming a gate insulating film covering the gate electrode .