JP2798276B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a DRAM capacitor and a method for manufacturing the same.

[Conventional technology]

In recent years, miniaturization of memory cells has been progressing with high integration. In addition, as memory cells are miniaturized, the area of a capacitor is reduced, and a soft error due to a reduction in capacitance has become a problem. In order to solve this problem, structures such as a trench capacitor and a multilayer capacitor (stacked capacitor) have been proposed.

On the other hand, recently, a wafer bonding technology for annealing and bonding two silicon wafers in a high-temperature atmosphere and a concentration difference etching technology for selectively etching a bonded wafer according to an impurity concentration to reduce the thickness have been developed. Was.

3 (a) to 3 (d) show a method of manufacturing a semiconductor memory using a conventional capacitor called a trench type capacitor as a capacitor.
It has an SOI structure, and in the case of a normal Tr structure, it can be considered that there is no underlying insulating film 102.

In FIG. 3A, 101 is a semiconductor substrate, 102 is a base insulating film, and 103 is a single crystal semiconductor (SO
I) layer. The base insulating film 102 is obtained by depositing on the semiconductor substrate 101 or oxidizing the semiconductor substrate 101. The single-crystal semiconductor layer 103 is obtained by melting and recrystallizing a polycrystalline or amorphous semiconductor layer deposited on the insulating film 102 by irradiating with an energy beam or heating with a heater, a lamp, or the like, or forming an amorphous layer to form a solid phase. Or by attaching a single crystal substrate or by forming a seed region and epitaxially growing in the lateral direction. As a method for simultaneously forming the base insulating film 102 and the single crystal semiconductor layer 103, the semiconductor substrate 1
A method of obtaining a compound insulating film layer by implanting ions that form an insulating film by combining with the semiconductor material in 01 and performing high-temperature annealing is also conceivable. For example, when the semiconductor substrate 101 is silicon, oxygen ions of about 200 KeV and 1 × 10 ¹⁸ / cm ² or more are implanted to form underlying silicon oxide films 102 and 10 of about 500 nm.
SIMOX that a single crystal silicon layer 103 of 0 to 200 nm can be obtained
(Separation by IMplanted OXygen) widely known as technology.

Next, in FIG. 1B, reference numeral 104 denotes an insulating film for separating elements, 105 denotes a trench hole, 106 denotes a gate insulating film of a switching transistor, and 107 denotes a dielectric film of a trench capacitor. Isolation between elements is performed by selective oxidation. The trench hole 105 is formed by anisotropic etching. The gate insulating film 106 and the capacitor dielectric film 107 are formed by oxidation or the like.

Next, as shown in FIG. 3C, a gate electrode 108 and a source / drain region 109 of the switching transistor are formed, a contact hole 110 is opened in the source region, and an electrode 111 of the capacitor is formed.

Finally, as shown in FIG. 2D, an interlayer insulating film 112 is deposited, a contact hole 113 is opened in the insulating film 112, and an inter-element wiring 114 is formed.

FIG. 4 shows a configuration of a conventional semiconductor memory using the above-mentioned stacked capacitor as a capacitor.

In the figure, 201 is a semiconductor substrate, 202 is a lower insulating film, 20
4 is an element isolation insulating film, 206 is a gate insulating film of a switching transistor, 207a and 207b are dielectric films of a capacitor, 2
08 is the gate electrode of the switching transistor, 209 is the drain region of the switching transistor, 210a and 210b are contact holes for establishing electrical conduction of the capacitor electrode, 211a is the source region of the switching transistor, and the first electrode of the capacitor is also used. is there. The 211a is electrically connected to the 211c via the contact hole 210a. 211
b and 211d are electrically connected via the contact hole 210b and serve as the second electrode of the capacitor. 212 is an interlayer insulating film, and 213a, 213b, and 213c are contact holes for establishing electrical continuity between the metal wirings 214a and 214b and the element.

[Problems to be solved by the invention]

The configuration of the capacitor of the conventional semiconductor memory device is as described above. In the case of a trench capacitor, as shown in FIGS.
Needed to dig 5 deep. Further, after the formation of the thin capacitor dielectric film 107, it is necessary to form an electrode inside and fill the hole. At this time, it is difficult to form an electrode film on the trench side wall, and the film tends to be thin. When filling the hole 105, there is a problem that a cavity is formed in the hole.

On the other hand, in the case of the stacked capacitor shown in FIG. 4, it is necessary to deposit several layers of films, which causes a problem that the process becomes complicated and a development period is required.
Furthermore, since a conductive film to be deposited is generally a polycrystalline or amorphous film, a thin dielectric film formed on the surface thereof, when formed, for example, by oxidation, becomes a non-uniform film. Destruction occurs, the breakdown voltage is deteriorated, and the reliability of the capacitor is deteriorated. Further, when a thin dielectric film is formed by deposition, there is a problem that the interface state between the electrode and the thin dielectric film of the capacitor is deteriorated and the interface state is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor memory device having good uniformity, high throughput, and a high-capacity capacitor, and a method of manufacturing the same. .

[Means for solving the problem]

In a semiconductor memory device according to the present invention, a part of a plurality of substrates each sandwiched between insulating films is separated into at least two regions by a thin dielectric film, and regions of each substrate where the dielectric films are separated from each other are separated. It is characterized by comprising capacitors wired so as to be electrically connected to each other via a dielectric region formed in at least a part of the insulating film.

Further, a method for manufacturing a semiconductor memory device according to the present invention includes:
A capacitor is formed on one principal surface of a first semiconductor substrate, and an insulating film is formed on at least a part of the surface of the capacitor in which a conductor reaching one electrode of the capacitor is exposed, and a second semiconductor substrate is formed on the surface. In which the active element or the passive element is formed on the thinned second semiconductor substrate.

Further, in the method of manufacturing a semiconductor memory device according to the present invention, the first capacitor is formed on one main surface of the first semiconductor substrate, and the first capacitor is formed on at least a part of the first capacitor surface. Forming an insulating film in which a conductor reaching one of the electrodes is exposed, joining a second semiconductor substrate to the surface of the insulating film, thinning the first semiconductor substrate to expose an electrode of the first capacitor, A second capacitor is formed on one principal surface of the semiconductor substrate of No. 3 and the first capacitor of the second capacitor is formed on at least a part of the surface of the second capacitor.
Forming an insulating film in which a conductor reaching the second electrode is exposed, aligning and joining the first semiconductor substrate and the third semiconductor substrate, and electrically connecting them; and reducing the thickness of the second semiconductor substrate. Forming an active element or a passive element on the thinned second semiconductor substrate.

[Action]

In the present invention, a capacitor having substantially the same size as the cell area is stacked under the active element such as the switching transistor or the passive element by a wafer bonding method, so that a high-capacitance capacitor can be provided without increasing the element area. Can be formed. In addition, when two or more layers are stacked, the capacitor formation process can be performed in parallel and a mask can be commonly used, so that the throughput can be increased and the manufacturing cost can be reduced.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

1 (a) to 1 (g) are cross-sectional views showing main steps of a method for manufacturing a semiconductor memory device according to a first embodiment of the present invention.

In FIG. 3A, reference numeral 301a denotes a first semiconductor substrate;
Is a concave portion formed by processing the surface of the first semiconductor substrate 301a and performing etching. In FIG. 3B, reference numeral 307a denotes a dielectric film of the first capacitor. Thus, the substrate
After a concave portion 305a is provided in 301a and a dielectric film 307a is formed, boron or the like is injected into the interface between the substrate 301a and the dielectric film 307a to form a high-concentration impurity implanted region. Thereafter, as shown in FIG. 3C, a conductor 311a serving as a second electrode of the capacitor is further embedded in the concave portion 305a. Here, the substrate 301a functions as a first electrode with respect to the capacitor 311a. Then, as shown in the left diagram of FIG. 4D, an insulating film 302a is deposited on the conductive film 311a, a hole is opened in a part of the insulating film 302a, and the conductive film 310a is embedded in the hole. The second of the capacitor
Electrode 311a.

During the above processing, as shown in the right side of FIG.
A high concentration impurity layer 315 of 1 × 10 ¹⁸ / cm ³ or more is formed on one main surface of the second semiconductor substrate 301b, and a low concentration epitaxial layer 316 is grown on the high concentration impurity layer forming region side of the semiconductor substrate.

Next, as shown in FIG. 3E, the first semiconductor substrate 301a and the second semiconductor substrate are joined, and annealed at a temperature of about 800 ° C. for 30 minutes or more in an inert gas to form a silicon layer 316 The silicon oxide film layer 302a is bonded.

Thereafter, the sample is impregnated in an aqueous solution of ethylenediamine and pyrocatechol as shown in FIG. 9F, whereby the second semiconductor substrate 301b is etched to a position short of the high-concentration impurity region 315, thereby making it thinner. Except further high concentration impurity regions 315 is etched in a gas such as SF ₆ and CCl _4,
The single crystal semiconductor layer 316 can be formed over the insulating film 302a. In addition, since a part of the single crystal semiconductor layer 316 and the contact hole portion 310a of the capacitor are in contact with each other, as shown in FIG.
If an SOI transistor is manufactured using a process, a dynamic RAM cell can be obtained. Referring to FIG.
Is an element isolation insulating film, 308 is a gate electrode, 309 is a drain electrode of a MOS transistor, 312 is an interlayer insulating film, 313 is a contact hole, and 314 is an aluminum electrode.

According to such a manufacturing method, since the capacitors are stacked by the wafer bonding method, the first semiconductor substrate 301a and the second semiconductor substrate 301a are bonded until the wafer bonding step (FIG. 1E). Since the processing of 301b can be performed in parallel, the throughput is improved, and the yield can be improved because the wafers to be bonded can be selected. In the semiconductor memory device manufactured by this method, not only the side surface of the dielectric film 307a but also the lower surface of the dielectric film 307a can function as a capacitor due to the effect of the capacitor shape, and a large capacitance can be obtained. . Further, since the capacitor dielectric film 307a is formed on the single crystal substrate 301a, a good and high withstand voltage dielectric film can be obtained, and there is no possibility that dielectric breakdown or the like occurs at this portion, and the reliability of the element is improved. . In addition, since a capacitor region can be provided below the switching transistor, the element area can be significantly reduced.

Although the above embodiment has been described with reference to the case where one capacitor is stacked immediately below the switch transistor via an insulating film, the present invention is not limited to this.
A plurality of capacitors may be stacked in the vertical direction as necessary.

Hereinafter, a case where two layers of capacitors are stacked will be described as an example. 2 (a) to 2 (i) show a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention. In the figure, the left diagram, the center diagram, and the right diagram process independently. It is assumed that it is done.

First, in the central part of FIG. 2A, a boron high concentration layer 41 of 1 × 10 ¹⁸ / cm ³ or more is formed on the surface of the first silicon substrate 401a.
After forming 5a, epitaxial growth is performed to about 2 μm
A single-crystal silicon layer 416a is formed. Further, a part of the epitaxial growth layer 416a is etched by about 1 μm by photolithography and etching to provide a concave portion. Further, a part of the concave portion is further engraved with high density by photolithography and etching to obtain a concave portion 405a having two steps. On the other hand, as shown on the left side of FIG. 7A, a high concentration impurity implantation layer 415b is formed on the surface of the second silicon substrate 401b, and then a low concentration epitaxial layer 416b is grown. A part of the third silicon substrate 401c is processed into a concave shape by photolithography and etching as shown on the right side of FIG. Step is 1 μm
It is.

Next, as shown in FIG. 1B, dielectric films 407a and 407c of the capacitors made of silicon dioxide are formed on the surfaces of the first and third silicon substrates 401a and 401c by oxidation. Here, in order to prevent a decrease in capacitance due to the depletion layer, the interface between the dielectric film 407a and the single-crystal silicon layer 416a and the interface between the dielectric film 407c and the substrate 401c are each doped with a high-concentration impurity by ion implantation. Is provided.

Next, as shown in FIG. 3C, the concave portions 415a and 415c are buried by depositing a dielectric film such as a high-concentration polycrystalline silicon layer or a high-melting-point metal layer or a high-melting-point metal silicide layer and flattening by etch-back or the like. Conductive layers 411a and 411c to be second electrodes of the capacitors 407a and 407c are formed.

Next, as shown in FIG. 3D, after interlayer insulating films 402a and 402c are deposited on the substrate surface, the interlayer insulating films 402a and 402c are formed.
The via holes 410a and 410c each having a conductive film embedded therein are formed and connected to the second electrode of each capacitor, and a via hole 413c is provided in the interlayer insulating film 402c. The conductive film is buried so as to reach the third silicon substrate 401c serving as the first electrode of the first embodiment.

Next, as shown in FIG.
Are bonded by performing annealing at a temperature of 80 ° C.

Next, a protective film (not shown) is formed on the back surface of the second silicon substrate 401b, and is etched in a mixed aqueous solution of ethylenediamine and pyrocatechol to perform concentration difference etching. In the above etching, the first silicon substrate 401a is etched, and the etching is completed before the high-concentration impurity layer 415a. Further, the second electrode 411a and the single-crystal silicon layer as the first electrode are exposed on the surface by removing the high-concentration impurity layer 415a by etching using ordinary CCl ₄ or the like, as shown in FIG. Get.

Next, as shown in FIG.
Is bonded to the single crystal silicon layer 416a side in the same manner as described above, and the second electrode 411a of the capacitor 407a and the capacitor 407c
Is connected via a via hole 410c, and the first electrode 416a of the capacitor 407a and the first electrode 401c of the capacitor 407c are connected via a via hole 413c. However, since alignment is required in this case, photolithography is performed with an exposure apparatus having an alignment mechanism using light having good transparency such as infrared rays.

Next, as shown in FIG. 2H, after the second silicon substrate 401b is thinned by the same method as described above, the high-concentration impurity regions 415b are removed.

Next, as shown in FIG. 2I, a switching transistor is formed on the single-crystal silicon layer 416b according to a normal MOSFET manufacturing process, thereby completing the manufacture of the semiconductor memory cell.

In this embodiment, in addition to the configuration of the first embodiment, the capacitor is stacked by a wafer bonding method, so that the DRAM having a larger capacity can be used without increasing the capacitor area. Can be configured. In this embodiment, the number of lamination processes is increased as compared with the above embodiment. However, since all such lamination processes can be performed in parallel in the same process and can be performed with the same mask, the number of masks is almost increased. This eliminates the need, and can reduce the cost.

〔The invention's effect〕

As described above, according to the present invention, a capacitor having substantially the same size as a cell area is sequentially stacked by a wafer bonding method under an active element or a passive element having a single crystal axis in a chip, such as a switching transistor. As a result, the respective manufacturing steps can be performed in parallel, and the throughput is improved. In addition, since the wafers to be bonded can be selected, the yield can be improved. In addition, since the capacitor region is provided below the switching transistor, a high capacitance can be easily obtained without increasing the element area even when miniaturizing the element.
Also, due to the effect of the capacitor shape, not only the side surface but also the bottom surface of the capacitor will work as a capacitor,
There is an effect that the capacity can be increased. In addition, since the dielectric film of the capacitor is formed on the single crystal substrate, it is possible to form a good dielectric film having a high withstand voltage and to obtain a highly reliable element. Further, in the step of performing the lamination, each step can be performed using the same process and the same mask, so that there is an effect that the process can be simplified and the cost can be reduced.

[Brief description of the drawings]

FIGS. 1A to 1G show a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention, and FIGS.
(I) is a diagram showing a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention, and FIGS. 3 (a) to (d) are diagrams showing a method for manufacturing a semiconductor memory device using a conventional trench capacitor. FIG. 4 is a diagram showing a configuration of a conventional semiconductor memory device using a stacked capacitor. In the figure, 301a and 401a are first semiconductor substrates, and 301b and 401b
Is the second semiconductor substrate, 401c is the third semiconductor substrate, 302a, 4
02a, 402c are insulating films 304, 404 are element isolation insulating films, 305a, 405
a, 405c is a concave portion, 307a, 407a, 407c is a capacitor dielectric film, 308, 408 is a gate electrode, 309, 409 is a drain or source region, 310a, 410a, 410c, 413c is a via hole, 311a, 411
a and 411c are conductor films, 312 and 412 are interlayer insulating films, 313 and 413 are contact holes, 314 and 414 are aluminum electrodes, 315, 415a and 415b are high-concentration impurity implantation layers, and 316, 416a and 416b are single-crystal silicon layers. In the drawings, the same reference numerals indicate the same or corresponding parts.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-98766 (JP, A) JP-A-62-293756 (JP, A) JP-A-64-25458 (JP, A) JP-A 61-98 4271 (JP, A) JP-A-62-193275 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/04 H01L 27/108 H01L 21/8242 H01L 21/822

Claims (3)

(57) [Claims] 1. A semiconductor substrate having a concave portion on one main surface, a dielectric film formed on the concave surface of the substrate, and formed on the dielectric film to fill the concave portion of the substrate. And a plurality of capacitors formed by vertically stacking a plurality of capacitors each including a conductor layer, with an insulating film interposed therebetween, and electrically connected to each other via via holes provided in the insulating film. A capacitor; an active element or a passive element formed on the uppermost capacitor of the plurality of capacitors with an insulating film interposed therebetween, and electrically connected to the uppermost capacitor via via holes provided in the insulating film; A semiconductor memory device comprising: 2. A concave portion is formed on one principal surface of a first semiconductor substrate, a dielectric film is formed on a surface of the concave portion, and a conductive film is formed on the dielectric film so as to fill the concave portion. Forming a capacitor by forming the capacitor; forming an insulating film on a surface of the capacitor; and forming a via hole reaching a conductor film of the capacitor on at least a part of the insulating film; A second side is formed on the side of the substrate on which the insulating film is formed.
Bonding a semiconductor substrate of the present invention to thin the second semiconductor substrate, and forming an active element or a passive element on the thinned second semiconductor substrate. Device manufacturing method. 3. A concave portion is formed on one main surface of a first semiconductor substrate, a dielectric film is formed on a surface of the concave portion, and a conductive film is formed on the dielectric film so as to fill the concave portion. Forming a first capacitor, forming an insulating film on a surface of the first capacitor, and forming a via hole reaching a conductor film of the first capacitor in at least a part of the insulating film. Step 1, a second semiconductor substrate is bonded to the side of the first semiconductor substrate on which the insulating film is formed, the first semiconductor substrate is thinned, and a conductor film of the first capacitor is formed. Processing, and at least the first capacitor manufactured in the first step is bonded to the capacitor surface side of the substrate formed by the first processing, and the bonded first capacitor The thickness of the first semiconductor substrate of the capacitor is reduced, and A second process of performing at least the first process of the second process of performing the process of exposing the conductor film of the capacitor one or more times;
Forming a recess on one main surface of the third semiconductor substrate, forming a dielectric film on the surface of the recess, and forming a conductor film on the dielectric film so as to fill the recess. Forming a second capacitor, forming an insulating film on the surface of the second capacitor, and forming the third semiconductor substrate and the conductor film of the second capacitor on at least a part of the insulating film. A third step of forming via holes reaching each other, a fourth step of aligning and joining the surface of the third semiconductor substrate and the first semiconductor substrate and electrically connecting them, and Forming a thin semiconductor substrate and forming an active element or a passive element on the thinned second semiconductor substrate.