JP2795270B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JP2795270B2 JP2795270B2 JP8257989A JP25798996A JP2795270B2 JP 2795270 B2 JP2795270 B2 JP 2795270B2 JP 8257989 A JP8257989 A JP 8257989A JP 25798996 A JP25798996 A JP 25798996A JP 2795270 B2 JP2795270 B2 JP 2795270B2
- Authority
- JP
- Japan
- Prior art keywords
- bump
- solder member
- diameter
- conductor layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 229910000679 solder Inorganic materials 0.000 claims description 50
- 239000004020 conductor Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 19
- 230000002093 peripheral effect Effects 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】この発明は、例えばフリップ
チップＩＣに係るものであり、特に接続電極部の構造を
改良した半導体集積回路装置に関する。
【０００２】
【従来の技術】従来において、フリップチップＩＣの接
続電極部分は、例えば図７に示すように構成されてい
る。すなわち、半導体素子等の回路要素を組み込み形成
したシリコンチップ１１とアルミナによる基板１２とが
対面設定されるようになっているもので、シリコンチッ
プ１１の基板１２との対向面には、端子電極とされる銅
（Cu) によるバンプ１３が突出形成されている。また基
板１２上には、このバンプ１３と対向設定される位置
に、接続電極とされる導体１４の層が形成されているも
ので、この導体１４とバンプ１３との間を、半田部材１
５によって接続するようにしているものである。
【０００３】ここで、Ｃｕバンプ１３はメッキ手段によ
って形成されるようになるものであり、等法的に成長す
るものであるため、その断面形状が基端部分で細く傘の
ような先頭形状を有する構造となる。そして、このバン
プ１３の傘状形状の先頭部分と導体１４との間が半田部
材１５によって結合されるようになっている。
【０００４】
【発明が解決しようとする課題】このような電極接合構
造で、冷熱の温度サイクルが繰り返し供給されるような
状態となると、半田部材１５とバンプ１３との接合界面
部分に亀裂が進展し、破壊が生ずるようになる。この破
壊は、半田部材１５のバンプ１３側の歪みが、導体１４
側の歪みよりかなり高いことに起因するものである。
【０００５】それに対して、従来より、例えば、「PHIL
IPS TECHNICAL REVIEW VOLUME34,1974,NO.4,P.85〜95」
には、図８のような構造のフリップチップＩＣの接続電
極構造が示されている。このように、半田部材１５がバ
ンプ１３を包み込むような構成であるとともに、半田部
材１５は、径方向に凹部１５ａが形成されている接続電
極部の構造が知られている。
【０００６】しかしながら、このような構造においても
いまだ冷熱の温度サイクルが繰り返し供給されるような
状態となると、半田部材１５とバンプ１３との接合界面
部分に亀裂が進展し、破壊が生じてしまう。本願発明は
上記のような点に鑑みられたもので、電極接続部分にお
いて冷熱が繰り返し作用したような場合でも、その接合
部に歪みによる亀裂が発生しないようにして、信頼性が
確実に向上されさるようにするフリップチップＩＣのよ
うな半導体集積回路装置を提供しようとするものであ
る。
【０００７】
【課題を解決するための手段】そこで我々は、はじめ
に、図８のような構造のフリップチップＩＣ接続電極構
造である場合、なぜ、半田部材１５とバンプ１３との接
合界面部分に亀裂が進展してしまうのかの原因を鋭意研
究した。図９は、基板１２とシリコンチップ１１との接
続構造において、バンプ１３が形成されていない場合の
接続電極部の半田形状と冷熱繰り返し試験（−４０℃と
１００℃各３０分間の２００サイクル）を行った場合の
良品率の推移を示す。
【０００８】図９に示されるように、バンプ１３が形成
されない状態における接続電極部の構造においては、半
田部材１５の形状は、径方向に凹部が形成された状態の
ものほど、基板１２とシリコンチップ１１との接続強度
が高くなることがわかる。これは、基板１２とシリコン
チップ１１との間の接合強度は、半田部材１５のもっと
も細い箇所の強度にもっとも影響される。そして、バン
プが形成されない接続電極部の構造の場合には、基板１
２と半田部材１５との接合部またはシリコンチップ１１
と半田部材１５との接合部が最も細い箇所である時（図
９の（ａ）に相当）よりも、半田部材１５自体に最も細
い箇所が存在した時（図９の（ｃ）に相当）の方がよ
り、接合強度が高く、図９のような結果になったものと
判断される。
【０００９】しかしながら、我々発明者らは、図８のよ
うに、バンプ１３を有する接続電極部の構造の場合に
は、バンプが形成されていない接続電極部の構造とは全
く逆の結果になってしまうことを見いだしたのである。
即ち、図８のようにバンプ１３が形成された接続電極部
の構造の場合には、基板１２と半田部材１５との接合部
またはバンプ１３と半田部材１５との接合部の方が半田
部材１５自体の強度よりも強度が大となるために、バン
プ１３が存在する接続電極部の構造では、バンプ１５の
存在しない接続電極部の構造とは逆に、バンプ１５の径
方向に凸部を有する樽形状をなすバンプ形状が最も好ま
しいことを見いだしたのである。
【００１０】そこで、本願発明においては、回路要素が
形成された半導体チップと、この半導体チップの導出端
子部に対して形成された突出電極とされるバンプと、上
記半導体チップに対面設定され、上記バンプに対応する
位置に形成された導体層が形成された基板と、この基板
と上記半導体チップとが対面設定された状態で、上記バ
ンプと導体層との間を接続設定する半導体部材とを具備
し、上記バンプは上記対面される基板の方向に向けて立
ち上がる円筒状の周面部と、上記導体層に平行に対面す
る端面を形成する平面部と、かつ上記円筒状の周面部と
上記平面部とを結ぶ角部が曲面である曲面部とから構成
され、上記半田部材が上記バンプにおける周面部の上記
半導体チップ表面との境界部が起点となって覆い始め、
かつ上記曲面部分を含み上記周面部および平面部を包み
込むようにして設定され、さらに上記半田部材は前記曲
面部の上記周面部側から上記導体に向かう方向において
徐々に径が大きくなるようにして径方向に凸部を有する
樽形状とするとともに、上記対面設定されるバンプの径
と、導体層の径との比が、「１±０．３」以内の状態に
設定されるようにしたことを特徴とする半導体集積回路
装置を提供するものである。
【００１１】
【作用】このような半導体集積回路装置にあって、バン
プが形成される接続電極部の構造において、半田部材の
径方向にて凸部が形成される樽形状をなすとともに、バ
ンプの径と導体層の径とをほぼ等しく設定することによ
って、強度を向上させるとともに、半導体チップと基板
との相互間を結合する半田部材の中の最大歪みを小さく
することができ、これにより、冷熱が繰り返されたよう
な場合でも、半田に亀裂を発生させることが効果的に抑
制できる。
【００１２】さらに、半田部材をバンプの外周部分まで
含む状態で接合設定しているので、その接合面積を充分
大きく設定することができるので、熱応力が加わって
も、発生する歪みを少なくすることができ、さらにこの
半導体集積回路装置の信頼性を向上させることができ
る。
【００１３】
【発明の実施の形態】以下、図面を参照してこの発明の
一実施例を説明する。図１はこの半導体集積回路装置の
電極接続部分の構成を示しているもので、シリコンチッ
プ１１をアルミナ基板１２に接合設定する場合を示して
いるもので、この基板１２上に形成された導体層１４に
対向する位置に、シリコンチップ１１に形成された回路
要素の端子電極となる円柱状の銅(Cu)バンプ２１が突設
形成されている。そして、導体層１４とバンプ１２との
間を半田部材２２で結合するようにしているものであ
り、この場合この半田部材２２はバンプ２１の外周部を
含む状態で、バンプ２１が半田部材２２内に包含される
状態とされている。また、この半田部材２２は、径方向
に凸部２２ａを有する樽形状をなしている。
【００１４】ここで、バンプ２１は対面される基板１２
の方向に向けて立ち上がる円筒状の周面部２１ａと、導
体層１４に平行に対面する端面を形成する平面部２１ｂ
と、この平面部の周囲と円筒状周面との角を曲面とする
曲面部２１ｃとを有するように構成され、上記半田部材
２２は上記バンプの上記円筒状周面部２１ａを包み込む
ように設定される。
【００１５】したがって、バンプ２１と半田部材２２と
の接合面積は、バンプ２１の先頭頂部のみ半田部材と接
合するように従来例と比較して、次の式で表現されるよ
うに大きくなる。
２πｒＤ／πｒ2 ＝（１＋２Ｄ／ｒ）倍
ここでｒはバンプ２１の半径、Ｄはバンプ２１の高さで
ある。
【００１６】具体的には、”ｒ＝２２０μｍ”で”Ｄ＝
４０μｍ”の場合、半田部材２２とバンプ２１との接合
面積は、１．５倍となる。このように半田部材２２がバ
ンプ２１の全体を包含するように接合されさることによ
って、図７で示されたようにバンプの先頭頂部分だけで
半田部材と接合された場合に比較して、接着面積が大き
くなるため初期強度が高くなり、また熱応力が作用した
場合でも歪みが少なくなる傾向にある。
【００１７】さらにまた、上記バンプ２１を形成した接
続電極部の構造として、半田部材の形状を樽形状とする
ことによって、接合強度をさらに向上させることがで
き、熱応力が作用した場合でも亀裂等の発生を抑制させ
ることができる。図２は半田部材２２の内部の歪み（ミ
ーゼス歪）の等高線図を示しているもので、この等高線
図から半田の寿命に寄与する最大歪みが１．８％で、か
なり均等化されていることがわかる。この等高線図にお
いては、線が折り重なっていればいる程、その部分に歪
みが集中している。
【００１８】この歪みの状態を横軸に「バンプ径／導体
層径」の比をとり、縦軸に歪み量をとって示せば図３に
示すようになる。この図で実線は半田部材２２のバンプ
側の歪みの状態をまた鎖線は導体層１４側の歪みの状態
をそれぞれ示している。この図から判断して、回路構成
を微細化して（すなわち現状２２０μｍから１５０μｍ
にして）現状より長寿命化させるには、バンプ径と導体
層径の比を１±０．３に制限する必要がなることが判明
する。尚、この図で示されたレベルＡとは現状品の最大
歪（２．４％）である。
【００１９】図４（Ａ）〜（Ｃ）はそれぞれバンプ２１
の径と、導体層２２の径との比を変えた例を示している
ものであり、図５の（Ａ）〜（Ｃ）それぞれの実線は上
記図４の（Ａ）〜（Ｃ）それぞれの場合のバンプ２１と
半田部材２２との接触界面の歪みを示し、また破線は導
体層１４と半田部材２２の接触界面の歪みの状態を示し
ている。そして、この図５に示される歪みの状態から判
断して、バンプ２１の径と導体層１４の径との比が
「１」の状態とされることによって、半田部材２２の内
部の歪みが均等化されることが理解される。
【００２０】尚、図４（Ａ）は検討前の状態の例で、バ
ンプが円柱状に形成され、特に角部分が成形されていな
い場合を示している。また（Ｂ）はこのバンプの形状を
適正化しているもので、円柱状のバンプの角部分に曲面
部をつけるようにしているもので、この（Ａ）および
（Ｂ）の例ではバンプ径より導体層径が充分に大きく設
定された場合を示している。この場合、（Ａ）のように
バンプに角部が残っていると、（Ｂ）のように丸みを付
けた場合に比較して歪みが大きく立ち上がる。また、
（Ｃ）はバンプ性と導体層径とを等しく設定した例を示
しているもので、バンプと半田部材との接触界面の歪み
が大きく軽減される。
【００２１】この（Ｃ）の例では、実施例と同様にバン
プの角部に曲面部を付けるようにしているが、この角部
を（Ａ）のように丸みのない状態とすると、（Ａ）と
（Ｂ）との比較で理解できるように半田部材における歪
みが増大し、したがって実施例においてはバンプの角部
に曲面部を付けるようにすることが望ましいことが理解
できる。
【００２２】これまでの実施例の説明では、バンプの形
状を円柱状にし、半田部材の形状を径方向に凸部を有す
る樽形状となした場合のみを示しているものであるが、
例えば図６に示すようにバンプ３１の形状を従来例で示
したような基端部が細くなるような形状の場合でも、こ
のバンプ３１の径が導体層１４の径と等しく設定され、
且つバンプ３１が半田部材２２によって包含され、さら
には、半田部材２２の形状が樽形状をなすような構造と
することによっても本件発明の目的は同様に達成するも
のである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a flip-chip IC, and more particularly to a semiconductor integrated circuit device having an improved connection electrode structure. 2. Description of the Related Art Conventionally, a connection electrode portion of a flip chip IC is configured as shown in FIG. 7, for example. That is, a silicon chip 11 in which a circuit element such as a semiconductor element is incorporated and a substrate 12 made of alumina are set to face each other, and a terminal electrode and a terminal electrode are provided on the surface of the silicon chip 11 facing the substrate 12. A bump 13 made of copper (Cu) is formed so as to protrude. A layer of a conductor 14 serving as a connection electrode is formed on the substrate 12 at a position opposed to the bump 13. A solder member 1 is provided between the conductor 14 and the bump 13.
5 are used for connection. Here, since the Cu bumps 13 are formed by plating means and are grown in an equal manner, the cross-sectional shape of the Cu bumps 13 is thin at the base end and has a head-like shape like an umbrella. Structure. The umbrella-shaped head portion of the bump 13 and the conductor 14 are connected by a solder member 15. In such an electrode bonding structure, when a temperature cycle of cold and heat is repeatedly supplied, a crack develops at a bonding interface between the solder member 15 and the bump 13. And destruction occurs. This destruction is caused by distortion of the solder member 15 on the bump 13 side due to the conductor 14
This is due to being much higher than the side distortion. On the other hand, conventionally, for example, "PHIL
IPS TECHNICAL REVIEW VOLUME34, 1974, NO.4, pp. 85-95 ''
FIG. 1 shows a connection electrode structure of a flip chip IC having a structure as shown in FIG. As described above, the solder member 15 has a configuration in which the bump 13 is wrapped, and the solder member 15 is known to have a structure of a connection electrode portion in which a concave portion 15a is formed in a radial direction. However, even in such a structure, when a temperature cycle of cold and heat is still supplied repeatedly, a crack develops at a joint interface between the solder member 15 and the bump 13 and breakage occurs. The present invention has been made in view of the above points, and even in a case where cold heat is repeatedly applied to an electrode connection portion, a crack due to distortion is not generated at the joint portion, and reliability is reliably improved. It is an object of the present invention to provide a semiconductor integrated circuit device such as a flip-chip IC. [0007] Therefore, first, in the case of a flip-chip IC connection electrode structure having a structure as shown in FIG. 8, the reason why a crack is formed at the joint interface between the solder member 15 and the bump 13 is as follows. I have studied the cause of the progress of the research. FIG. 9 shows the solder shape of the connection electrode portion and the cooling / heating repetition test (200 cycles of -40 ° C. and 100 ° C. for 30 minutes each) when the bump 13 is not formed in the connection structure between the substrate 12 and the silicon chip 11. This shows the transition of the non-defective rate when the test is performed. As shown in FIG. 9, in the structure of the connection electrode portion in a state in which the bump 13 is not formed, the shape of the solder member 15 is such that the more the concave portion is formed in the radial direction, the more the substrate 12 and the silicon It can be seen that the connection strength with the chip 11 increases. This is because the bonding strength between the substrate 12 and the silicon chip 11 is most affected by the strength of the thinnest portion of the solder member 15. In the case of the structure of the connection electrode portion where no bump is formed, the substrate 1
2 or solder member 15 or silicon chip 11
When the thinnest portion exists in the solder member 15 itself (corresponding to (c) in FIG. 9), compared to when the joint between the solder member 15 and the solder member 15 is the narrowest portion (corresponding to (a) in FIG. 9). It is determined that the bonding strength is higher and the result shown in FIG. 9 is obtained. However, as shown in FIG. 8, the present inventors have found that the structure of the connection electrode portion having the bumps 13 has a completely opposite result to the structure of the connection electrode portion where no bump is formed. It was found that
That is, in the case of the structure of the connection electrode portion on which the bumps 13 are formed as shown in FIG. 8, the bonding portion between the substrate 12 and the solder member 15 or the bonding portion between the bump 13 and the solder member 15 is more suitable for the solder member 15. Since the strength is higher than the strength of the bump itself, the structure of the connection electrode portion having the bump 13 has a convex portion in the radial direction of the bump 15, contrary to the structure of the connection electrode portion having no bump 15. It has been found that the barrel-shaped bump shape is the most preferable. Therefore, in the present invention, a semiconductor chip on which a circuit element is formed, a bump serving as a protruding electrode formed with respect to a lead terminal portion of the semiconductor chip, A substrate on which a conductor layer formed at a position corresponding to the bump is formed, and a semiconductor member for setting connection between the bump and the conductor layer in a state where the substrate and the semiconductor chip are set to face each other. The bump has a cylindrical peripheral surface rising in the direction of the facing substrate, a flat surface forming an end surface facing in parallel with the conductor layer, and the cylindrical peripheral surface and the flat surface. is composed of a curved part corner is a curved surface connecting the bets, the above solder member is peripheral surface portion of the bump
Starting from the boundary with the semiconductor chip surface as the starting point,
And wraps the peripheral surface and the flat surface including the curved surface.
And the solder member is bent so that
In the direction from the peripheral surface side of the surface to the conductor
The diameter is gradually increased and the barrel shape is formed with a convex portion in the radial direction, and the ratio of the diameter of the bump set to the facing surface to the diameter of the conductor layer is within “1 ± 0.3”. A semiconductor integrated circuit device characterized by being set to a state. In such a semiconductor integrated circuit device, the structure of the connection electrode portion on which the bump is formed has a barrel shape in which a convex portion is formed in the radial direction of the solder member, and has a bump-like shape. By setting the diameter and the diameter of the conductor layer to be substantially equal, the strength can be improved, and the maximum distortion in the solder member that couples the semiconductor chip and the substrate can be reduced. Is repeated, it is possible to effectively suppress the occurrence of cracks in the solder. Further, since the bonding is set so as to include the solder member up to the outer peripheral portion of the bump, the bonding area can be set sufficiently large, so that even if a thermal stress is applied, the generated distortion is reduced. And the reliability of the semiconductor integrated circuit device can be improved. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of an electrode connecting portion of the semiconductor integrated circuit device, in which a silicon chip 11 is set to be bonded to an alumina substrate 12, and a conductive layer formed on the substrate 12 is formed. At a position facing 14, a columnar copper (Cu) bump 21 serving as a terminal electrode of a circuit element formed on the silicon chip 11 is formed in a projecting manner. The conductive layer 14 and the bumps 12 are joined by a solder member 22. In this case, the solder member 22 includes the outer peripheral portion of the bump 21 and the bump 21 Is included in the state. The solder member 22 has a barrel shape having a convex portion 22a in the radial direction. Here, the bumps 21 are formed on the facing substrate 12.
And a flat surface portion 21b forming an end face facing in parallel with the conductor layer 14
And a curved surface portion 21c having a curved surface at an angle between the periphery of the flat surface portion and the cylindrical peripheral surface. The solder member 22 is set so as to surround the cylindrical peripheral surface portion 21a of the bump. You. Therefore, the bonding area between the bump 21 and the solder member 22 becomes larger as expressed by the following equation, as compared with the conventional example in which only the top of the bump 21 is bonded to the solder member. 2πrD / πr 2 = (1 + 2D / r) times where r is the radius of the bump 21 and D is the height of the bump 21. Specifically, when “r = 220 μm” and “D =
In the case of “40 μm”, the bonding area between the solder member 22 and the bump 21 becomes 1.5 times. By bonding the solder member 22 so as to cover the entire bump 21 as shown in FIG. As compared with the case where only the top part of the bump is joined to the solder member as described above, the initial strength is increased because the bonding area is larger, and the distortion tends to be reduced even when thermal stress is applied. Furthermore, by making the shape of the solder member into a barrel shape as the structure of the connection electrode portion on which the bumps 21 are formed, the joining strength can be further improved, and even if thermal stress acts on the connection member, a crack is formed. 2 shows a contour diagram of the distortion (Mises distortion) inside the solder member 22. From the contour diagram, the maximum distortion contributing to the life of the solder is shown. In this contour map, the more the line is folded, the more the distortion is concentrated in that portion. FIG. 3 shows the ratio of “bump diameter / conductor layer diameter” on the horizontal axis and the amount of distortion on the vertical axis. In this figure, the solid line shows the state of distortion on the bump side of the solder member 22, and the chain line shows the state of distortion on the conductor layer 14 side. Judging from this figure, the circuit configuration was miniaturized (ie, the current 220 μm to 150 μm
It becomes clear that it is necessary to limit the ratio of the diameter of the bump to the diameter of the conductor layer to 1 ± 0.3 in order to extend the life from the current state. The level A shown in this figure is the maximum distortion (2.4%) of the current product. FIGS. 4A to 4C show bumps 21 respectively.
5 and the diameter of the conductor layer 22 are changed, and solid lines in FIG. 5A to FIG. 5C are respectively shown in FIG. 4A to FIG. In this case, the strain at the contact interface between the bump 21 and the solder member 22 is shown, and the broken line shows the state of the strain at the contact interface between the conductor layer 14 and the solder member 22. Judging from the state of the distortion shown in FIG. 5, the ratio of the diameter of the bump 21 to the diameter of the conductor layer 14 is set to “1”, so that the internal distortion of the solder member 22 is uniform. It is understood that FIG. 4A shows an example of a state before the examination, in which the bumps are formed in a columnar shape, and in particular, the corner portions are not formed. (B) optimizes the shape of the bump, and forms a curved surface at the corner of the columnar bump. In the examples of (A) and (B), the bump diameter is smaller than the bump diameter. This shows a case where the conductor layer diameter is set to be sufficiently large. In this case, when the corners remain on the bumps as shown in (A), the distortion rises significantly as compared with the case where the bumps are rounded as shown in (B). Also,
(C) shows an example in which the bump property and the conductor layer diameter are set to be equal, and distortion at the contact interface between the bump and the solder member is greatly reduced. In the example of (C), a curved surface is formed at the corner of the bump as in the embodiment. However, if the corner is not rounded as shown in FIG. As can be understood from the comparison between (b) and (B), it is understood that the distortion in the solder member increases, and therefore, it is desirable to form a curved portion at the corner of the bump in the embodiment. In the description of the embodiments described above, only the case where the shape of the bump is cylindrical and the shape of the solder member is a barrel having a convex portion in the radial direction is shown.
For example, as shown in FIG. 6, even in the case where the shape of the bump 31 is such that the base end portion becomes narrow as shown in the conventional example, the diameter of the bump 31 is set to be equal to the diameter of the conductor layer 14, and
Further, the object of the present invention can be similarly achieved by adopting a structure in which the bump 31 is included by the solder member 22 and the shape of the solder member 22 is formed in a barrel shape.
【図面の簡単な説明】
【図１】本発明の一実施例に係る半導体集積回路装置を
構成するバンプによる接合部分を説明する断面構成図で
ある。
【図２】上記結合部分の半田部材内部の歪みの発生状態
を示す図である。
【図３】バンプ径／導体層径の比を変えた場合の歪みの
発生状態を示す図
【図４】（Ａ）〜（Ｃ）はそれぞれバンプ径と導体層径
との比を変えた例を示す図である。
【図５】（Ａ）〜（Ｃ）はそれぞれ図６の（Ａ）〜
（Ｃ）の例に対応する歪みの発生状態を示す図である。
【図６】本発明の他の実施例を説明する図である。
【図７】従来の例を説明する部である。
【図８】従来の例を説明する部である。
【図９】従来の半田部材の形状を変化させた場合の良品
率の変化を示す関係図である。
【符号の説明】
１１ シリコンチップ
１２ アルミナ基板
１３，２１，３１ バンプ
１４ 導体層
１５，２２ 半田部材BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional configuration diagram illustrating a bonding portion by a bump constituting a semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 2 is a view showing a state in which distortion occurs inside a solder member at the connection portion. FIG. 3 is a view showing a state of occurrence of distortion when the ratio of bump diameter / conductor layer diameter is changed. FIGS. 4A to 4C are examples in which the ratio of bump diameter to conductor layer diameter is changed, respectively. FIG. FIGS. 5A to 5C are FIGS. 6A to 6C, respectively.
It is a figure which shows the generation | occurrence | production state of the distortion corresponding to the example of (C). FIG. 6 is a diagram illustrating another embodiment of the present invention. FIG. 7 is a diagram illustrating a conventional example. FIG. 8 is a diagram illustrating a conventional example. FIG. 9 is a relationship diagram showing a change in a non-defective rate when the shape of a conventional solder member is changed. [Description of Signs] 11 Silicon chip 12 Alumina substrate 13, 21, 31 Bump 14 Conductive layer 15, 22 Solder member
───────────────────────────────────────────────────── フロントページの続き (72)発明者 陸井 智 愛知県刈谷市昭和町１丁目１番地 日本 電装株式会社内 (72)発明者 阿部 吉次 愛知県刈谷市昭和町１丁目１番地 日本 電装株式会社内 (72)発明者 真山 恵次 愛知県刈谷市昭和町１丁目１番地 日本 電装株式会社内 (56)参考文献 特開 昭62−293729（ＪＰ，Ａ) 特開 昭64−28931（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 311 H01L 21/92──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoshi Rikui 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Japan Denso Co., Ltd. (72) Inventor Yoshiji Abe 1-1-1, Showa-cho, Kariya-shi, Aichi Japan Japan Denso Stock In-company (72) Inventor Keiji Mayama 1-1-1 Showa-cho, Kariya-shi, Aichi Japan Inside Denso Co., Ltd. (56) References JP-A-62-293729 (JP, A) JP-A-64-28931 (JP, A) (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 311 H01L 21/92
Claims (1)
電極とされるバンプと、 上記半導体チップに対面設定され、上記バンプに対応す
る位置に形成された導体層が形成された基板と、 この基板と上記半導体チップとが対面設定された状態
で、上記バンプと導体層との間を接続設定する半導体部
材とを具備し、 上記バンプは上記対面される基板の方向に向けて立ち上
がる円筒状の周面部と、上記導体層に平行に対面する端
面を形成する平面部と、かつ上記円筒状の周面部と上記
平面部とを結ぶ角部が曲面である曲面部とから構成さ
れ、 上記半田部材が上記バンプにおける周面部の上記半導体
チップ表面との境界部が起点となって覆い始め、かつ上
記曲面部分を含み上記周面部および平面部を包み込むよ
うにして設定され、さらに上記半田部材は前記曲面部の
上記周面部側から上記導体に向かう方向において徐々に
径が大きくなるようにして径方向に凸部を有する樽形状
とするとともに、 上記対面設定されるバンプの径と、導体層の径との比が
「１±０．３」以内の状態に設定されるようにしたこと
を特徴とする半導体集積回路装置。(57) [Claims] A semiconductor chip on which a circuit element is formed; a bump serving as a protruding electrode formed on a lead terminal portion of the semiconductor chip; and a conductor formed facing the semiconductor chip and formed at a position corresponding to the bump. A substrate on which a layer is formed, and a semiconductor member for setting connection between the bump and the conductor layer in a state where the substrate and the semiconductor chip are face-to-face set, wherein the bump is the face-to-face substrate A cylindrical surface that rises in the direction of the above, a flat surface that forms an end face that faces parallel to the conductor layer, and a curved surface that has a curved surface connecting the cylindrical peripheral surface and the flat surface. Wherein the solder member is a semiconductor on a peripheral surface portion of the bump.
Start to cover from the boundary with the chip surface
Encloses the above-mentioned peripheral surface and flat surface, including the curved surface
And the solder member is formed on the curved surface portion.
Gradually in the direction from the peripheral surface to the conductor
The diameter of the bump is set to be larger than the diameter of the conductor layer, and the ratio of the diameter of the bump set to the facing surface to the diameter of the conductor layer is set to be within “1 ± 0.3”. And a semiconductor integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8257989A JP2795270B2 (en) | 1996-09-30 | 1996-09-30 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8257989A JP2795270B2 (en) | 1996-09-30 | 1996-09-30 | Semiconductor integrated circuit device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62195856A Division JPH0793306B2 (en) | 1987-08-05 | 1987-08-05 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09107005A JPH09107005A (en) | 1997-04-22 |
| JP2795270B2 true JP2795270B2 (en) | 1998-09-10 |
Family
ID=17314006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8257989A Expired - Fee Related JP2795270B2 (en) | 1996-09-30 | 1996-09-30 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2795270B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62293729A (en) * | 1986-06-13 | 1987-12-21 | Oki Electric Ind Co Ltd | Connection structure of flip chop |
-
1996
- 1996-09-30 JP JP8257989A patent/JP2795270B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09107005A (en) | 1997-04-22 |
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