JP2789679B2 - Parity signal insertion circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a parity bit insertion circuit in a digital transmission device.

(Prior Art) A method of inserting a parity bit into a transmission signal at a constant period and monitoring the state of a transmission path on a receiving side is widely known. Referring to Fig. 6, AMI (Alternative Mark Inve)
A conventional example using a (rse) code will be described. The encoder comprises a precoder comprising an exclusive OR circuit 1, an 11-bit delay circuit 2, and a subtraction circuit 3. Transmission signal a _n , subtractor 3
The relationship between the positive input b _n and the output c _n of the delay circuit is shown in FIG. The exclusive OR circuit 6 and the delay circuit 7 generate a parity signal, and are supplied to the exclusive OR circuit 1 via the select 5 by the control signal 40 at the parity bit position. When this supply ends, the internal state of the delay circuit 7 is initialized by the control signal 40. The AMI-converted signal is supplied to the transmission line 8 as shown in FIG. On the receiving side, the transmission code 0 is converted to 0 and the transmission codes +1 and -1 are converted to 1 by the MOD2 circuit 9 that converts the signal into a modulo 2 signal, thereby restoring the original signal.

(Problems to be Solved by the Invention) In the configuration shown in FIG. 6, the exclusive OR circuits 2 and 7 are provided, but the processing function is to perform the exclusive OR of the transmission signal and the parity result before it. And they are the same. Processing the same function in different circuits causes circuit waste.

An object of the present invention is to eliminate such waste by realizing exclusive OR processing used in a precoder and exclusive OR processing for generating a parity sum using the same circuit.

If even parity as an example, FIG. 7 (a), the positive input b _n of the subtracter 3 in the insertion position P of the parity bit P, as shown in (b) always becomes 1 or 0. Therefore, even if a parity signal circuit is not provided, the same effect can be obtained by setting the signal b _n to 0 or 1 at the parity bit insertion position.

The parity signal insertion circuit according to the present invention uses
A bit-delay signal is input to the transmission-side precoder comprising an exclusive-OR circuit for generating an exclusive-OR signal. The transmission code is divided into N (N ≧ 1) phases at N-bit intervals.
A circuit for providing even-numbered parity bits to each of the N signal sequences, provided between an exclusive OR circuit and an N-bit delay circuit, and inserting parity bits of the N signal sequences. At the time position, a gate circuit supplies 0 (or 1) to the delay circuit, and at other time positions, supplies the signal of the exclusive OR circuit to the delay circuit as it is.

Also, the parity signal insertion circuit of the present invention is provided in a transmission side precoder comprising an exclusive OR circuit that inputs an input signal and a self N-bit delay signal and generates an exclusive OR signal, and transmits a transmission code at N bit intervals. A circuit for dividing into N (N ≧ 1) phases and giving an odd parity bit to each of the N signal sequences.
A bit is provided between the delay circuits of bits, and 0 and 1 are alternately supplied in the parity insertion cycle at the insertion time position of the parity bit of each of the N signal sequences and supplied to the delay circuit. At other time positions, The gate circuit is configured to directly supply the signal of the exclusive OR circuit to the delay circuit.

(Embodiment) FIG. 1 shows a first embodiment of the present invention. This is an example applied to a transmission device using an AMI code. The positive pulse control signal 40 supplied by the parity bit position output or the OR gate 41 sets the signal b _n to 1. It is also possible to use AND gates 42 shown in FIG. 2 in place of the OR gate 41, in this case, the signal b _n is by applying a control pulse to be 0 only at a parity bit position, it becomes zero.

FIG. 3 shows a second embodiment applied to a partial response class 4. This transmission code is known as AMI-encoded for each of two code sequences obtained by dividing the transmission code into even-numbered and odd-numbered, as shown by the logical expression in FIG. A 2-bit delay circuit 10 is provided. In this case, as shown in FIG. 4, the control signal 40 is applied at the parity bit insertion positions P1 and P2 determined in the two signal sequences {a _1i } and {a _2i } to generate parity bits. The transmission signal received via the transmission line 8 is
The original signal is restored by the MOD2 circuit 9. In the present invention, the positions of the parity bits P1 and P2 of the two signal sequences can be set arbitrarily and do not limit the mutual positional relationship.

FIG. 5 shows the configuration of another transmission device using the partial response class 4. One-bit delay circuits 11 and 12 and an adder circuit 13 are added to each of the transmission side and the reception side. It can be seen from the logical expression shown in FIG. 11 that d _n is the same as the signal c _{n in} FIG. The present invention is also applicable to a transmission device having this configuration.

The case where the even parity is added has been described above. Next, the assignment of the odd parity will be described. FIG. 8 shows a signal sequence in the conventional example of FIG. As shown in the figure, the signal b _n is alternately inverted for 1, 0 at each parity bit position P. FIG. 9 shows a fourth embodiment in which a gate group is provided instead of the OR gate 41 having the configuration of FIG. AN
One input of the gate 43 of the D logic and the gate 44 of the NAND logic is supplied with the same positive pulse as the control pulse 40 used in the embodiment of FIG. A counter signal that is alternately inverted to 0 and 1 in a repetition cycle is supplied. Therefore, the operation of FIG. 9 is different from the operation by the gate 41 shown in FIG. 1 and the gate 42 shown in FIG.
Are alternately performed in the above-described repetition cycle, and a desired operation can be obtained. Even if the gate group shown in FIG. 9 is provided in a precoder for implementing the partial response class 4, an operation of adding an odd parity to each of two signal sequences can be obtained in the same manner.

(Effect of the Invention) A parity bit insertion circuit can be realized without providing an exclusive OR circuit and a delay circuit redundantly, which can contribute to downsizing of the circuit.

[Brief description of the drawings]

FIGS. 1, 3, 5, and 9 show an embodiment of the present invention, and FIG. 2 shows another example of a gate circuit used in the present embodiment.
FIG. 4 shows a transmission frame of the second embodiment, FIG. 6 shows a conventional example, and FIGS. 7 and 8 show the operation of the conventional example. In the figure, 1, 6 is an exclusive OR circuit, 2, 7, 10, 11, 12 are delay circuits, 3 is a subtraction circuit, 41, 42, 43, 44 are gates, 5 is a selector, 8 is a transmission line, 9 Denotes a MOD2 circuit, and 13 denotes an addition circuit.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 13/00-13/22 H04L 25/00-25/66

Claims (2)

(57) [Claims] 1. A transmission side precoder comprising an exclusive OR circuit for receiving an input signal and its own N-bit delayed signal to generate an exclusive OR signal, wherein N transmission codes are provided at N bit intervals (N ≧ N). 1) a circuit for dividing each of the phases into 1) and giving an even parity bit to each of the N signal sequences. The circuit is provided between an exclusive-OR circuit and an N-bit delay circuit. 0 (or 1) is supplied to the delay circuit at the insertion time position of the parity bit of the signal sequence,
A parity signal insertion circuit comprising a gate circuit that supplies the signal of the exclusive OR circuit to the delay circuit as it is at other time positions. 2. A transmission-side precoder comprising an exclusive-OR circuit for receiving an input signal and its own N-bit delay signal to generate an exclusive-OR signal, and transmits N (N ≧ N) transmission codes at N-bit intervals. 1) a circuit for dividing each phase into N number of signal sequences and providing an odd parity bit to each of the N number of signal sequences. The circuit is provided between an exclusive OR circuit and an N-bit delay circuit. A gate for supplying 0 to the delay circuit alternately with 0 and 1 at a parity insertion cycle at a parity bit insertion time position of the signal sequence and supplying the exclusive OR circuit signal to the delay circuit as it is at other time positions. A parity signal insertion circuit comprising a circuit.