JP2786057B2 - Traffic distribution measurement circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a traffic distribution measuring circuit, and more particularly to an A-type circuit for performing asynchronous switching processing in units of cells.
TM (Asynchronous Transfer)
The present invention relates to a traffic distribution measurement circuit for measuring a traffic distribution of a cell on a data line using an exchange.

[0002]

2. Description of the Related Art Conventionally, in order to measure traffic distribution, the number of cells passing through a data line is counted by a counter circuit, and the counter value is stored in a memory as it is for each unit time notified by a timer. A control device provided with a processor writes and reads the value, and performs processing by software, thereby obtaining the distribution of the number of passed cells.

[0003]

A conventional traffic distribution measuring circuit counts the number of cells passing through a data line, and writes the count value as it is to a memory every time a unit time elapses. Therefore, the distribution of the number of cell passages cannot be obtained unless the software calculates based on the written data, and it takes time for software processing. Therefore, there is a problem that the processing cannot keep up with the high-speed line.

[0004] It is an object of the present invention to solve the above-mentioned problems,
An object of the present invention is to provide a traffic distribution measuring circuit capable of quickly obtaining a traffic distribution.

[0005]

A traffic distribution measuring circuit according to the present invention comprises a fixed-length communication information having a number of cells passing on a data line through which a cell in which information for identifying a destination is added at the beginning is transmitted. Circuit, a timer for notifying the counter of the elapse of the measurement unit time, a traffic distribution memory accessed using the number of passing cells counted by the counter circuit as an address, and an access to the traffic distribution memory. An arithmetic circuit for performing a predetermined operation for calculating the traffic distribution of the cell with respect to the contents of the address indicated by the counter value of the counter circuit every time, and a control circuit capable of reading the contents of the traffic distribution memory from outside. With this configuration, the distribution of the number of cells passing through the data line in the measurement unit time is obtained. .

[0006]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a traffic distribution measuring circuit according to one embodiment of the present invention. In FIG. 1, 1 is a data line to which a cell is transferred, 2 is a counter circuit which counts up by one each time a cell passes on the data line 1, and 3 is a unit time when measuring the number of passed cells. , A traffic distribution memory that accesses the number of passed cells per unit time as an address, a traffic distribution memory that accesses the number of passed cells per unit time as an address, and a traffic distribution memory 6 that is accessed. 7 is the number of times the address has been accessed, that is, an adder circuit as an arithmetic circuit for incrementing the stored data 6 of the address by 1, 8 is the output data of the adder circuit 7, and 9 is the traffic distribution memory. The input / output data 10 between the control unit 10 and the control unit 10 is controlled by the input / output data 9 to read and write the contents of the traffic distribution memory 5 from outside. It is the location.

FIG. 2 is an explanatory diagram of the operation of the traffic distribution memory 5 of FIG. The initial value of the data in the traffic distribution memory 5 is set to 0 by the control device 10 prior to the traffic measurement.

Next, the operation of the traffic distribution measuring circuit according to this embodiment will be described.

First, when a cell passes on the data line 1, the counter circuit 2 counts the number of passing cells.

When the elapse of the measurement unit time is notified by the timer circuit 3, the counter circuit 2 outputs the number of passing cells 4 and thereafter resets the counter value to 0, and counts the number of passing cells within the next measurement time. Start counting. The traffic distribution memory 5 is accessed using the number of cells 4 passing through the unit time as an address, and the data 6 at the corresponding address is output to the adding circuit 7.

The adder circuit 7 counts up the input memory data 6 by one and outputs it to the traffic distribution memory 5 as output data 8.

In the traffic distribution memory 5, the adder 7 writes the output data 8 to the corresponding address.

By repeating the above operation,
The stored data 51 in the traffic distribution memory 5 indicates the number of measurement unit times through which the number of cells equal to the address has passed. That is, data indicating the distribution of the number of cell passages within the measurement unit time is obtained. The obtained distribution data is
It is read from the control device 10.

In this embodiment, an adder circuit for performing +1 operation is used as an arithmetic circuit. However, it is obvious that the present invention can be implemented as a circuit for performing -1 operation and other operations.

[0016]

As described above, according to the present invention, a memory which counts the number of cells passing per unit time and measures the counter value as an address to measure the traffic distribution for the cells passing on the data line. By counting up the data of the cell, even if the line speed through which the cell passes becomes extremely high, the distribution of the number of cell passages within a certain time can be quickly stored in the traffic distribution memory. This has the effect that it can be secured.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is an explanatory diagram of an operation of the traffic distribution memory 5 of FIG.

[Explanation of symbols]

 Reference Signs List 1 data line 2 counter circuit 3 timer circuit 4 number of passing cells 5 traffic distribution memory 6 memory data 7 adder circuit 8 output data 9 input / output data 10 controller

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 12/28 H04L 12/56 H04L 13/00

Claims (1)

(57) [Claims] 1. A counter circuit for counting the number of cells on a data line through which a cell in which information for identifying a destination is added at the beginning of fixed-length communication information, A timer for notifying a counter, a traffic distribution memory accessed using the number of passing cells counted by the counter circuit as an address, and an address indicated by a counter value of the counter circuit each time the traffic distribution memory is accessed. And a control circuit capable of reading out the contents of the traffic distribution memory from the outside by providing an arithmetic circuit for performing a predetermined operation for obtaining the traffic distribution of the cells with respect to the contents of A traffic distribution measuring circuit for obtaining a distribution of the number of passages.