JP2785606B2 - Debugger for pipelined computer programs - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a symbolic step debugger, and more particularly to a debugger for debugging a source program for a computer employing a pipeline processing method in units of lines.

[0002]

2. Description of the Related Art An error in a program leads to an incorrect result or an irrecoverable state. For example, dividing the number by zero, referring to a non-existent memory address,
This is the case when trying to write there. The error in the program that causes this is called a bug, and the work to remove the bug is called debugging.

[0003] Complete debugging does not end without verifying that the program is created as intended by the program developer. However, writing a complete program is extremely difficult, and debugging on a desk takes a lot of work.

[0004] Therefore, it is customary to employ symptomatic debugging in which the program is executed to find the cause of the error, and the program is modified so that the program operates correctly within the range actually used. A system that enables such debugging to be performed efficiently is a debugger. In particular, a debugger that performs debugging at a symbolic source program level is called a symbolic debugger.

[0005] The debugger includes a tracer for recording the execution process of the program in a batch, and a stepper for checking the execution state of the program while executing the program one step at a time. The present invention relates to a stepper, a step debugger.

In a computer employing a pipeline control method, as is well known, each of a plurality of machine language instructions corresponding to a plurality of lines of a source program is continuously executed in a plurality of predetermined phases. However, depending on the arrangement of machine language instructions determined by the source program, a wait state for instruction execution may occur. In order to avoid this waiting state, a technique of changing the arrangement of machine instructions corresponding to different source lines in advance and shortening the program execution time is called object optimization.

Referring to FIG. 5, which shows a part of a program example before the object optimizing process, this program example adds a content of a memory address a and a content of a memory address b and stores the sum at a memory address c. Line number 5
Source line 52 in which 1 is “1” (hereinafter referred to as source line 1)
And a source row 52 (source row 2) having a source row number 51 of "2", which is to add an immediate value "1" to the contents of the memory address e and store the result at the memory address d.

The operation assignment statement c = a + b in the source line 1 is translated into three machine instructions as shown by numbers 1, 2 and 3 in the machine instruction number column 53 of FIG. A first machine language instruction having a machine language instruction number “1” (hereinafter referred to as machine language instruction 1; the same applies to “2” and “3”) reads out the contents of the memory address a and transfers it to the register 1. The machine instruction 2 adds the contents of the memory address b to the contents of the register 1 and holds the result in the register 1, and the machine instruction 3 transfers the contents of the register 1 to the memory address c.

Similarly, the operation assignment statement d = e +
1 is also translated into three machine language instructions. The machine language instruction 4 reads the contents of the memory address e and transfers them to the register 2. The machine language instruction 5 adds an immediate value “1” to the contents of the register 2 and holds the same in the register 2.
Is transferred to the memory address d.

Since the word length of the machine language instruction is selected to be equal to the number of bits of the two-memory address statement, the memory addresses of the machine language instructions 1, 2, 3,. .. And 10 respectively.

On the other hand, in a computer employing the pipeline processing method, machine language instructions 1, 2, 3,.
As shown in FIG. 6, the processing is executed continuously and in parallel at timings shifted from each other. FIG. 6 shows an example of the four-stage pipeline processing. For each of the machine language instructions 1, 2, 3,..., The machine language instruction word is read, the necessary memory contents are read, and the instruction execution is performed every clock cycle. The writing of the execution result is sequentially and continuously performed.

The program shown in FIG. 5 shows an example in which the execution of a machine language instruction falls into a wait state. Unless "write" to register 1 by machine language instruction 1 is completed, machine language instruction 2 is executed.
Cannot be executed in Therefore, in the example of the program shown in FIG. 5, machine language instructions 2 and below are delayed by one clock cycle.

This processing delay can be avoided by rearranging the machine language instructions. In the example of the program shown in FIG.
Since instructions 2 and 3 are irrelevant instructions, if the instruction is moved between machine instruction 1 and machine instruction 2, machine instruction 2 waits for “execution” of machine instruction 1 while machine instruction 4 The execution is performed, and the instruction execution performance can be improved. FIG. 7 shows a program after the object optimization processing with respect to the program example of FIG.

The conventional symbolic step debugger stores, for each source line of a source program, its line number and the head memory address of a machine language instruction string as a translation result of this source line, as debug information. Using the specified row number / address information table.

In FIG. 8, which shows such a line number / address information table 80 for the program example in FIG. 5, the symbolic step debugger operates as follows: source line number 1 (displayed as source line 1; When debugging the same, the line number “1” and the head memory address “0” of the source line 1 and the line number “2” and the head memory address “6” of the source line 2 are read. First, after executing the machine language instruction 1, the stop memory address becomes "2". Since this stop memory address is smaller than the head memory address "6" of the source row 2, the next machine address of the memory address "2" A word instruction is executed.

Thereafter, the machine language instruction is similarly executed until the stop memory address becomes "6". If the stop memory address is "6", it means that the source line 1 has been completely executed in the case of FIG. 5 where the object optimization has not been performed, whereas FIG. 7 where the object optimization has been performed
In the case of, execution of the machine language instruction 3 in the machine language instruction sequence of the source line 1 has not been reached. That is, the processing is delayed accordingly.

[0017]

In the above-mentioned conventional symbolic step debugger, since the debug information includes only the head memory address, the end memory address of the source line is the same as the head memory address of the next source line. The end of the step execution at the source line level is determined based on the premise that the memory address is the memory address. However, in an object-optimized program, the execution order of machine language instructions extends over two source lines, so this assumption is false, and it is not possible to correctly judge the end of step execution at the source line level. become. For this reason, conventionally, one or both of step debugging at the source level of a program program without object optimization and step debugging at the object level of a program with object optimization have been performed. . However, according to the former, there is a problem that a program different from that at the time of operation is debugged, and according to the latter, a large amount of time is required for the debugging work, so that efficient debugging cannot be performed.

It is an object of the present invention to provide a symbolic step debugger for a computer employing a pipeline control system, which can debug a program after optimization processing.

[0019]

According to the present invention, there is provided a symbolic communication system comprising:
The step debugger prepares, for each line of the source program, a table storing a source line number and a memory address range of a machine language instruction string which is a translation result of the source line, and uses this as debug information. The machine language instruction sequence may be a result of executing the object optimization according to the instruction. At the time of executing the step / debug, the debug information for the source line and the next source line are read, and each time one machine instruction is executed, it is determined whether or not the next machine instruction address is within the above-mentioned memory address range. The process proceeds while checking, and if not, debugging of the source line ends.

[0020]

FIG. 1 shows an embodiment of the present invention.
In the present embodiment, an analyzing unit 21 for analyzing a source program input from a source file 1, a translating unit 22 for converting the analysis result into machine language instruction sequence information, and an optimization for performing object optimization involving movement of a machine language instruction A language processing unit 2 including a unit 23 and a line number / address range information table output unit 24; and a machine language instruction sequence file input unit 4 for inputting a machine language instruction sequence file 31 output by the language processing unit 2.
1. Source level for the line number / address range information table input means 42 supplied with the line number / address range information table 32 from the line number / address range information table output means 24 and the optimized machine language instruction sequence And a debug processing unit 4 including a source level step executing means 43 for performing step execution.

FIG. 2 is an explanatory diagram showing an example of the row number / address range information table 32, where each entry is a column 32a.
., A starting address 0, 2, 12,... To the column 32b, and a ending address 7, 11, 14,. The contents of the start address and the end address in the figure correspond to the machine language instruction after the object optimization processing shown in FIG. 7, and when compared with the line number / address information table 80 shown in FIG. It can be seen that the value has been added and the value of the head address column 32b is also different.

Next, the operation of this embodiment is divided into language processing and debugging processing, and will be described with reference to the flowcharts of FIGS. 3 and 4, respectively.

First, the interpreter 21 of the language processor 2 reads the source program 1 and analyzes it (step S1). The translation means 22 translates the information of the source file 1 into a machine language instruction sequence (step S2). Optimizing means 23
Determines whether the user of the language processing program has designated the object optimization processing (step S3).
This specification can be made, for example, by inputting a job control language card.

If the result of determination in step S3 is that object optimization processing has been specified, the optimization means 23 performs optimization processing by moving the machine language instruction (step S4). In the example of the program shown in FIG. 5, the machine language instruction 2 has a machine language instruction execution waiting state as described above, so that the machine language instruction 4 is replaced with the machine language instruction 1 and the machine language instruction 2 as shown in FIG. Have moved between.

The row number / address range information table output means 24 outputs the row number / address range information table 32 shown in FIG. 2 irrespective of whether or not the optimization process is performed (step S5). If the optimization process has not been performed, the contents of the head address in the line number / address range information table 32 are set in the line number / address information table 80.
The contents of the end address are the same as the contents of the start address of the column 82 in FIG. 8, and the contents of the end address are one smaller than the contents of the start address of the column 82 with respect to the source line number described in the column 81.

On the other hand, when the optimization processing is performed, as shown in FIG. 2, the memory address ranges of the machine language instructions 1, 2, and 3 which are the translation results of the source line 1 are changed to the machine language instruction 1
From the start address 0 to the end address 7 of the machine language instruction 3. Further, the memory address range of the machine language instructions 4, 5 and 6 which are the translation result of the source line 2 is from address 2 which is the head address of the machine language instruction 4 to address 11 which is the end address of the machine language instruction 6. . Finally, the translation means 22 writes the machine language instruction sequence into the machine language instruction sequence file 3 (step S6). Next, the operation of the debug processing unit 4 will be described.

When the user of the debug processing program gives a source level step execution instruction, the machine language instruction sequence file input means 41 of the debug processing unit 4 inputs the machine language instruction sequence file 3, line number / address range information table input. The means 42 reads the row number / address range information table 32 into a memory (not shown). Thereafter, the source level step executing means 43 performs the following processing as shown in the flowchart of FIG. (1) If the current stop address of the machine language instruction string to be debugged is compared with the start address 32b in the line number / address range information table 32 and the same or less than the start address 32b of the next source line, The line number of the source line is obtained (step S11). If the current stop address is address 0, the source line number to be obtained is "1" because it is the same as the start address 0 of source line 1.

(2) The start address x and end address y of the obtained source line are obtained (step S12). For source row 1, x = 0 and y = 7.

(3) One machine language instruction is executed (step S13).

(4) The stop address of the program is (2)
If it stays between the start address x and the end address y obtained in step (3), the process returns to (3) and the step execution of the machine language instruction is repeated (steps S14 and S13). If the stop address is outside the range defined by the start address x and the end address y, the step execution at the source level has been completed.
The step execution of the machine language instruction for the source line ends (step S14). In the example of the program shown in FIG. 7, the end address of the source line 1 is 7, so that
When the stop address reaches address 8, the step execution of the source line 1 ends.

(5) When the step execution at the source level is completed, the stop address of the current program, the line number,
The head addresses of the column 32b of the address range information table 32 are compared, and the source line number of the column 32a is determined when they are the same or less than the head address of the next source line (S15). When the stop address is address 8, as is clear from FIG.
Since it is within address 2, the source line number to be obtained is the second line.

(6) The stopped source line number is displayed on a display device such as a console to notify the debugger of the source line number obtained in (5) (step S16).

In the present embodiment, the end address of the source line is represented by an absolute value as shown in FIG. 2, but an embodiment in which the end address is represented by a relative value to the start address can be easily realized.

As described above, according to the present invention, even when object optimization processing is performed in a computer of a pipeline control system, a line number and an address that accurately display a memory address range of a machine language instruction for a source line. Since the range information table is used, source-level debugging can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a line number / address range information table in a symbolic step debugger of the present invention.

FIG. 3 is a flowchart showing a processing procedure of a language processing unit in the symbolic step debugger of the present invention.

FIG. 4 is a flowchart showing a processing procedure of a debug processing unit in the symbolic step debugger of the present invention.

FIG. 5 is an explanatory diagram showing a part of a program example before an optimization process;

FIG. 6 is an explanatory diagram showing an example of pipeline processing of the program shown in FIG. 1;

FIG. 7 is an explanatory diagram showing a program after an optimization process is performed on the program example shown in FIG. 1;

FIG. 8 is an explanatory diagram showing an example of a line number / address information table in a conventional symbolic step debugger.

[Explanation of symbols]

 1 Source file 2 Language processing unit 21 Analysis unit 22 Translation unit 23 Optimization unit 24 Line number / address range information table output unit 31 Machine language instruction sequence file 32 Line number / address range information table 32a Source line number 32b Start address 32c End Address 4 Debug processing unit 41 Machine language instruction string file input unit 42 Line number / address range information table input unit 43 Source level step execution unit 51 Source line number 52 Source line 53 Machine language instruction number 54 Memory address 55 Machine language instruction 80 line Number / address information table 81 Source line number 82 Start address

Claims (3)

(57) [Claims] 1. A symbolic step debugger for debugging a source program for a computer adopting a pipeline control system in units of lines, wherein an execution order of machine language instructions constituting the source program is minimized. Number and address range displaying, for each source line of the source program, the line number and the memory address range after the machine language instruction for the source line, based on the result of the optimization. A line number / address range information table output means for creating an information table, and the machine language instruction is executed while checking whether or not a memory address for stopping execution of the machine language instruction is in the memory address range; Source level step execution means for determining that the debugging of the source line has been completed. A symbolic step debugger. 2. The symbolic step debugger according to claim 1, wherein the memory address range is represented by an absolute value of a head memory address and a tail memory address after a machine language instruction for the source line. 3. The symbolic according to claim 1, wherein the memory address range is represented by a head memory address after a machine language instruction for the source line and difference information from the head memory address to the end address.・
Step debugger.