JP2785338B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2785338B2 JP2785338B2 JP1157692A JP15769289A JP2785338B2 JP 2785338 B2 JP2785338 B2 JP 2785338B2 JP 1157692 A JP1157692 A JP 1157692A JP 15769289 A JP15769289 A JP 15769289A JP 2785338 B2 JP2785338 B2 JP 2785338B2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- solder
- forming
- electrode
- barrier metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H10W72/012—
-
- H10W72/01215—
-
- H10W72/01255—
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にはんだバ
ンプ電極を有する半導体装置の製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having solder bump electrodes.
従来、バンプ電極を有する半導体装置は、第２図に示
すように、シリコン基板１の上にAl電極３を設け、Al電
極３の上に単層あるいは多層からなる障壁金属層４を形
成し、しかる後半球状のはんだ電極８を形成する。はん
だ電極８のはんだ供給方法としては、めっき法、蒸着
法、はんだボール法、はんだディップ法が代表的な方法
として挙げられるが、所謂フリップチップにはめっき法
が多用されている。Conventionally, in a semiconductor device having a bump electrode, as shown in FIG. 2, an Al electrode 3 is provided on a silicon substrate 1, and a single-layer or multilayer barrier metal layer 4 is formed on the Al electrode 3. An appropriate spherical solder electrode 8 is formed. As a method of supplying solder to the solder electrode 8, a plating method, a vapor deposition method, a solder ball method, and a solder dipping method are mentioned as typical methods, but a plating method is often used for a so-called flip chip.
近年、超音波を利用したディップ法によりAl電極上に
直線はんだ電極を形成する方法が提案されているが、は
んだの均一な供給が困難であり、また十分なはんだ量の
供給が困難であるとされている。In recent years, a method of forming a straight solder electrode on an Al electrode by a dip method using ultrasonic waves has been proposed, but it is difficult to supply solder uniformly and it is difficult to supply a sufficient amount of solder. Have been.
上述した従来のはんだバンプ電極の形成方法は、はん
だめっき法を用いた場合、はんだめっきを行なうための
障壁金属層をはんだめっき終了後にエッチング除去する
際、はんだを劣化させない様にエッチング液とエッチン
グ方法を工夫しなければならない。また、絶縁膜２を厚
く形成した上で障壁金属層と電極としたはんだめっきを
行なうことは、障壁金属層の段差切れが発生し実現が困
難である。一方、はんだを超音波はんだディップにより
供給する方法を行なった場合、はんだの供給量にばらつ
きが発生し易く、これを制御することができない。ま
た、供給される半田量が少なく、電極の高さは30μｍ前
後あるいはそれ以下となり、従来行なわれていたフリッ
プチップと同様の実装を行なうことはできない。In the conventional method of forming a solder bump electrode described above, when a solder plating method is used, when a barrier metal layer for performing solder plating is removed by etching after completion of solder plating, an etching solution and an etching method are used so as not to deteriorate the solder. Must be devised. In addition, it is difficult to realize the formation of the thick insulating film 2 and then to perform the solder plating using the barrier metal layer and the electrode, because the barrier metal layer is stepped. On the other hand, when the method of supplying the solder by the ultrasonic solder dip is performed, the supply amount of the solder tends to vary, and this cannot be controlled. Further, the supplied amount of solder is small, and the height of the electrode is about 30 μm or less, so that the same mounting as the conventional flip chip cannot be performed.
本発明の半導体装置の製造方法は、能動領域が形成さ
れている半導体基板の前記能動領域に接触体を形成する
工程と、前記接触体に障壁金属層を形成する工程と、前
記接触体の上方に開口部を有するように前記障壁金属層
上にレジストのマスクを形成する工程と、前記マスクを
利用してめっき法により前記開口部を埋める金属層を形
成する工程と、前記レジストを除去して露出した前記障
壁金属層を除去する工程と、前記金属層の上面は薄くそ
の他の表面には前記金属層の厚さの半分程度の厚さに耐
熱性樹脂を被覆する工程と、ドライエッチングにより前
記金属層の上面及び上半分の側面を露出させる工程と、
はんだディップ法によりはんだバンプ電極を形成する工
程とを含んで構成される。A method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a contact in the active region of a semiconductor substrate in which an active region is formed; forming a barrier metal layer on the contact; Forming a resist mask on the barrier metal layer so as to have an opening, forming a metal layer filling the opening by plating using the mask, and removing the resist. Removing the exposed barrier metal layer, covering the upper surface of the metal layer with a thin heat-resistant resin to a thickness of about half the thickness of the metal layer on the other surface, and dry etching. Exposing the upper surface and the upper half side surface of the metal layer,
Forming a solder bump electrode by a solder dipping method.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｆ）は本発明の一実施例を説明する
ための工程順に示した断面図である。1 (a) to 1 (f) are cross-sectional views shown in the order of steps for explaining an embodiment of the present invention.
まず、第１図（ａ）に示すように、シリコン基板１の
上にAl電極３を設け、絶縁膜２で周囲を保護する。この
ように形成されたウェーハ全面に障壁金属層４をスパッ
タ法あるいは蒸着法により形成する。障壁金属層４は単
層あるいは多層からなり、Ti/Cu,NiCr/Cu等の構成によ
り、例えばTiを0.1μｍ、Cuを１μｍの厚さに形成す
る。First, as shown in FIG. 1 (a), an Al electrode 3 is provided on a silicon substrate 1, and the periphery is protected by an insulating film 2. A barrier metal layer 4 is formed on the entire surface of the wafer thus formed by sputtering or vapor deposition. The barrier metal layer 4 is composed of a single layer or a multilayer, and is formed of Ti / Cu, NiCr / Cu, or the like, for example, with a thickness of 0.1 μm for Ti and a thickness of 1 μm for Cu.
次に、第１図（ｂ）に示すように、レジスト５を障壁
金属層４の上に形成し、露光現像してAl電極３上に開口
部を形成する。ここで、レジストとしてドライフィルム
レジストを使用すると容易に50μｍ厚以上の膜厚を得る
ことが可能である。次に、障壁金属層４を電極として金
属めっきを行なう。めっき材としてはCu,Niなどのはん
だ濡れ性の良好な材料を使用し、電解めっきにより少な
くとも10μｍの厚い金属層を形成する。ここではCu層６
を形成するものとする。前述したドライフィルムレジス
トを使用し、厚さを50〜100μｍにすることにより金層
柱に近い金属層を得ることが可能である。Next, as shown in FIG. 1B, a resist 5 is formed on the barrier metal layer 4 and exposed and developed to form an opening on the Al electrode 3. Here, when a dry film resist is used as the resist, a film thickness of 50 μm or more can be easily obtained. Next, metal plating is performed using the barrier metal layer 4 as an electrode. As a plating material, a material having good solder wettability such as Cu or Ni is used, and a thick metal layer of at least 10 μm is formed by electrolytic plating. Here, Cu layer 6
Is formed. By using the dry film resist described above and setting the thickness to 50 to 100 μm, it is possible to obtain a metal layer close to the gold layer pillar.
次に、第１図（ｃ）に示すように、レジストを除去
し、電極周囲の障壁金属層４をエッチング除去する。障
壁金属層にTi/Cuを用い、Cuをスパッタ法で形成した場
合、そのCu層はめっきによるCu層６に比べて非常に薄い
ので、特にレジスト等による保護を行なわなくとも、電
極部のCu層を残すことができる。Cuエッチャントとして
はH2SO4とH2O2の水溶液が、また、Tiのエッチャントと
してはHFの水溶液が適用可能である。この様にして、Al
電極３上にCuの柱状電極を形成する。Next, as shown in FIG. 1C, the resist is removed, and the barrier metal layer 4 around the electrodes is removed by etching. When Ti / Cu is used for the barrier metal layer and Cu is formed by sputtering, the Cu layer is much thinner than the Cu layer 6 formed by plating. Layers can be left. An aqueous solution of H 2 SO 4 and H 2 O 2 can be used as the Cu etchant, and an aqueous solution of HF can be used as the Ti etchant. In this way, Al
A columnar electrode of Cu is formed on the electrode 3.
次に、第１図（ｄ）に示すように、比較的粘度の低い
ポリイミド等の耐熱性樹脂を1000rpm以下の低速回転で
スピン塗布し、スムージングを行なってポリイミド膜７
を形成する。ポリイミド膜中はCu層６の上では周囲より
も薄く形成される。このように形成されたポリイミド膜
７をドライエッチングして、第１図（ｅ）に示すよう
に、Cu層６表面のポリイミド膜は除去されるが、Cu層６
の周囲のポリイミド膜は残る条件にて処理して、柱状の
Cu層６の下部周囲を覆う。Next, as shown in FIG. 1 (d), a heat-resistant resin such as polyimide having a relatively low viscosity is spin-coated at a low speed of 1000 rpm or less, and smoothed to obtain a polyimide film 7.
To form The polyimide film is formed thinner on the Cu layer 6 than on the periphery. The polyimide film 7 thus formed is dry-etched to remove the polyimide film on the surface of the Cu layer 6 as shown in FIG.
The polyimide film around is processed under the remaining conditions,
The lower periphery of the Cu layer 6 is covered.
次に、第１図（ｆ）に示すように、はんだディップを
行なう事によりCu層６上部にはんだ電極８を形成する。Next, as shown in FIG. 1 (f), a solder electrode 8 is formed on the Cu layer 6 by performing a solder dip.
以上説明したように、本発明によれば、充分な高さの
はんだバンプ電極が得られ、半導体素子と実装基板との
間の熱膨張係数差によって発生する応力を吸収し、オー
プン不良を低減することができ、また、電極以外の半導
体素子表面は耐熱性樹脂により覆われているために、は
んだディップ後の工程において半導体素子表面が保護さ
れ、不良の発生率が大幅に低減されているという効果が
ある。As described above, according to the present invention, a solder bump electrode having a sufficient height is obtained, a stress generated due to a difference in thermal expansion coefficient between a semiconductor element and a mounting substrate is absorbed, and an open defect is reduced. In addition, since the surface of the semiconductor element other than the electrodes is covered with the heat-resistant resin, the surface of the semiconductor element is protected in the process after the solder dipping, and the occurrence of defects is greatly reduced. There is.
第１図（ａ）〜（ｆ）は本発明の一実施例を説明するた
めの工程順に示した断面図、第２図は従来の半導体装置
のバンプ電極近傍の一例を示す断面図である。 １……シリコン基板、２……絶縁膜、３……Al電極、４
……障壁金属層、５……レジスト、６……Cu層、７……
ポリイミド膜、８……はんだ電極。1 (a) to 1 (f) are sectional views showing steps in order to explain an embodiment of the present invention, and FIG. 2 is a sectional view showing an example near a bump electrode of a conventional semiconductor device. 1 ... silicon substrate, 2 ... insulating film, 3 ... Al electrode, 4
... Barrier metal layer, 5 ... Resist, 6 ... Cu layer, 7 ...
Polyimide film, 8 ... Solder electrode.
Claims (1)
記能動領域に接触体を形成する工程と、前記接触体に障
壁金属層を形成する工程と、前記接触体の上方に開口部
を有するように前記障壁金属層上にレジストのマスクを
形成する工程と、前記マスクを利用してめっき法により
前記開口部を埋める金属層を形成する工程と、前記レジ
ストを除去して露出した前記障壁金属層を除去する工程
と、前記金属層の上面は薄くその他の表面には前記金属
層の厚さの半分以下の厚さに耐熱性樹脂を被覆する工程
と、ドライエッチングにより前記金属層の上面及び上半
分の側面を露出させる工程と、はんだディップ法により
はんだバンプ電極を形成する工程とを含むことを特徴と
する半導体装置の製造方法。1. A step of forming a contact in the active region of a semiconductor substrate having an active region formed therein, a step of forming a barrier metal layer on the contact, and an opening above the contact. Forming a resist mask on the barrier metal layer, forming a metal layer filling the opening by plating using the mask, and removing the resist to expose the barrier metal. Removing the layer, coating the upper surface of the metal layer with a heat-resistant resin to a thickness less than or equal to half the thickness of the metal layer on the other surface, and dry etching to form the upper surface of the metal layer and A method of manufacturing a semiconductor device, comprising: exposing a side surface of an upper half; and forming a solder bump electrode by a solder dipping method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1157692A JP2785338B2 (en) | 1989-06-19 | 1989-06-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1157692A JP2785338B2 (en) | 1989-06-19 | 1989-06-19 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0322437A JPH0322437A (en) | 1991-01-30 |
| JP2785338B2 true JP2785338B2 (en) | 1998-08-13 |
Family
ID=15655299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1157692A Expired - Lifetime JP2785338B2 (en) | 1989-06-19 | 1989-06-19 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2785338B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7863739B2 (en) | 2001-03-05 | 2011-01-04 | Megica Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
| US7902679B2 (en) | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
| US7960270B2 (en) | 2002-01-07 | 2011-06-14 | Megica Corporation | Method for fabricating circuit component |
| US8021976B2 (en) | 2002-10-15 | 2011-09-20 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
| US8021921B2 (en) | 2002-10-25 | 2011-09-20 | Megica Corporation | Method of joining chips utilizing copper pillar |
| US8178967B2 (en) | 2001-09-17 | 2012-05-15 | Megica Corporation | Low fabrication cost, high performance, high reliability chip scale package |
| US8294279B2 (en) | 2005-01-25 | 2012-10-23 | Megica Corporation | Chip package with dam bar restricting flow of underfill |
| US8481418B2 (en) | 2002-05-01 | 2013-07-09 | Megica Corporation | Low fabrication cost, high performance, high reliability chip scale package |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3053675B2 (en) * | 1991-09-09 | 2000-06-19 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
| US6042953A (en) * | 1996-03-21 | 2000-03-28 | Matsushita Electric Industrial Co., Ltd. | Substrate on which bumps are formed and method of forming the same |
| AU2073599A (en) * | 1998-01-20 | 1999-08-02 | Citizen Watch Co. Ltd. | Semiconductor device and method of production thereof and semiconductor mountingstructure and method |
| WO2000010369A1 (en) | 1998-08-10 | 2000-02-24 | Fujitsu Limited | Method of forming solder bump, method of mounting electronic device, and mounting structure of electronic device |
| JP2000150703A (en) * | 1998-11-06 | 2000-05-30 | Sony Corp | Semiconductor device and assembling method thereof |
| JP4688362B2 (en) * | 2001-07-25 | 2011-05-25 | セイコーインスツル株式会社 | Solder bump electrode and manufacturing method thereof |
| JP3829325B2 (en) | 2002-02-07 | 2006-10-04 | 日本電気株式会社 | Semiconductor element, manufacturing method thereof, and manufacturing method of semiconductor device |
| JP2009164442A (en) * | 2008-01-09 | 2009-07-23 | Nec Electronics Corp | Semiconductor device |
| JP2010238886A (en) * | 2009-03-31 | 2010-10-21 | Seiko Npc Corp | Semiconductor device and manufacturing method thereof |
| FR3011120A1 (en) * | 2013-09-24 | 2015-03-27 | St Microelectronics Crolles 2 | CHIP OF INTEGRATED CIRCUITS MOUNTED ON A SUPPORT |
-
1989
- 1989-06-19 JP JP1157692A patent/JP2785338B2/en not_active Expired - Lifetime
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8138079B2 (en) | 1998-12-21 | 2012-03-20 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
| US7902679B2 (en) | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
| US7863739B2 (en) | 2001-03-05 | 2011-01-04 | Megica Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
| US8072070B2 (en) | 2001-03-05 | 2011-12-06 | Megica Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
| US8158508B2 (en) | 2001-03-05 | 2012-04-17 | Megica Corporation | Structure and manufacturing method of a chip scale package |
| US8368213B2 (en) | 2001-03-05 | 2013-02-05 | Megica Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
| US9369175B2 (en) | 2001-09-17 | 2016-06-14 | Qualcomm Incorporated | Low fabrication cost, high performance, high reliability chip scale package |
| US8178967B2 (en) | 2001-09-17 | 2012-05-15 | Megica Corporation | Low fabrication cost, high performance, high reliability chip scale package |
| US8461679B2 (en) | 2002-01-07 | 2013-06-11 | Megica Corporation | Method for fabricating circuit component |
| US7960270B2 (en) | 2002-01-07 | 2011-06-14 | Megica Corporation | Method for fabricating circuit component |
| US8890336B2 (en) | 2002-01-07 | 2014-11-18 | Qualcomm Incorporated | Cylindrical bonding structure and method of manufacture |
| US8481418B2 (en) | 2002-05-01 | 2013-07-09 | Megica Corporation | Low fabrication cost, high performance, high reliability chip scale package |
| US8742580B2 (en) | 2002-10-15 | 2014-06-03 | Megit Acquisition Corp. | Method of wire bonding over active area of a semiconductor circuit |
| US8026588B2 (en) | 2002-10-15 | 2011-09-27 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
| US9142527B2 (en) | 2002-10-15 | 2015-09-22 | Qualcomm Incorporated | Method of wire bonding over active area of a semiconductor circuit |
| US9153555B2 (en) | 2002-10-15 | 2015-10-06 | Qualcomm Incorporated | Method of wire bonding over active area of a semiconductor circuit |
| US8021976B2 (en) | 2002-10-15 | 2011-09-20 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
| US8421222B2 (en) | 2002-10-25 | 2013-04-16 | Megica Corporation | Chip package having a chip combined with a substrate via a copper pillar |
| US8021921B2 (en) | 2002-10-25 | 2011-09-20 | Megica Corporation | Method of joining chips utilizing copper pillar |
| US8294279B2 (en) | 2005-01-25 | 2012-10-23 | Megica Corporation | Chip package with dam bar restricting flow of underfill |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0322437A (en) | 1991-01-30 |
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