JP2785327B2 - Display control device and display device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a CRT display device and a flat display device such as a liquid crystal (hereinafter referred to as LCD) display device or a plasma (hereinafter referred to as PDP) display device. The present invention relates to a horizontal synchronization timing of a display control circuit capable of displaying by switching operation modes.

[Summary of the Invention]

The present invention relates to a display control circuit that can select and display both a CRT display device and a flat display device such as an LCD display device or a PDP display device by switching operation modes, particularly when driving a flat display device. By setting the start timing of the horizontal display data to be the same clock timing as the switching timing of the horizontal synchronization signal, the display on the flat display device can be performed without adding a circuit such as a counter or increasing the number of timing signals. This realizes a display control circuit capable of performing horizontal display position adjustment necessary for performing the display control circuit.

[Conventional technology]

The conventional display control circuit controls the start timing of the horizontal display data even when displaying on a flat display device.
(1) Counting the number of clocks from the switching timing of the horizontal synchronization signal to the data start timing, and giving the display start timing to the flat display device, (2) the horizontal synchronization signal Apart from the above, a valid data period is provided by a signal (DISP signal) exactly the same as the display period.

[Problems to be solved by the invention]

The above-mentioned prior art enables horizontal display position alignment, but has the following disadvantages.

That is, in the method (1), since a circuit such as a counter and a shift register is added as an interface, the cost of an additional circuit part is increased, and the substrate area of the display control circuit is increased, which hinders miniaturization of the entire system. It was something. In the method (2), the signal line connecting the display control circuit unit and the flat display device is connected to DI.
The addition of one SP signal line increased the technical difficulties in dealing with electromagnetic interference (EMI) and increased costs.

Accordingly, an object of the present invention is to solve such a problem and to provide a method for realizing horizontal display alignment without increasing the number of interface circuits and signal lines.

[Means for solving the problem]

The display control device of the present invention is a display control device for selectively displaying a CRT display device and a flat display device such as an LCD according to an operation mode switching, wherein a vertical synchronization signal is supplied to a display driver circuit for driving the flat display device. A display control circuit for transmitting a horizontal synchronization signal, display data, and a shift clock signal for taking in the display data. The display control circuit determines a horizontal pixel number counter and a timing of the horizontal synchronization signal. A horizontal synchronizing signal register, and a comparator for comparing an arbitrary value stored in the horizontal synchronizing signal register with the horizontal pixel number counter, wherein the operation mode is the flat display device, A horizontal synchronization signal that matches the timing of driving the CRT display device based on the output of the comparator is used as a horizontal synchronization signal that drives the flat display device. It converted to, and transmission start of a horizontal synchronizing signal and a horizontal direction of the display data for the flat display device is characterized by being controlled to be synchronized.

Further, the display device of the present invention includes a display driver that receives the output of the display control device and drives the flat display device, and a flat display device that is driven by the display driver and displays data. I do.

[Action]

The display control circuit of the present invention controlled as described above, since the switching timing of the horizontal synchronizing signal coincides with the output timing of the first horizontal display data, uses the switching timing of the horizontal synchronizing signal as a trigger to trigger the flat display. The apparatus only needs to start shifting in the display data, and horizontal display positioning can be performed without the need to generate a start timing by an interface circuit or adding a DISP signal or the like.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to examples. First
The figure shows an example in which a display control circuit according to the present invention is connected to an LCD module as an example of a flat display panel.
The vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC are input to the LCD driver circuit 2 in the LCD module 4, and determine the vertical and horizontal start positions of the display, respectively. Display data signal
DATA is input to the shift register in the LCD driver circuit 2 by the shift clock CLK, converted into a voltage, and applied to the liquid crystal display cell 3.

FIG. 2 shows display data and HSYNC of the display control circuit of the present invention.
FIG. 3 is a diagram showing the output timing corresponding to the register inside the display control circuit, and FIG. 3 is a diagram showing it in a timing chart.

As shown in FIGS. 2 and 3, the first display data (data indicated by) of each horizontal display line is output at the same clock timing as the leading edge (rising edge) of HSYNC in this example. Is controlled by the display control circuit. LCD driver circuit 2 is HSYNC
, The start position of the horizontal display data is detected based on the switching timing (in this case, the rising timing), and shift-in of the display data DATA is started, so that accurate horizontal display position alignment is possible.

Generally, a flat display device is different from a CRT display device in that pixels corresponding to the resolution of display data are physically built in the device. Therefore, if the start timing of the display data is displaced even by one dot, the first data or the last data of each line does not correspond to a pixel, and a fatal malfunction occurs that data to be displayed is lost. In particular, horizontal display alignment is an important technique since the frequency of the data shift-in clock is higher than that in the vertical direction, and one of the significance of the present invention is here.

On the other hand, FIG. 4 shows an example in which a conventional display control circuit and an LCD module are connected, and the horizontal display data start timing HS
It has the drawback that a circuit for generating YNC 'is required. Usually, this circuit is a circuit for counting the number of clocks from the rising or falling edge of HSYNC to the start of display data, and is constituted by a counter or a shift register.

FIG. 5 is a diagram showing display data and output timing of HSYNC of a conventional display control circuit so as to correspond to an internal register of the display control circuit, and FIG. 6 is a timing chart.

Generally, the display control circuit has a large number of programmable registers in the circuit in order to support display devices having various resolutions, and the resolution can be changed by changing the programming value of the register. R ₁ , R ₂ , R ₃ and R ₄ shown in FIG. 2 of the present invention are register values, which correspond to the horizontal total, horizontal display enable end, HSYNC start and HSYNC end, respectively. The same applies to the case of the conventional example shown in FIG.

In the case of a circuit that displays only the CRT, like a conventional display control circuit, the HSYNC pulse is output between the horizontal display enable end position and the horizontal total, as shown in the timing of FIG. In general, a circuit for generating the display data start timing as shown in FIG. 4 is required.

Here, in the conventional example, it seems that the program values R ₃ ′ and R ₄ ′ of the registers may be simply programmed as R ₃ ′ = 0 and 0 <R ₄ ′ <R ₂ as in the present invention. In recent years, there has been a need for display on a flat display device that can be made thinner, and since a conventional display control circuit has been premised on display on a CRT display device, HSYNC as in the present invention is used. Cannot be set at an arbitrary timing, or a normal circuit operation cannot be performed unless the program value satisfies a certain condition premised on display on a CRT.

FIG. 7 shows an HSYN for realizing the display control circuit of the present invention.
1 shows an example of a C generation circuit. 10 is a counter corresponding to the number of pixels in the horizontal direction, and 11 and 12 are HSYNC start R ₃ ,
A register to program the HSYNC end R _4. 8th
As shown in the timing chart of the figure, the contents of the n bits of the counter 10 and the values of the registers R ₃ and R ₄ are compared with the comparators 13 and 14.
And J-KF / F16
HSYNC can be obtained as the output of the F / F if the input of is activated. As is clear from the circuit operation,
R ₃ and R ₄ can be set to any values from zero to the maximum value of the horizontal counter 10, and an HSYNC output at any timing can be obtained. Further, there is no influence on other circuit operations of the display control circuit.

〔The invention's effect〕

As described above, when driving the flat display device as in the present invention, if the switching timing of the horizontal synchronization signal HSYNC is controlled by the clock timing simultaneous with the display data start timing in the horizontal direction, a counter, a shift register, etc. The horizontal alignment of the display can be performed without adding the circuit described above and without increasing the number of signal lines such as the display timing signal DISP.

[Brief description of the drawings]

FIG. 1 is a diagram showing a connection between a display control circuit of the present invention and an LCD module. 1. Display control circuit 4. LCD module FIG. 2 is a view showing display data and output timing of a horizontal synchronization signal HSYNC of a display control circuit of the present invention. FIG. 3 is a timing chart of one horizontal line of the display control circuit of the present invention. FIG. 4 is a diagram showing a connection between a conventional display control circuit and an LCD module. 9 Horizontal display data start timing generation circuit FIG. 5 is a diagram showing output timing of display data and a horizontal synchronization signal HSYNC of a conventional display control circuit. FIG. 6 is a timing chart of one horizontal line of a conventional display control circuit. FIG. 7 is a diagram showing an example of an HSYNC generating circuit of the display control circuit of the present invention, and FIG. 8 is a timing chart showing the operation thereof.

Claims (2)

(57) [Claims] 1. A CRT display device according to an operation mode switching.
A display control device for selectively displaying a flat display device such as a CD, a shift clock for capturing a vertical synchronization signal, a horizontal synchronization signal, display data, and the display data in a display driver circuit for driving the flat display device. A display control circuit for transmitting each signal of the above, the display control circuit, a horizontal pixel number counter, a horizontal synchronization signal register to determine the timing of the horizontal synchronization signal, and any stored in the horizontal synchronization signal register A comparator for comparing the value with the horizontal pixel number counter.If the operation mode is the flat display device, the horizontal mode matches the timing for driving the CRT display device based on the output of the comparator. A synchronization signal is converted into a horizontal synchronization signal timing for driving the flat panel display device, and a horizontal synchronization signal for the flat panel display device and a horizontal table are converted. Display control apparatus characterized by transmission start data is controlled to be synchronized. 2. The display device according to claim 1, further comprising: a display driver that receives the output of the display control device and drives the flat display device; and a flat display device that is driven by the display driver and displays data. A display device using the display control device described in the above.