JP2785006B2 - Multiplexing / demultiplexing method in FC / ATM network interconversion equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to communication between N ports having Fiber Channel (hereinafter, FC) interfaces arranged at a distance from each other via an asynchronous transfer mode network (hereinafter, referred to as an ATM network). In particular, F
In services that require return of confirmation frames belonging to class 1 and class 2 of the C standard, when performing full-duplex communication,
FC / AT that improves transmission efficiency by preventing an increase in data frame transmission time due to waiting for return of a confirmation frame
The present invention relates to a multiplexing / demultiplexing method in an M network interconversion device.

[0002]

2. Description of the Related Art Conventionally, connection between an FC network and an ATM network has not been made publicly, and no conventional example is found. However, in the FC standard (ANSI standard X3T11), there is a definition of a data frame transmission procedure between N ports.
It is mandatory to return a confirmation frame. This is to prevent overflow of the opposite receiving buffer, and suppresses transmission of data frames on the transmission side so as not to exceed a value EE called the end_end_credit number reserved in advance. EE represents the size represented by the number of frames in the reception buffer, and the larger this value is, the more data frames can be transmitted at one time.

The above-mentioned N port refers to a Node port provided in terminals 110 and 120, as shown in FIG. 8, to which data from each terminal 110 and 120 is input and exchanged. The port of the switching apparatus 100 that performs the above operation is called an F port. Note that TX and RX in FIG. 7 indicate a transmission terminal and a reception terminal, respectively. On the other hand, the number Nr of data frames received by the opposite reception buffer is inserted into the header of the confirmation frame and notified. When the number of transmitted data frames is Ns, the N port on the transmitting side calculates the number of spare frames in the opposite receiving buffer using Expression (1). That is, EE-Ns + Nr [frame] (1) Further, it is allowed to further transmit a data frame of a number equal to the value.

Here, in the state of Nr <Ns, out of Ns transmitted data frames, (Ns-Nr) frames are still on the transmission line and have not arrived at the opposite N port. Then, when Nr = Ns at a certain point in time when the confirmation frame is received, a new number of data frames represented by Expression (2) can be transmitted. That is, EE−Ns + Nr = EE [frame] (2) Only one EE data frame can be transmitted at a time, and the next data frame cannot be transmitted until a confirmation frame is received.

[0005]

If such a conventional technique is applied to a transmission method via an ATM network as it is, it takes a long time to transmit a large number of data frames. The reason is that the delay of the confirmation frame due to FC / ATM conversion cannot be ignored, and the time for waiting for the confirmation frame increases, and during that time, the data frame cannot be transmitted.

In other words, if a large number of data frames are transmitted at a time and the value "EE" is set to a large value, the queue of data frames in the FC / ATM converter increases in proportion to the value, and therefore, the number of confirmation frames increases. The waiting time that must wait until transmission of all data frames that have arrived before that is completed increases. When the arrival of the confirmation frame is delayed, the next data frame to be transmitted is made to wait, and as a result, the required transmission time of the data frame increases.

Accordingly, an object of the present invention is to reduce the waiting time of a confirmation frame at an N port connected to the present apparatus as much as possible. It is another object of the present invention to reduce the waiting time of the confirmation frame at the opposite N port as much as possible. That is, the transmission efficiency of the data frame is improved by reducing the waiting time of the confirmation frame at both N ports.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method in which an N port having an FC interface as an optical fiber channel interface and an ATM network as an asynchronous transfer mode network are provided. And an FC frame receiver that receives an FC frame from the N port, first and second memories in which output frames of the FC frame receiver are respectively distributed and accumulated via a first switch, A first and a second segmenter for inputting each FC frame of the second memory and converting the frame into an ATM cell having a virtual channel identifier having a unique value;
FC / ATM consisting of a multiplexer for transmitting to the M network
An ATM cell receiver for receiving an ATM cell from the ATM network, a demultiplexer for separating the ATM cell output from the ATM cell receiver, and an FC for receiving each of the separated ATM cells. First and second reassembly units for converting frames, third and fourth memories respectively storing FC frames from the respective reassembly units, and third and fourth memory units via a second switch.
A FC / ATM network interconversion apparatus provided with an ATM / FC conversion unit comprising an FC frame transmitter for extracting each FC frame from the memory of the above and transmitting the frame to the N port. A detection frame is detected, a first switch and a multiplexer are controlled according to the detection result, a first path connecting the first memory and the first segmenter, and a second memory and the second segmentation are connected. The first selecting means for selecting one of the second paths connecting the devices is the FC / A
When the virtual channel identifier detected in the output cell of the ATM cell receiver indicates a confirmation frame, the demultiplexer and the second switch are controlled, and the first reassembly unit and the third reassembly unit are provided. 3rd link with the memory of
The above-mentioned ATM / FC conversion unit is provided with a second selecting means for selecting one of the path of the second and the fourth path connecting the second reassembly unit and the fourth memory.

Therefore, the confirmation frame transmitted from the N port to the opposing N port via the device is immediately transmitted to the ATM cell prior to the data frame stored in the memory of the device and waiting to be transferred to the opposing N port. Converted ATM
Sent to the network. The confirmation frame in the cell input from the ATM network is immediately transferred to the N port prior to the data frame stored in the memory and waiting to be transferred. As a result, the waiting time of the confirmation frame at the N port and the opposite N port is reduced, and thus the transmission efficiency of the data frame can be improved. Further, the number of output terminals of the first switch and the number of input terminals of the second switch are each N + 1, the degree of multiplexing in the multiplexer and the demultiplexer is N-multiplexed, and The other path is configured as N parallel connections, a third switch having N + 1 input terminals and N output terminals is connected between the N + 1 segmenter and the multiplexer, and the third switch is connected to the third switch. And the other of the fourth paths is connected in N parallel connections, and a fourth switch having N input terminals and N + 1 output terminals is connected to N + 1
This is connected between the reassembly units and the demultiplexer. Therefore, both the FC / ATM converter and the ATM / FC converter perform N parallel processing of data. As a result, the present apparatus can cope with a high-speed ATM network with inexpensive and low-speed circuit components, and therefore can be economically constructed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the FC / ATM mutual conversion device of the present invention. In this figure, the present apparatus converts an FC frame input from an FC frame input terminal Fin into an ATM cell, and outputs an ATM cell output terminal Aou.
FC / ATM converter 1 that outputs from t ((a) in the figure)
And reversely converts the ATM cell input from the ATM cell input terminal Ain into an FC frame and outputs the FC frame output terminal Fou.
and an ATM / FC converter 2 ((b) in FIG. 4) which outputs the data from the t.

The FC / ATM converter 1 shown in FIG. 1A includes an FC frame receiver 11, a switch 12,
7, data frame memory 13, confirmation frame memory 14, segmenter (SEGM) 15, 1
6, an ATM cell transmitter 18, and a confirmation frame detection / control circuit 19. Then, the switch 17 operates as a multiplexer. Next, the ATM / FC converter 2 shown in FIG. 1B includes an ATM cell receiver 21, switches 22, 27, and reassembly units (RASM) 23, 2.
4, a data frame memory 25, a confirmation frame memory 26, an FC frame transmitter 28, and a VCI detection / control circuit 29. Then, the switch 22 operates as a demultiplexer. The four memories 13, 14, 25, 26 are used for speed adjustment because the data speeds of the ATM line and FC are different.

Next, an outline of the operation of the present apparatus will be described with reference to FIG. The FC frame input from the N port (not shown) to the input terminal Fin is a so-called 10-bit code in which one byte is represented by 10 bits. This is a code designed to maintain DC balance and facilitate clock extraction. The input FC frame is optically / electrically converted by the FC frame receiver 11, and then one byte is inversely converted into an 8-bit code. The FC frame output from the FC frame receiver 11 is input to the confirmation frame detection / control circuit 19, and the header of the frame is checked.

The reason why two output lines are output from the FC frame receiver 11 is to pass the frame header to the confirmation frame detection / control circuit 19 earlier in the receiving process, and to control the switch 12 in time. Is the purpose. Between the two output lines, for example, a buffer having a byte size of the size of the header is incorporated. Confirmation frame detection / control circuit 1
9 checks the header, and if it is determined that the frame is a confirmation frame, switches the switch 12 to the confirmation frame memory 14.
To accumulate. In the case other than the confirmation frame, the switch 12 is switched and the data is stored in the data frame memory 13. The term other than the confirmation frame here means that the confirmation frame is excluded,
It also includes data frames, commands (request frames), and responses (response frames). In this example,
The description as a data frame memory is merely for simplicity, and does not store only data frames.

Each of the FC frames read from each of the memories 13 and 14 is independently provided with a segmenter (SE).
GM) 15 and 16, the ATM cell is divided into 48-byte ATM cells, and a 5-byte header is added to each
It becomes a cell. The last cell at the end of the frame is provided with an 8-byte trailer, and padding of the required number of bytes is inserted between the data and the trailer to form a 53-byte cell. The above description is based on AAL5 (A
This is the case of a protocol called TM adaptation layer 5), but it is not always necessary to use this protocol.

In such a conversion process, the segmentation units 15 and 16 add the destination address (Destina) contained in the header of the FC frame to the header of the cell.
VPI (virtual path identifier) corresponding to (tion_ID)
And VCI (virtual channel identifier) are set. VP
The correspondence between I and VCI and the destination address (counter N port address) is determined in advance, and the correspondence information is held inside the apparatus. The segmenters 15 and 16 add different VCIs to the header. In addition,
The VPI may be common. Segmentation devices 15, 16
Are multiplexed by the switch 17 and subjected to electrical / optical conversion by the ATM cell transmitter 18, and then transmitted from the terminal Aout to the ATM line. On the ATM line, VCIs different from the cells of the confirmation frame and the other cells are allocated.

Conversely, a cell input from the ATM line is
The ATM receiver 21 performs optical / electrical conversion to extract cells, and the VCI detection / control circuit 29 detects VCI. Here, the reason why two output lines are output from the ATM cell receiver 21 is to make up for the processing at the subsequent stage, similarly to the reason in the case of the FC frame receiver 11, and the two output lines are also used. As an example, a buffer having a byte size of the size of the header is provided between the output lines. Since the VCI is different between the confirmation frame and the other frames, it can be identified as a confirmation frame. In the case of the confirmation frame, the switch 22 is switched, and the cell is output to the reassembly unit (RASM) 23. Other cells are transmitted to the reassembly unit 24 by switching the switch 22. The reassembly units 23 and 24 operate independently, remove the cell header, trailer, and padding, and restore the original FC frame transmitted by the opposite N port.

As a result, the confirmation frame is stored in the confirmation frame memory 26, and the other frames are stored in the data frame memory 25. The switch 27 is connected to the data frame memory 25 when the frame is not a confirmation frame. When the confirmation frame is written into the confirmation frame memory 26, the switch 27 is switched, and the confirmation frame is immediately passed to the FC frame transmitter 28. As a result, the FC frame transmitter 28 converts one byte into a 10-bit code, performs electrical / optical conversion, and transmits it as an FC frame to the N port. The FC frame transmitter 28 and the FC frame receiver 11 control all of the FC layers FC-0 (physical layer) and FC-1 (code layer) and the frame processing unit of FC-2 (protocol layer). Has been realized.

When the connection is established prior to the communication, the VPI and VCI on the transmitting side and the VP on the receiving side are set.
Since the correspondence between I and VCI is determined, the correspondence information of VCI is stored in the present converter. The VCI detection / control circuit 29 allocates cells based on the VCI correspondence information. This is because the VPI and VCI may be replaced by an exchange or the like in the ATM network.

Next, FIG. 2 is a block diagram showing another example of the configuration of the present conversion apparatus, which is an example of data parallel processing.
In this example, the number of parallel processes N = 4. Here, the FC / ATM converter 1 shown in FIG. 2A includes data frame memories 131 to 134, a confirmation frame memory 14, and segmentation units 151 to 154 and a segmentation unit 16 connected to them. Be composed. In this case, the confirmation frame is processed by the confirmation frame memory 14 and the segmenter 16 as in the example of FIG. Frames other than the confirmation frame
The data is processed by the data frame memories 131 to 134 and the segmenters 151 to 154. The newly provided switch 31 has five input terminals 0 to 4 and connects four signals to four output terminals 0 to 3. The multiplexer (MUX) 32 stores 4 cells.
The data is multiplexed and transmitted to the ATM transmitter 18.

Next, the ATM / FC converter 2 shown in FIG. 2 (b) includes reassembly units (RASM) 231 to 234,
The reassembly unit 24 includes data frame memories 251 to 254 and a confirmation frame memory 26 connected thereto. The confirmation frame is processed by the reassembly unit 24 and the confirmation frame memory 26, and the frames other than the confirmation frame are reassembled by the reassembly units 231-2.
34 and data frame memories 251 to 254. The newly provided switch 42 has four input terminals of Nos. 0 to 3 and connects them to four output terminals of the five output terminals of Nos. 0 to 4. The demultiplexer (DMUX) 41 divides the multiplexed cell into quarters and outputs the multiplexed cells to the four input terminals of the switch 42. Other configurations are the same as those in FIG.

Next, the detailed operation of the present apparatus configured as shown in FIG. 2 will be described with reference to the respective timing charts of FIGS. FIG. 3 is a timing chart showing the operation of converting the FC frame into the ATM cell in the FC / ATM conversion unit 1 in FIG. Numbers 15 to 21 on the timing chart of the input terminal Fin are FC frame numbers. In the timing diagram of the input terminal Fin shown in FIG. 3, the data frames 1 to 14 are not shown, but are shown starting from the data frame after the data frame 15.
It is assumed that the data frames 1 to 14 have already been input to the apparatus from the input terminal Fin before the data frame 15. The confirmation frame ACK_N is sandwiched between the 19th and 20th. The frame length of the FC frame is 36 to 2148 bytes, and the confirmation frame has a frame length of 36 bytes, which is shorter than the data frame.

Here, the confirmation frame detection / control circuit 19
When the confirmation frame ACK_N is detected in step (1), the confirmation frame detection / control circuit 19 outputs a signal “1”. With this as a trigger, the switch 12 is switched to output number 4
And outputs the confirmation frame ACK_N to the confirmation frame memory 14. By this time, the segmenters 151 to 154 (corresponding to SEGMs 00 to 03 in FIG. 3, respectively) have already processed the data frame from the first which has already been input to the apparatus. This delay is due to the difference between the writing speed of the FC frame and the reading speed of the ATM cell conversion. This delay varies depending on the data frame transmission status, and how many frames are delayed depends on the congestion of the data frame memories 151 to 154 at that time.

Now, in this example, the confirmation frame ACK_N
Is detected, the segmentation unit 151
(SEGM00) is the data frame No. 9, and the segmentation unit 152 (SEGM01) is the data frame No. 6.
The segmenter 153 (SEGM02) sets the data frame number 7 to the segmenter 154.
(SEGM03) cell number 8 of the data frame. Among them, since the data frame No. 6 has been input to the segmentation unit 152 earliest, the cell formation ends the earliest. When the segmentation unit 152 completes the cellification of the data frame No. 6, the segmentation unit 152 is stopped, and the segmentation unit 16 (corresponding to SEGM1 in FIG. 3) is operated instead. The confirmation frame A stored in the segmenter 16
CK_N is input and cell conversion is performed immediately. The segmenter 16 is stopped at other times.

When the cell of the acknowledgment frame ACK_N is output from the segmenter 16, the switch 31
Input number 4 is connected to output number 1 and the confirmation frame AC
K_N is output to the multiplexer 32 (corresponding to the MUX in FIG. 3). At this time, the input number 1 of the switch 31 is open and is not connected to any output terminal. From the point of view of the multiplexer 32, only the input signal has changed,
The multiplexing operation does not need to be changed at all. After the segmentation unit 16 (SEGM1) converts the confirmation frame ACK_N into a cell, the segmentation unit 152 (SEG1)
EGM01) operates, and the next data frame No. 10 is taken into cells. Thereafter, the same operation as before the input of the confirmation frame ACK_N is continued.

Next, the operation of the ATM / FC converter 2 of FIG. 2B will be described with reference to the timing chart of FIG. FIG. 4 is a timing chart when the FC frame is restored from the ATM cell. The ATM cell received from the input terminal Ain includes the confirmation frame ACK_N transmitted from the opposite N port. The VCI detection / control circuit 29 uses the VCI to check the confirmation frame ACK_
N is detected, and a signal of "1" is generated as a detection result. This is a trigger for switching the switch 42.

The demultiplexer 41 (corresponding to DMUX in FIG. 4) sequentially outputs the input cells from four output terminals. Since the order of arrival of the ATM cells multiplexed and transmitted by the multiplexer 32 (MUX) on the transmission side is guaranteed in the ATM network, the ATM cells are transmitted and separated by the demultiplexer 41 in the same order as the order of the cells. When the demultiplexer 41 receives the cell of the confirmation frame ACK_N, for example, the cell of the data frame No. 17 from the output terminal No. 0 (corresponding to DMUX output 0 of FIG. 4) is output to the output terminal No. 1 (FIG.
No. 2 cell (corresponding to DMUX output 2 in FIG. 4) from the 18th cell of data frame to the second output terminal (corresponding to DMUX output 2 in FIG. 4)
, The cell of the data frame No. 15 is output from the output terminal No. 3 (corresponding to the DMUX output 3 in FIG. 4).

In the switch 42, the four outputs from the demultiplexer 41 are input terminal 0 to output terminal 0, input terminal 1 to output terminal 1, input terminal 2 to output terminal 2, and input terminal 2 to output terminal 2. Terminal No. 3 is connected to output terminal No. 3 respectively. Therefore, the reassembly unit 231 (FIG. 4)
To the reassembly unit 232 (corresponding to RASM01 in FIG. 4) and the reassembly unit 233 (corresponding to RASM02 in FIG. 4). Indicates that the cell of the data frame 15 is the reassembly unit 234 (R in FIG. 4).
(Corresponding to ASM03), the cell of the data frame 16 is input. When the cell of the confirmation frame ACK_N is detected, the reassembly unit 233 (RASM)
02), the second input terminal of the switch 42 is connected to the fourth output terminal, and the cell of the confirmation frame ACK_N is output to the reassembly unit 24 (corresponding to RASM1 in FIG. 4). I do. Reassembly unit 2
At 33 (RASM02), there is no input during this period, and the operation is stopped.

The reassembly unit 24 (RASM1) uses FC
The confirmation frame ACK_N restored to the frame is output to the fourth input terminal of the switch 27 via the confirmation frame memory 26. The switch 27 immediately connects the fourth input terminal to the output terminal, and sends a confirmation frame ACK_N to the FC frame transmitter 28. At this time, the switch 27
The input terminal of No. 1 jumps over the original No. 2 after the No. 1 and the No. 4 is selected, then returns to the No. 2 and thereafter returns to the original order.
Therefore, when viewed from the output terminal Fout, the confirmation frame ACK_N (the fourth input terminal of the switch 27) is interposed after the data frame No. 10 (the first input terminal of the switch 27), and then the data frame No. 11 (the switch input terminal of the switch 27). 27 second input terminal) is transmitted. The delay of the data frame between the output terminal Fout and the reassembly units 231 to 234 (RASM00 to 03) is caused by the data frame memories 251 to 251 because the speed of the ATM cell differs from that of the FC frame.
254 buffer operations. Here, which of the four parallel circuits temporarily stops due to the interruption of the confirmation frame ACK_N depends on the data frame reception status at that time, and the above description is an example.

As described above, the acknowledgment frame ACK_N is immediately transferred to the transmitting side and the receiving side immediately, bypassing the queue of data frames stored in the speed adjusting memory. Here, the ATM line is 622.08 Mb
If the speed is ps, the segmentation units 151 to 1
54 (SEGM00-03), segmenter 1
6 (SEGM1) and reassembly units 231 to 23
4 (RASM 00-03), reassembly unit 24 (RA
SM1) operate at a rate of 155.52 Mbps. Among them, N = 4 circuits are operating at the same time. Therefore, when viewed at the input terminal Ain or the output terminal Aout, 45.55.5 Mbps cells are required. Multiplexed 62
At a speed of 2.08 Mbps, the entire band is transmitted exclusively.

Next, an example in which full-duplex communication is performed between N ports will be described with reference to the sequence diagram of FIG.
In this example, the FC is faster than the ATM line, and the transmission time interval for each data frame is FC
This is an example in which a frame is narrower than an ATM cell transmission interval. FIG. 5 shows a case where two N ports A and E are separated from each other via an ATM network C. Both N ports A and E are connected to an ATM network C via converters B and D, respectively. Here, in FIG. 5, the horizontal direction indicates the distance, and the vertical axis indicates the time, and the time elapses from the upper direction to the lower direction in the figure.

First, it is assumed that a series of data frames indicated by a dotted line from the opposite N port (N port E) is transmitted to the N port A via the conversion device D → the ATM network C → the conversion device B. In this case, the conversion device D sets the FC frame to A
The data is converted into a TM cell, and the conversion device B converts the data back into an FC frame again. When a series of data frames reaches N port A, a confirmation frame ACK_N is returned from N port A. Here, “N” of the confirmation frame ACK_N is N
It represents the number of data frames received by port A. In this example, N = 4. However, in this case, since full-duplex communication is performed, N port A transmits a series of data frames indicated by solid lines in the figure independently to the opposite N port E at this time. The order in which the conversion device B receives the acknowledgment frame ACK_N is the sixth in the data frame. Then, at this time, at the conversion device B, when the first data frame has been transmitted, the second and subsequent data frames are still left in the memory as a queue.

As described above, this confirmation frame A
CK_N is transmitted to the ATM network immediately after the first data frame. Thereafter, the second and subsequent data frames are sequentially transmitted. In other words, the acknowledgment frame ACK_N received sixth by the converter B is carried up secondly and transmitted from the converter B to the ATM network C. Here, it is assumed that when the confirmation frame ACK_N is received by the conversion device D, the first data frame has not been transferred yet. As described above, also in this direction, the acknowledgment frame ACK_N has priority, and is immediately transferred to the opposite N port E before the first data frame is transferred. Therefore, the acknowledgment frame ACK_N is transferred from the second to the first on this transmission path. Therefore,
FC / ATM conversion and ATM / FC with two converters B and D
By receiving the inverse conversion, the confirmation frame ACK_N
Arrives at the opposite N-port E, where the sixth order transmitted from N-port A goes up to the first.

Here, an example in which the transfer control of the confirmation frame is not performed will be described with reference to FIG. 7, as compared with the example of the transfer control of the confirmation frame ACK at the time of the full duplex communication. In the example shown in FIG. 7, only the handling of the confirmation frame is different from that in FIG. 5, and the other conditions are the same. Where N
Before transmitting the confirmation frame ACK_N on the port A,
It is assumed that five data frames have already been transmitted to the converter B side. In this case, the conversion device B receives these five data frames and transmits them to the ATM network 3 side, and then transfers the confirmation frame ACK_N to the ATM network C. When the acknowledgment frame ACK_N arrives at the conversion device D, the conversion device D queues the acknowledgment frame ACK_N in the memory 12 until the transfer is completed because there is a transfer remainder of the data frame received up to that time. And accumulate it. As a result, the arrival of the confirmation frame ACK_N at the opposite N port E is delayed.

That is, in this example, since the confirmation frame is treated in the same way as a normal data frame, a transmission delay occurs, and the two converters B and E accumulate the delay. In the above example, one arrow is described as one data frame for the sake of simplicity, but this is not always necessary. For example, even if one arrow represents hundreds to tens of thousands of data frames, The operation is the same.

Next, referring to FIG. 6, how much the throughput is when the transfer of the confirmation frame is controlled (case of FIG. 5) and when the transfer control of the confirmation frame is not performed (case of FIG. 7). The improvement will be described. In FIG. 6, some assumptions are made to verify the effect of the method of the present invention. First, it is assumed that the arrangement intervals of the two N ports A and E are close, and there is no transmission delay of the ATM network C, and the N frames A and E also receive an acknowledgment frame ACK_N immediately after receiving N data frames. It is assumed that there is no internal processing delay as a return. In addition, it is assumed that the transfer delays of the confirmation frames ACK_N are also sufficiently small for the conversion devices B and D.

It is also assumed that full duplex communication is being performed between the two N ports A and E, and that the FC speed is faster than the ATM line speed. Under such conditions, assuming that the time length of one frame formed into cells in the ATM network C is T seconds, a series of N
The entire frame has a time length of T × N seconds. The occurrence time position of the acknowledgment frame ACK_N for this series of data frames is the first position preceding the N data frames transmitted in the reverse direction because full-duplex communication in which transmission and reception are performed independently; This is some point between the N + 1th position immediately after the transmission of the N data frames. Therefore, if these are averaged, the confirmation frame AC
K_N can be considered to occur N / 2th in each data frame.

Therefore, when the transfer of the confirmation frame shown in FIG. 7 is not performed, the confirmation frame ACK_N is kept waiting in a queue for N / 2 × T seconds on average. In contrast, in the example of FIG. 5, no waiting time occurs. Therefore, the time required from the start of the transmission of the first N data frames to the reception of the acknowledgment frame ACK_N and the transmission of the next N data frames is the sum of the above-described respective times. In the case of (2), N × T + (N / 2) × T = (3N / 2) × T [sec] (3), and in the case of FIG. 5, N × T [sec] (4).

Here, when the throughput (number of packets that can be transmitted per second) on the ATM line is expressed in terms of the number of frames, in the case of FIG. 7, N frames / {(3N / 2) × T} = 2 / 3T [frame / second] (5), and in the case of FIG. 5, N frame / N × T = 1 / T [frame / second] (6) Then, based on the case of FIG. 7, (1 / T) / (2 / 3T) = 1.5 times (7), and the throughput is improved 1.5 times on average.

Thus, at the opposite N port E,
The time interval between the transmission of a series of data frames and the transmission of the next series of data frames is reduced, and the transfer time of the entire data frame can be reduced.
The reason is that the conversion device E transfers the confirmation frame addressed to the opposite N port E without passing through the queue of data frames waiting for transmission. AT is N port A
Since the acknowledgment frame restored from the M cell can be received immediately, the time interval between the end of the transmission of a series of data frames and the transmission of the next series of data frames is narrowed, and the transfer time of the entire data frame can be shortened. .
The reason is that in the conversion device B, the confirmation frame arriving from the opposite N port E via the ATM network C is transmitted to the N port A.
This is because the data frame can be immediately transferred to the N port A without passing through the queue of the destination data frame.

Further, even a low-speed segmenter or reassembler can be applied to a high-speed ATM network. The reason is that the operation speed per circuit can be reduced by performing the parallel processing.
Further, the data frame can be transmitted while occupying almost the entire band of the ATM line, and the use efficiency of the ATM line can be improved. The reason is that some bands are always prepared for the confirmation frame and are not left empty, and as soon as the confirmation frame occurs,
This is for interrupting between data frames and transmitting the data in a short time.

[0041]

As described above, according to the present invention, N
The confirmation frame transmitted from the port to the opposing N port via the device is immediately converted to an ATM cell and transmitted to the ATM network prior to the data frame stored in the memory of the device and waiting to be transferred to the opposing N port. On the other hand, ATM
Since the confirmation frame in the cell input from the network is processed before the data frame stored in the memory and waiting for transfer, the frame is immediately transferred to the N port.
The waiting time of the confirmation frame at the N port and the opposite N port is reduced, and thus the transmission efficiency of the data frame can be improved. Further, the FC / ATM conversion unit and A
Since the N / N parallel processing of the data is performed in the TM / FC conversion unit, the present apparatus can cope with a high-speed ATM network with inexpensive and low-speed circuit components, and therefore, the apparatus can be constructed economically.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an FC / ATM network interconversion device to which the present invention is applied.

FIG. 2 is a block diagram showing another example of the conversion device.

FIG. 3 is a timing chart showing operation timings of an FC / ATM converter of the converter.

FIG. 4 is a timing chart showing operation timings of an ATM / FC converter of the converter.

FIG. 5 is a timing chart showing data transmission / reception timing during full-duplex communication of a system including the conversion device.

FIG. 6 is a timing chart for explaining a state of transmission efficiency in the conversion device.

FIG. 7 is a timing chart showing the data transmission / reception timing during the conventional full-duplex communication.

FIG. 8 is an explanatory diagram of an N port used in the present invention.

[Explanation of symbols]

1: FC / ATM converter, 2: ATM / FC converter, 1
1 ... FC frame receiver, 12, 27, 31, 42 ... switch, 13, 131 to 134, 25, 251-254
... Memory for data frame, 14, 26 ... Memory for confirmation frame, 151 to 154, 16 ... Segmentation unit, 18 ... ATM cell transmitter, 19 ... Confirmation frame detection / control circuit, 21 ... ATM cell receiver, 231 to 234
, 24: reassembly unit, 28: FC frame transmitter, 29: VCI detection / control circuit, 32: multiplexer, 41: demultiplexer, ACK, ACK_N: confirmation frame.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-251195 (JP, A) 1996 IEICE General Conference B-774 IEICE Technical Report IN97-1 1996 IEICE General Conference B -773 1996 IEICE General Conference B -775 1995 IEICE General Conference B -755 1995 IEICE General Conference B -754 GLOBECOM'94 P1801-1807 GLOBECOM'93 P1127-1133 ICC'94 P598-602 WESCON'94 P660-665 COMPUTER DESIGN (J UNE 1994) P59-60, 62, 64, 66 (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12/56 H04L 12/28 H04L 12/66 JICST file (JOIS)

Claims (2)

(57) [Claims] 1. An FC frame receiver disposed between an N port having an FC interface which is a fiber channel interface and an ATM network which is an asynchronous transfer mode network, for receiving an FC frame from the N port, and an FC frame. The first and second memories in which the output frames of the receiver are respectively distributed and accumulated via the first switch, and the FC frames of the first and second memories are input and the virtual frames of the unique values are input. AT with channel identifier
An FC / ATM converter comprising first and second segmenters for converting into M cells, and a multiplexer for multiplexing the converted ATM cells and transmitting the ATM cells to the ATM network, and receiving the ATM cells from the ATM network. AT to do
M cell receiver and AT output from ATM cell receiver
Demultiplexer for separating M cells and each separated A
A first and a second reassembly unit for inputting a TM cell and converting it to an FC frame, a third and a fourth memory for respectively storing FC frames from each of the reassembly units, and a second switch; And an FC frame transmitter for extracting each FC frame from the third and fourth memories via an N port and transmitting the frame to the N port.
A C / ATM network interconversion device for detecting a confirmation frame from each output frame of an FC frame receiver, controlling a first switch and a multiplexer according to the detection result, and The first selecting means for selecting one of a first path connecting the first segmentation unit and a second path connecting the second memory and the second segmentation unit to the F.
If the virtual channel identifier detected in the output cell of the ATM cell receiver indicates a confirmation frame, the demultiplexer and the second switch are controlled, and the first reassembly unit is provided. The second selection means for selecting one of a third path connecting the third memory and a fourth path connecting the second reassembly unit and the fourth memory is provided by the ATM / FC. A multiplexing / reproducing device in an FC / ATM network interconversion device provided in a conversion unit.
Separation method. 2. The method according to claim 1, wherein the number of output terminals of the first switch and the number of input terminals of the second switch are each N + 1 (N is an integer), and the multiplicity in the multiplexer and the demultiplexer is N
The third switch having N + 1 input terminals and N output terminals is divided into N + 1 segmentations by multiplexing and configuring the other of the first and second paths in N-parallel connection. A fourth path having N input terminals and N + 1 output terminals by connecting the other of the third and fourth paths in an N-parallel connection. In the FC / ATM network interconversion apparatus, wherein the switch is connected between N + 1 reassembly units and the demultiplexer.
Separation method.