JP2783008B2 - Frame synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an HDT transmitted in accordance with a 1125/60 high-definition television system studio digital signal standard (draft) specified by BTA-S002.
The present invention relates to a frame synchronizer for synchronizing the frame of a V digital signal.

[0002]

2. Description of the Related Art In recent years, development of HDTV equipment has been actively carried out in anticipation of the advent of the full-scale HDTV era. B
TA (Broadcasting Technology Development Council) uses 1125/60 high-definition television system as a standard for an interface between video devices having a digital video input or output, which is used for studio production among HDTV devices. Studio Digital Video Standard (HDTV)
Described as a digital standard. ) Is under discussion. In the HDTV digital standard, in order to clarify the timing relationship between a video signal and an analog synchronization waveform, a SAV (Start of Active Video) is placed at the beginning of each video data block.
At the end of each video data block, EAV (End of Active
Video). In each video device, SAV, an EAV detected from the sent come digital signal, di
Synchronizes the frame of the digital video signal . The fret here
Synchronized with the over arm, the frame synchronization in digital transmission
Means. The cycle of the transmission frame in this case is SAV
Alternatively, EAV is used as a frame synchronization pattern and SAV
Appears and coincides with the cycle in which the next SAV appears. Follow
The transmission frame period matches the horizontal line period of the video
doing.

In the case where signals are transmitted serially between devices, if a frame synchronization cannot be detected on the signal receiving side, a bit shift may have occurred in the serial / parallel converter in the preceding stage. There is. In this case, the bit shift signal must be fed back to the serial / parallel conversion unit in the frame synchronization unit. Hereinafter, a conventional frame synchronization detecting device for detecting a frame synchronization signal of the HDTV digital standard will be described with reference to the drawings.

FIG. 4 shows a conventional frame synchronizer and a serial / parallel converter, and FIGS. 5A and 5B are signal diagrams showing signals input to the frame synchronizer. In FIG. 4, a portion surrounded by a dotted line is a conventional frame synchronization device. 41 is an input terminal for inputting serial data, 42 is a serial / parallel converter for converting serial data into parallel data, 43 is a synchronization detection circuit, 44 is a bit shift generation circuit, and 45 is an output terminal for outputting a synchronization signal It is. The frame synchronizer configured as described above will be described below with reference to FIGS.

[0005] Now, the transmitted signal is represented by a Y signal, PB /
It is assumed that the two channels of the PR signal are 10-bit signals. First, the serial signal transmitted is serial /
The data is expanded into a 20-bit parallel signal by the parallel conversion unit 42. As shown in FIG. 5A, when the data can be developed like the original data, the synchronization detection circuit 43 detects the 20-bit all 1, 20-bit all 0, 20-bit all 0 SAV and EAV patterns, The synchronization signal is output from the synchronization signal output terminal 45 in accordance with the timing. The detected synchronization signal is output to the subsequent stage together with the data signal, and serves as a timing reference signal for signal processing of the video data block. Further, when a signal having a bit shift as shown in FIG. 5B is input, the synchronization detection unit cannot detect the synchronization. If the synchronization cannot be detected for one or more frames, a bit shift generation signal is transferred from the synchronization detection circuit 43 to the bit shift generation circuit 44, and the bit serial /
The bit shift signal is transferred to the parallel
A bit shift is performed.

If synchronization cannot be detected by one bit shift, a bit shift operation is performed one frame later.

[0007]

Now, a 20-bit signal
If you are dealing with are in some cases the deviation of up to 19 bits is generated. The pattern of SAV and EAV is one
Since a transmission frame, that is, only once per video line , is transmitted once when a bit shift occurs.
Beam, i.e. must wait for judgment of the synchronization detection or between 1 video line. Therefore for synchronization recovery is it takes up to 19 frames or more of the time. Also synchronized times
If the recovery midway data error had occurred in the detection pattern, look at the detection pattern can not detect the synchronization pattern
Miss you. If a bit shift occurs, it takes more than several transmission frame times to recover synchronization.

SUMMARY OF THE INVENTION In view of the above problems, the present invention performs synchronization detection for each channel, and reads the occurrence of a bit shift based on the synchronization timing of a plurality of one-channel synchronization signals and the presence or absence of the synchronization detection. It is an object of the present invention to provide a frame synchronization apparatus having a short synchronization recovery time by calculating the number of bit shifts by reading a shift pattern and generating bit shifts within the number of shifts within one frame. This
The channel here means an HDTV digital signal video signal.
In the case of the Y, P _B / P _R system, the Y signal and P _B / P _R
Refers to each signal when divided into signals. Also, RG
In the case of B system, various color signals of G signal, B signal, R signal
It refers to each color signal when divided into numbers.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a frame synchronization apparatus according to the present invention comprises a 1125/60 high-definition
HDTV transmitted according to the fine television system
Frame synchronizer for synchronizing digital signal frames
Input from the serial / parallel converter.
Input 10 bit signal of HDTV digital signal
To detect the SAV and EAV patterns, and
Output 1-channel synchronization detection signal according to the timing
And a plurality of one-channel frame synchronization detection circuits.
Receive the output of the one-channel frame synchronization detection circuit.
Bit shift detection circuit to detect
Coming HDTV digital signal and said bit shift detection circuit
Shift to calculate the bit shift value in response to the output result of
A value calculation circuit and an output of the bit shift value calculation circuit.
In the serial / parallel conversion device,
Generates a bit shift signal that causes
/ Bit shift generating circuit for input to parallel / parallel converter
It is provided with.

[0010]

According to the present invention, a bit shift is determined based on whether or not synchronization can be achieved for each channel by the above-described configuration, and whether or not the synchronization timing is the same. By calculating the value, the bit shift is corrected in a short time within one frame, and the frame synchronization is detected.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A frame synchronizing apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a frame synchronizer and a serial / parallel converter according to an embodiment of the present invention. FIG. 2 shows an input signal input to the one-channel synchronization detection circuit. FIG. 3 shows a serial signal input to the serial / parallel converter. In FIG. 1, a portion surrounded by a dotted line is a frame synchronization detection circuit.

In FIG. 1, reference numeral 1 denotes an input terminal for inputting serial data, 2 denotes a serial / parallel converter,
Is a one-channel synchronization detection circuit, 5 is a bit shift detection circuit,
Reference numerals 6 and 7 denote bit shift value calculation circuits, 8 denotes a bit shift generation circuit, 9 denotes a frame synchronization detection circuit, and 10 denotes an output terminal for outputting a frame synchronization signal. In FIG. 2, (a) is an input signal to the one-channel synchronization detection circuit in which no bit shift occurs, (b) is an input signal to the one-channel synchronization detection circuit in which a two-bit shift occurs, ( c) is 1
An input signal to the 1-channel synchronization detection circuit causing a 4-bit bit shift, and (d) is an input signal to the 1-channel synchronization detection circuit when a 10-bit bit shift occurs.

The serial data as shown in FIG. 5 input from the input terminal 1 is converted into parallel data by the serial / parallel converter 2. When the serial signal input as shown in FIG. 3 is converted into a parallel signal by the serial / parallel converter 2 at a correct timing, the data becomes parallel data without bit shift as shown in FIG.

In FIG. 2A, the upper 10 bits are input to the one-channel synchronization detection circuit 3 and the lower 10 bits are input to the one-channel synchronization detection circuit 4. Each one-channel synchronization detection circuit has 10
A pattern of all 1, 0, and 0 bits is detected, and a one-channel synchronization detection signal is output in accordance with the detected timing. 1-channel synchronization detection circuits 3 and 4
Since but outputs one channel synchronous detection signals simultaneously, the bit shift detector circuit 5 does not detect the bit shift. The synchronization detection circuit 9 detects the synchronization and outputs a frame synchronization signal from the output terminal 10.

When a signal having a bit shift as shown in FIG. 2B is input to the one-channel synchronization detection circuits 3 and 4, the one-channel synchronization detection is detected only by the one-channel synchronization detection circuit 4. Is done. Since only one of the one-channel synchronization detection signals is input to the bit shift detecting circuit 5, the bit shift is detected, and the bit shift value calculating circuit 6
To output a bit shift value calculation signal. The bit shift value calculation circuit 6 calculates a 2-bit shift from the bit shift pattern of the portion B in FIG. 2B and outputs a signal indicating that a 2-bit shift has occurred to the bit shift generation circuit 8. As a result, the bit shift generating circuit 8 outputs the bit shift signal twice within one frame, and in the serial / parallel converter 2 receiving the bit shift signal, the serial / parallel conversion timing is changed and the bit shift signal is output. The shift is corrected.

Here, if the bit shift pattern of B in FIG. 2 (b) is a 2-bit shift pattern, 2 bits are 1 from LSB and all the remaining bits are 0, and if the shift is 3 bits, 3 bits from LSB. Is 1 and the remaining bits are 0. As described above, there is one bit from the LSB corresponding to the number of shifts, and the number of bit shifts can be calculated from the bit shift pattern. The timing at which the bit shift pattern appears is
At timing 1 channel synchronous detection circuit 4 for detecting a channel synchronization, which is one before the timing T1 in FIG. 2 (b).

When a signal having a bit shift as shown in FIG. 2C is input to the one-channel synchronization detection circuits 3 and 4, the one-channel synchronization detection is detected only by the one-channel synchronization detection circuit 3. You. Since only one of the one-channel synchronization detection signals is input to the bit shift detection circuit 5, the bit shift is detected, and the bit shift value calculation circuit 6
To output a bit shift value calculation signal. The bit shift value calculating circuit 6 calculates a 14-bit shift from the bit shift pattern of the portion C in FIG. 2C and outputs a signal indicating that a 14-bit shift has occurred to the bit shift generating circuit 8 . As a result, the bit shift generation circuit 8 outputs the bit shift signal 14 times within one frame, and the bit serial / parallel converter 2 receiving the bit shift signal changes the timing of the bit serial / parallel conversion. Bit shift correction is performed. The bit shift pattern is the timing at which the one-channel synchronization detection circuit 3 detects synchronization, T2 in FIG.
Always appear two data before the timing. If the bit shift pattern is 1 bit from the LSB and 4 bits and the remaining bits are 0, the shift number is 14 bits. If the 1 from the LSB is 5 bits and the remaining bits are 0, the shift number is 15 bits. The number of bit shifts is determined by adding 10 to the number of 1 bits of the shift pattern. From this, the number of bit shifts can be calculated from the bit shift pattern.

When a signal having a bit shift as shown in FIG. 2D is input to the one-channel synchronization detection circuits 3 and 4, one-channel synchronization is detected by both the one-channel synchronization detection circuits 3 and 4. . However, the detection timing is 1
The channel synchronization detection circuit 4 is faster. The bit shift detecting circuit 5 outputs a 10-bit shift signal to the bit shift generating circuit 8 in response to the timings of the two input one-channel detection signals. The bit shift generating circuit 8 receives a 10-bit shift signal and
A bit shift signal is generated ten times within a short time within a frame, and the serial / parallel converter 2 shifts the serial / parallel timing. As described above, S
In AV and EAV, the first three words are expressed in hexadecimal.
There are 3FF, 000,000 data words. BTA S
-002 standard uses 3FF data words
Is only in SAV and EAV. Because of this
3FF, 000,000 data words in data word
Does not occur. Bit shift detection is bit shift
1 channel synchronization with pattern and serially continuous
It is detected only when both signals are input at the same time. This
Signal that satisfies the condition
0 consecutive patterns are included in at least 30 bits in total
You. Therefore, even if a bit shift occurs,
At least one word of 3FF or 000 pattern
This pattern occurs if it is not included in the 0 bit.
do not do. Therefore, make sure that no reception error has occurred.
Bit shift is detected erroneously and the bit shift signal is
It does not occur. Although the probability is extremely low,
Communication error, etc.
The following EAV, SA
No error occurs at V and the bit shift pattern is correct.
If it is detected incorrectly, the bit shift is corrected immediately.
You. Each detection pattern surrounded by a broken line in FIG. 2 includes a pattern of all 0s continuous for 30 bits. However,
As described above, the 30-bit all-0 pattern is SA
Since it does not occur in portions other than V and EAV, it can be limited to SAV and EAV depending on each detection pattern. Thereby, it can be limited that the bit shift value calculated from each detection pattern in FIG. 2 is correct.
The signal input to the serial / parallel converter in FIG.
Is the same sampling as the serial data in Figure 3.
The point is a signal multiplexed in order of Y, PB / PR.
However, signals in the order of PB / PR, Y as shown in FIG.
Let's say it's coming. This signal is
FIG. 7 shows a serial-to-parallel conversion in the
become that way. The signal in FIG. 7 is a series of the signals in FIG. 2 and FIG.
Y signal and PB
The / PR signal has been switched. However, the Y signal and PB /
What is the difference in the video timing reference code between PR signals?
Therefore, the SAV and EAV that have become parallel signals in FIG.
The pattern is input in the order of Y, PB / PR in FIG.
Of SAV and EAV after serial-to-parallel conversion
Same as turn. Therefore, the frame synchronizer of FIG.
Is the PB / PR signal and Y signal like the serial data in FIG.
Even if they are entered in the order of issue,
The same operation as when the serial data of No. 3 is input
Corrects bit shifts and establishes frame synchronization
You.

[0019]

As described above, the present invention detects the frame synchronization for each channel even if a bit shift occurs in the digital parallel data input according to the HDTV digital standard, and The bit shift value is calculated from the timing and presence / absence of the channel frame synchronization detection signal and the bit shift pattern, and the bit shift is corrected in a short time within one frame, so that frame synchronization recovery can be realized in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frame synchronizer and a serial / parallel converter according to an embodiment of the present invention.

FIG. 2 (a) is a state diagram when a bit shift of an input signal input to a 1-channel synchronization detection circuit in a frame synchronization apparatus according to an embodiment of the present invention is not caused; (C) State diagram when a 14-bit bit shift occurs (d) State diagram when a 10-bit bit shift occurs

FIG. 3 is a signal state diagram of serial data input to a serial / parallel converter at a preceding stage of the frame synchronizer according to one embodiment of the present invention;

FIG. 4 is a block diagram of a conventional frame synchronizer and a serial / parallel converter.

FIG. 5 (a) is a signal state diagram when a bit shift of a signal input to a synchronization detection circuit in a conventional frame synchronizer does not occur, and (b) a signal state diagram when a bit shift occurs.

FIG. 6 is a signal state diagram of serial data input to a serial-to-parallel converter at a preceding stage of the frame synchronizer according to one embodiment of the present invention;

FIG. 7A is a state diagram in a case where a bit shift of an input signal input to a one-channel synchronization detection circuit in a frame synchronization apparatus according to an embodiment of the present invention has not occurred; (C) State diagram when a 14-bit bit shift occurs (d) State diagram when a 10-bit bit shift occurs

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 serial / parallel converter 3 1-channel synchronization detection circuit 4 1-channel synchronization detection circuit 5 bit shift detection circuit 6 bit shift value calculation circuit 7 bit shift value calculation circuit 8 bit shift generation circuit 9 frame synchronization detection circuit 10 output Terminal

Continuation of the front page (72) Inventor Kiyoshi Uchimura 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-62-27241 (JP, A) JP-A-2-53345 (JP) JP-A-2-257730 (JP, A) JP-A-3-1922843 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N ^5/ 04-5/12 H04N 7/00 H04N 7/24-7/68 H04L 7/08

Claims (1)

(57) [Claims] 1. A 1125/60 A frame synchronizing device for frame synchronization of the HDTV digital signals transmitted in accordance with high definition television system, the serial
/ HDTV digital input from parallel converter
SAV, EAV by inputting 10-bit signal out of signals
Pattern is detected, and in accordance with the detected timing.
One-channel frame that outputs one-channel synchronization detection signal
A plurality of arm synchronization detection circuit, the output result of the bit shift detecting circuit for detecting a bit shift in response to an output of said plurality of single-channel frame synchronization detection circuit, the HDTV digital signal transmitted the bit shift detector circuit a bit shift value calculating circuit for calculating a bit shift value in response to, in response to the output of the bit shift value calculating circuit, the serial /
A bit shift generator in a parallel converter
Serial-to-parallel converter that generates a bit shift signal
And a bit shift generation circuit for inputting the data to the frame synchronization apparatus.