JP2780553B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semi-custom semiconductor integrated circuit device having a fixed base.

[0002]

2. Description of the Related Art The fixed base type is a MOS transistor,
Bipolar transistors, resistors, capacitors, etc. are advanced to the diffusion layer formation in advance, and these are prepared. Wiring is performed according to the circuit configuration and commercialized. This is excellent in terms of development period and development cost. is there. Next, a conventional semiconductor integrated circuit device of this type will be described with reference to the drawings in the case of an analog circuit.

In this semiconductor integrated circuit device, as shown in FIG. 4A, a first circuit element forming area EA in which a plurality of resistance elements RE are sequentially formed in a certain direction on a substrate 11 is formed.
11, a plurality of PNP transistor elements PTE provided close to and parallel to the first circuit element formation region EA11.
Are formed sequentially in a certain direction, and a plurality of NPN transistor elements N are provided adjacent to and parallel to the second circuit element area EA12.
A third circuit element formation area EA13 in which TEs are sequentially arranged in a fixed direction; and a third circuit element formation area EA1
And a fourth circuit element formation region EA14 in which a plurality of resistance elements RE provided in parallel with and adjacent to each other are sequentially formed in a predetermined direction, and an underlayer circuit is formed on the underlayer circuit. (Not shown), the resistance elements R of the circuit element formation regions EA11 to EA14 are formed on the insulating film.
E, the wiring WL connecting the electrodes of the PNP transistor element PTE and the electrode of the NPN transistor element NTE and the power wirings PL1 and PL2 for supplying power are formed. FIG. 4B shows the above-described wiring WL, power supply wiring PL1,
It is a circuit diagram of an amplifier circuit obtained by forming PL2.

An important point in the layout of an analog circuit is the design of wiring and the arrangement of circuit elements.

That is, in the design of the wiring, the wiring impedance, the aluminum wiring migration, etc. are taken into consideration, and the wiring width for the wiring is designed. When the circuit element arrangement is used in pairs, it is necessary that the difference between the characteristics is small (hereinafter referred to as “pairing”).

Next, the importance of the pairing and the circuit element arrangement will be described.

Normally, when a semiconductor chip is formed from a wafer, the characteristics of the transistor and the absolute value of the resistance vary depending on the semiconductor chip and the position on the wafer. The first factor is the effect of etching during diffusion, and the second is the effect on assembly that occurs when semiconductor chips are cut out from a wafer, bonded and molded.

More specifically, the influence of the etching is caused by the non-uniformity of the thickness of the oxide film and the resist depending on the place at the time of patterning.
This is because the width of the resistance element differs. This indicates that the base-emitter voltage Vbe and the resistance value of the transistor differ depending on the location, and this limits the arrangement of circuit elements requiring pairing.

[0009] Next, the influence on the assembling is related to the structure of the silicon crystal lattice. However, the influence of the mechanical stress of physical properties due to resin distortion or the like at the time of cutting a semiconductor chip from a wafer, bonding, or molding is not affected by the position on the chip. This is due to the fact that they differ greatly.

In the arrangement of the base circuit of the semiconductor integrated circuit device shown in FIG. 4, the same circuit elements are arranged in the same stage. If these circuit elements are laid out at random, the elements that require pairing will be greatly reduced, which may affect the characteristics.

Therefore, in the amplifier circuit shown in FIG. 4 (B), a pair of circuit elements is specifically designated adjacently so as to reduce the offset voltage. That is, even if the absolute values are shifted, the relative ratio of the values of the circuit elements forming a pair is canceled.

As described above, in the conventional circuit configuration of the prior art, the larger the size of the underlying circuit, the more attention is required and manual work is required.

As a countermeasure, if one circuit element formation region is configured to include a minimum number of circuit elements necessary for forming one circuit, the distance will be reduced, but the analog circuit is still required. At present, about 100 elements are included in one circuit element formation region due to the above configuration.

FIGS. 5A and 5B are a characteristic diagram and a layout diagram of the pairing characteristics of the transistors for explaining the above-described pairing characteristics and circuit element arrangement in an easy-to-understand manner.

[0015] Two NPN transistors NTE1, NT
The interval of E2 is d, and the base of these NPN transistors is
Assuming that the difference between the emitter-to-emitter voltages Vbe is Δbe, Δbe is proportional to the interval d. If ΔVbe is required to be 2 mV or less, two NPN transistors NTE1 and NTE
TE2 is such that the interval ΔVbe is 2 mV (interval d
s) It is limited to the following range.

[0016]

In the above-mentioned conventional semiconductor integrated circuit device, a plurality of circuit element forming areas EA11 to EA in which one kind of circuit elements are sequentially formed in a certain direction are formed.
14 are provided close to and parallel to each other,
Since the lengths of these circuit element formation regions EA11 to EA14 are long, predetermined characteristics for forming a circuit by randomly selecting two circuit elements requiring pairing may be obtained. Since it was difficult, manual work was required, and there was a problem that the production period was lengthened.

An object of the present invention is to provide a semiconductor integrated circuit device in which even circuit elements that require pairing can be selected at random, thereby facilitating automation and shortening the manufacturing period. It is in.

[0018]

According to the present invention, there is provided a semiconductor integrated circuit device comprising: a first circuit element formation region in which a plurality of active circuit elements are formed within a circle having a first diameter set in advance on a substrate; A second circuit element forming area in which a plurality of passive circuit elements are formed within a circle having a second diameter set in advance; and a circuit element forming area on the first and second circuit element forming areas. And wiring for forming a circuit that performs a predetermined function by connecting electrodes of the active element and the passive element therein.

Further, a plurality of active circuit elements and passive circuit elements are formed in the circuit element forming region.

[0020]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a layout view of a semiconductor chip showing a first embodiment of the present invention.

In this embodiment, a first circuit element forming area EA1 in which a plurality of resistance elements RE are formed within a predetermined first diameter d1 circle on a substrate 11, and a second predetermined circuit area EA1 are formed. A plurality of PNP transistor elements PTE are formed in a circle having a diameter d2 of a second circuit element area EA2 provided in the vicinity of the first circuit element formation area EA1, and a predetermined third diameter d3 is formed. Second circuit element formation region EA in which a plurality of NPN transistor elements NTE are formed in a circle
2 and a third circuit element formation region EA3
And a base circuit including a third circuit element formation region EA4 in which a plurality of resistance elements RE are formed within a circle having a predetermined fourth diameter, and an insulating film (not shown) is formed on the base circuit. ), The wiring WL connecting the resistance elements RE, the PNP transistor element PTE, and the NPN transistor element NTE of the circuit element forming regions EA1 to EA4 and the power supply lines PL1 and PL for supplying power are formed on the insulating film.
2 is formed. The diameters d1 to d4
Are set so as to satisfy the pairing property even if the circuit elements in the respective circuit element formation areas EA1 to EA4 are randomly selected and used as a pair.

Now, a 10 μm × 20 μm circuit element 150
When the pieces are arranged by the method of the conventional example, even if they are arranged in three steps of 50 pieces, the size is 60 μm × 500 μm. On the other hand, in the present invention, it can be accommodated in a circle having a diameter of 196 μm. If the maximum distance between two circuit elements requiring pairing is, for example, 200 μm, all 150 elements can be selected at random in the present invention, but in the conventional example, it is within about 1/3 of the whole. Only the one that satisfies the pairing property can be obtained.

FIG. 2 is a layout diagram of a circuit element forming region according to a second embodiment of the present invention.

In the circuit element forming area EA5 of this embodiment, a plurality of resistance elements RE and PNP transistor elements PT
An E, NPN transistor element NTE is formed.
Therefore, a circuit having a predetermined function can be formed in one circuit element formation region EA5, and the length of the wiring can be shortened. Therefore, there is an advantage that a circuit having excellent high-frequency characteristics can be formed. .

FIG. 3 is a layout diagram of a semiconductor chip according to a third embodiment of the present invention.

In the first embodiment, the circuit element forming regions EA1 to EA4 are base circuits arranged in a line in close proximity to each other, but in this embodiment, the circuit element forming regions EA1 to EA4 EA6 is a base circuit having an arbitrary arrangement. This arrangement is performed by estimating a circuit to be formed on the underlying circuit, taking into account the use efficiency of circuit elements, the routing of wiring, and the like.

[0028]

As described above, according to the present invention, a base circuit including a circuit element forming region in which a plurality of circuit elements are formed in a circle having a predetermined diameter is formed, and wiring is formed on the base circuit. By forming the circuit to form a circuit having a predetermined function, the pairing property is satisfied even when two circuit elements in one circuit element formation region are randomly selected and used as a pair. Therefore, there is an effect that automation becomes easy and a production period can be shortened.

[Brief description of the drawings]

FIG. 1 is a layout view of a semiconductor chip showing a first embodiment of the present invention.

FIG. 2 is a layout diagram of a circuit element forming region according to a second embodiment of the present invention.

FIG. 3 is a layout view of a semiconductor chip according to a third embodiment of the present invention.

FIG. 4 is a layout diagram of a semiconductor chip showing an example of a conventional semiconductor integrated circuit device, and a circuit diagram showing a circuit formed on the semiconductor chip.

5A and 5B are a characteristic diagram and a layout diagram of a pair characteristic of a transistor requiring a pair characteristic of the semiconductor integrated circuit device shown in FIG. 4;

[Explanation of symbols]

1, 1a, 1x Semiconductor chip 11 substrate EA1 to EA5, EA11 to EA14 Circuit element forming area MTE MOS transistor element NTE NPN transistor element PTE PNP transistor element PL1, PL2 Power supply wiring RE Resistance element WL Wiring

Claims (2)

(57) [Claims] 1. A first circuit element forming region in which a plurality of active circuit elements are formed within a circle having a predetermined first diameter on a substrate, and a circle having a second diameter having a predetermined diameter. A second circuit element forming region in which a plurality of passive circuit elements are formed,
A semiconductor having a wiring on the first and second circuit element formation regions for connecting electrodes of an active element and a passive element in these circuit element formation areas to form a circuit having a predetermined function; Integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein a plurality of active circuit elements and passive circuit elements are formed in the circuit element formation region.