JP2778396B2 - Spread spectrum signal receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for a mobile communication system using a code division multiple access system.

[0002]

2. Description of the Related Art Along with recent advances in electronic communication technology, mobile communications such as automobile telephones and mobile telephones have become widespread. In the field of mobile communication, digital communication is being studied, and various communication systems are being studied.
One such system is CDMA (Code Division Multiple Access).
There is a system that can share time and frequency, has excellent confidentiality, and has strong resistance to frequency-selective fading.

In the CDMA system (particularly, a CDMA system using DS / SS, which is a direct spread spectrum spread system), in addition to a modulator / demodulator for performing ordinary wireless communication, a spread spectrum is performed using a PN code or the like. Means and despreading means for performing despreading for returning the spread spectrum signal to the original band are required.

Further, for example, in data communication from a mobile station to a cell site (base station), in addition to a spread code such as a PN code, an orthogonal signal system such as a Walsh function corresponding to a plurality of transmission data is transmitted. By doing so, efficient information transmission may be performed. In such a case, at the cell site, when demodulating data, in addition to despreading the PN code, a correlation value is obtained for each of the Walsh functions corresponding to all transmission candidate symbols, and a Walsh function that gives the maximum correlation value is obtained from the correlation values. An operation for demodulating the transmission data by the determination is required.

FIG. 21 shows, for example, US Pat.
FIG. 22 shows a conventional configuration example of the above-mentioned spread spectrum signal transmitter / receiver shown in FIG. 9, and FIG. 22 shows the analog receiver and digital data receiver shown in FIG. 2 shows a configuration example. Hereinafter, the receiver of the conventional system will be described with reference to the drawings.

FIG. 21 is a block diagram showing an embodiment of the cell site equipment. At the cell site, two receiver systems, each with a separate antenna and analog receiver, are used for space diversity reception. In each receiver system, the signal is processed independently until it reaches the diversity combining process. Elements surrounded by broken lines correspond to elements corresponding to communication between the cell site and one mobile unit. The output of the analog receiver is also provided to other elements for communicating with other mobile units. In FIG. 21, a first receiver system includes an antenna 60, an analog receiver 64, and a searcher receiver 6.
8. It is composed of a digital data receiver 69. The first receiver system also has an optional digital data receiver 70. The second receiver system includes an antenna 61, an analog receiver 65, a searcher receiver 71, and a digital data receiver 72.

[0007] The cell site also has a cell site control processor 74. Control processor 74 couples data receivers 69, 70, 72 with searcher receivers 68, 71. The control processor 74 performs signal processing, timing signal generation,
It has functions such as handoff control, diversity, interface with the system control processor, and allocation of Walsh series.

[0008] The two receiver systems are connected to data receivers 69, 70, 72 and input to a diversity combiner & decoder circuit 73. Digital link 7
5 is also connected to the control processor 74, the cell site transmission modulator 77, and the MTSO digital switch. The digital link 75 is controlled by a modulator 77 and a circuit 73 under the control of a control processor 74.
Used for communication with the MTSO.

The mobile unit transmission signal is a direct spread spectrum spread signal, which is spread modulated by multiplying a transmission symbol by a PN sequence at a predetermined clock speed, for example, 1.2288 MHz. This clock speed is determined to be an integral multiple of the baseband data speed.

[0010] The signal received by the antenna 60 is supplied to an analog receiver 64. Details of the analog receiver are shown in FIG.

[0011] The signal received by the antenna 60 is supplied to a down converter 541. Down converter 5
41 includes an RF amplifier 542 and a mixer 543. The received signal is provided as an input to an RF amplifier, where the received signal is amplified and then mixed
43. The output of the frequency synthesizer 544 is also supplied to the mixer 543 as an input. The amplified RF signal is mixed with the output signal of the frequency synthesizer 544 by the mixer
Converted to frequency.

The IF signal output from the mixer is input to a band pass filter (BPF) 545. The band pass filter 545 is configured by, for example, a SAW filter or the like, and has a pass band of 1.25 MHz. The signal band-limited by the band-pass filter 545 is input to an IF amplifier 546, where it is amplified. The amplified IF signal is supplied to an analog / digital (A / D) converter 5
The signal is converted to a digital signal at 9.8304 MHz, that is, at a clock rate eight times the chip clock. The A / D converter 547 is an analog receiver 6
Although shown as part of FIG. 4, it can also be considered as part of a data receiver or a searcher receiver. A / D
The digitized IF signal output from the converter is supplied to a data receiver 69, an optional receiver 70, and a searcher receiver 68. Hereinafter, the output from the analog receiver 64 and the I (in-phase axis) and Q (quadrature axis) channel signals will be described. Although the A / D converter 547 is shown as a single device in FIG.
It is assumed that the I and Q channel IF signals are supplied before the conversion and digitized by the two separate A / D converters, and thereafter, the two I and Q channel signals are handled. Frequency conversion (down conversion) to RF-IF-baseband and A / D conversion of I and Q channel signals are techniques well known to those skilled in the art.

A searcher receiver 68 is provided at the cell site for receiving additional digital data receiver 69 and, when used, so that digital data receiver 70 can track and process the strongest time domain signals. Scan the time domain for the signal. Scan results provided by searcher receiver 68
This causes the cell site control processor 74 to
Select the desired reception signal for the digital receivers 69 and 70
Control signal to process.

This processing at the cell site data receiver and the searcher receiver has some differences from the signal processing performed by similar elements at the mobile unit. In the inbound, that is, reverse (mobile-cell site) link, since the mobile unit does not transmit a pilot signal, the reference signal of synchronous detection cannot be used at the cell site. Variable demodulation arrangement asynchronous with 64 bi-orthogonal signal is used in the reverse link.

In the hexadecimal quadrature signal process, the transmitted symbols of the mobile unit are encoded into one of ²⁶ , ie, 64 different binary sequences. That is , one transmission symbol is constituted by a binary sequence of length 64 (each sequence is referred to as a chip), and the total number of orthogonal symbols is 64 (each symbol is 6-bit information). Therefore, the decimal representation of the 6-bit information is called a symbol number.) The set of selected binary sequences is known as a Walsh function. A fast Hadamard transform (FHT) is often used as an optimal receiver configuration for solving this Walsh function M-ary signal code.

Further description will be made with reference to FIG. Searcher receiver 68 and digital data receivers 69 and 7
To 0, the output signal of the analog receiver 64 is input.
In order to decode a spread spectrum signal transmitted to a particular cell site receiver via a communicating mobile unit, an appropriate PN sequence must be generated and supplied.

The details of the generation of the mobile unit signal will be described below. As shown in FIG. 22, the digital data receiver 69 includes a PN generator 308 that generates two different short code PN sequences having the same sequence length,
312. These two PN sequences are common to all cell site receivers and all mobile units as the outer code of the modulation configuration. A PN generator 308,
312 supplies the PN _I and PN _Q sequences as output sequences, respectively. The PN _I and PN _Q sequences are I and Q, respectively.
It is referred to as a channel PN sequence.

The two PN sequences PN _I and PN _Q are different 1
It is generated by a fifth-order polynomial and has a normal sequence length of 3276.
7, a sequence with a sequence length of 32768 is generated. Therefore, for example, there is a rule that 14 continuous zeros occur once in one cycle of the 15th-order longest linear sequence (M sequence).
By adding one zero after the 14 consecutive zeros, a sequence with a sequence length of 32768 is obtained. In other words, one state of the PN generator is repeated when the sequence is generated. In this way, the modified sequence includes one of 15 consecutive 1s and one of 15 consecutive 0s.

Digital data receiver 69 of one embodiment
Includes long code generator 310 for generating a PN _U sequence corresponding to another PN sequence generated by the mobile unit on the reverse link also. PN generator 3
10 generates a very long sequence of order 42, time-shifted according to additional factors such as a user ID to identify each user, and is realized, for example, by a maximum length linear sequence generator. Thus, cell sites are spread modulated long code PN _U sequence and the short code PN _I, in both PN _Q. Alternatively, a non-linear encryption generator, such as an encryption using the data encryption standard, may be used in place of the PN generator 310 to encrypt the 64-symbol representation with a key characterizing the user. Is also good.

The PN _U sequence of PN generator 310 output is the exclusive OR gates 314, 316, PN _I, sequence and each exclusive OR of the PN _Q is taken, sequence PN _I ',
PN _Q 'is output.

QPSK correlator 650 has the sequence PN
_I ′, PN _Q ′ and both I and Q channel signals output from the analog receiver 64 are input. The outputs of the correlated I and Q channel correlators 550 are supplied to accumulators 1067 and 1068, respectively, and the data is accumulated over a 4-chip length (ie, the transmission symbols are spread modulated with a 256-chip PN code). ing). The output of accumulators 1067 and 1068 is a fast Hadamard transform (FHT) processor 342 (344).
Supplied to The FHT processor 342 generates correlation values for 64 Walsh functions corresponding to 6 bits of data. The 64 correlation values are multiplied by a weight function generated by the control processor 74. The weight function is associated with the strength of the demodulated signal. The weighted data at the output of the FHT 342 is supplied to a diversity combiner & decoder circuit 73 (FIG. 21) for further processing.

The second receiver system performs the same signal processing on the received signal as in the first receiver system shown in FIGS. Digital data receiver 69,
The 64 correlation values weighted from 72 are supplied to the diversity combiner & decoder circuit 73. Circuit 7
Reference numeral 3 denotes an adder for adding 64 weighted correlation values from the digital data receiver 69 and the digital data receiver 72 for each same symbol. The 64 resulting correlation values are compared with each other to determine the largest correlation value. The magnitude of the comparison result, together with the symbol number giving the maximum value, is used to determine the weight of the decoder used in the Viterbi algorithm decoder mounted in the circuit 73 and the transmission data.

The Viterbi decoder included in the circuit 73 has a capability of decoding data encoded by the mobile unit at a constraint length K = 9 and a code rate r = 1/3. A Viterbi decoder is used to determine the most likely bit sequence. Normally, signal quality estimation is obtained periodically every 1.25 msec, and transmitted as a mobile unit power adjustment command together with data to the mobile unit. Detailed information on generating this quality estimate can be found in US
No. 5,056,109 . This quality estimate is the average SN ratio over 1.25 msec.

Generally, the data reception timing is unknown, and it is necessary to operate the FHT at a plurality of timings, estimate the timing, and track the timing. The searcher receiver is a receiver for performing initial timing estimation (capture). Acquisition is performed before communication, and even during communication, when the level relationship of the received wave is reversed due to a large change in the line state such as frequency selective fading, the higher level received wave is demodulated. There are two cases. In the latter case, it is necessary to always monitor (scan) the level of the received wave at different timings. On the other hand, timing control (tracking) needs to be performed for each digital data receiver in order to track data timing associated with relatively small fluctuations in the line state after capturing.

Although not shown in the figure, according to US Pat. No. 5,103,459, each digital data receiver tracks the timing of a received signal received by each digital data receiver. This is due to the slightly earlier reference P
This is achieved by well-known techniques for correlating with N and a slightly late timing reference PN. When the timing error is zero, the difference between these two correlation values is zero on average. Conversely, if there is a timing error, the error will be indicated by the magnitude and polarity of the difference between the two correlation values, and the timing of the digital data receiver will be adjusted accordingly.

A conventional spread spectrum signal communication apparatus is:
The transmission symbol number corresponding to the transmission data must be determined from all the transmission candidate symbols (Walsh functions). For this purpose, FHT is used as a means for correlating with the Walsh function. However, the United States
In Japanese Patent No. 5,103,459, a transmission symbol is multiplied by a signal at the same timing as a PN sequence. Also, since one chip of the Walsh function corresponds to four chips of the PN code, 256 chips of the PN code correspond to one transmission symbol. That is, even if the same Walsh function is repeatedly transmitted, 128 (= 32768/2)
56) PN codes are sequentially used. Therefore, the simple use of the FHT can obtain only the correlation value of the Walsh function at one data timing. Therefore, in order to configure a searcher receiver, a plurality of FHTs that operate with shifted timings are required, and the circuit scale is increased. Furthermore, if the acquisition of the timing takes too long, or if the monitoring function of the searcher receiver cannot cope with fluctuations in the state of the communication line, the incoming wave received by the current digital data receiver is lost due to fading or the like. Even if there is another receivable arriving wave, the spread spectrum signal may not be able to be received.

[0027]

Since the conventional spread spectrum signal receiver is constructed as described above, there is a problem that the circuit scale becomes large. In addition, multiple FHs
Of the correlation values obtained by T, only meaningful correlation values corresponding to transmission symbols are used, and other correlation values become noise when the transmission symbols are orthogonal functions. There is also a problem that averaging processing such as cyclic addition is necessary to remove the influence of noise, and a large processing time is required to sufficiently remove the influence of noise. On the other hand, if the processing time was shortened, sufficient noise could not be removed. That is, an error in the capture timing may be increased due to the influence of noise, or a capture timing may be provided such that good data demodulation cannot be performed.
There was a problem that the efficiency was high .

Also, in the timing tracking performed by the digital data receiver, only a significant correlation value corresponding to a transmission symbol is necessary, and other correlation values become noise. The averaging process is performed similarly to remove the influence of noise, and a large processing time is required to remove the influence of noise. That is, there is a problem that it is difficult to track the timing fluctuation due to the fluctuation of the communication line state, the timing is completely shifted, and the data cannot be demodulated. Alternatively, when shortening the processing time, can not sufficiently denoising, timing error
And the data demodulation characteristics deteriorate .

Furthermore, diversity reception is performed in order to cope with multipath fading. However, if the signal timing acquisition and tracking characteristics are poor, a sufficient diversity effect cannot be obtained and good reception characteristics cannot be obtained. There were challenges.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a spread spectrum signal receiver having improved acquisition characteristics, timing tracking characteristics, and data reception characteristics in a searcher receiver. I do.

[0031]

Means for Solving the Problems A spectrum according to the present invention
The receiver of the spread-spectrum signal
A plurality of correlation processors for multiplying and adding a spreading code, and
From the input or output side of multiple correlation processors
The input timing of the correlator or the above multiple
The timing at which the output of the
Output of multiple correlators at different timings
Output at different timings
Gate for sequentially selecting and outputting the output group of correlator output
Circuit and correlation processing sequentially output from these gate circuits
Solves Walsh function of detector output and outputs as correlation value intensity
Having a search processing unit, and a high speed converter that
Searcher receiver. The invention of claim 2
Is provided with the search processing means of claim 1 and the determination result.
Until the output of the search processing means is delayed
Path and the decision feedback signal from outside the searcher receiver.
Of the specific Walsh function from the delay circuit output
Selector for selecting the correlation value intensity and select with this selector
Having a, a cyclic adder for cyclic addition the correlation value intensities
Searcher receiver.

Further, according to the invention of claim 3, the transmission symbol is determined.
Transmission symbol determination means for generating a determination feedback signal
And a synchronously detected complex reception signal and a predetermined positive phase difference
And multiply and multiply with the spreading code with negative phase difference
Correlation processor for timing and multiple correlation processors for timing
Solve the output Walsh function and output as correlation value intensity
The high-speed converter for timing and one of the following elements (1) The output of the high-speed converter for timing is delayed by a required time.
Delay / selection circuit selected by the
The timing phase is determined by the correlation value strength selected by the selection circuit.
Supply of a spread code to the received signal input to the
Low-pass to obtain timing control signal to control the timing
Filter, (2) Judgment feedback signal from output of high-speed converter for timing
Correlation value intensity corresponding to specific Walsh function
And the correlation selected by the gate circuit
A delay / selection circuit that selects the value intensity after a predetermined time delay
And the correlation value strength selected by the delay / selection circuit.
Spreading code for the received signal at the input to the correlation processor
A timing control signal for controlling the supply timing of the signal
Digital receiver consisting of a low-pass filter
, Equipped with. Further, according to the invention of claim 4, the transmission symbol is
A transmission symbol judgment method that judges and generates a judgment feedback signal
Stage, and a complex reception signal that has been synchronously detected and a predetermined spreading code.
And a correlation processor for multiplying and adding
Solve the Walsh function of force and output as correlation value intensity
A high-speed converter, a complex reception signal synchronously detected and
Multiply and add the spreading code of the phase difference and the negative phase difference and add
Timing correlator and these multiple timings
A delay circuit for delaying the output of the correlation processor for an appropriate time;
A specific signal is determined from the decision feedback signal output from the transmission symbol decision means.
A Walsh function generator for generating an Walsh function,
Multiple timing correlator outputs and Walsh functions
Correlate with the Walsh function given by the generator
And a plurality of correlating means.
And to control the supply timing of the spreading code using
Digital receiver .

Further, according to the fifth aspect of the present invention, the complex input signal and the expanded
Correlate with the scatter code
Searcher receiver, and complex input signal and predetermined
Correlation between the positive and negative phase differences of the
Select a specific transmission candidate symbol and select the selected transmission candidate symbol.
Digital receiver phase to set timing by vol
Timing setting means and searcher
Value strength at data demodulation timing determined by output
And the transmission candidate symbol after selecting the output of the timing setting means.
Multiplication circuit for multiplying the correlation value intensity of the
Transmission candidate symbol with a value obtained by adding the output for each combination timing
The maximum value is determined from among the correlation values of
The specified transmission candidate symbol
Also outputs decision feedback signal to stage and searcher receiver
Walsh symbol composed of a maximum value determination circuit
Number selection means.

According to a sixth aspect of the present invention, the complex received signal is expanded.
Multiply scattered codes and add them in a predetermined combination to obtain two orthogonal components
A plurality of correlation processors for obtaining the output of
Provided on the input side or output side of the
Adjust the timing or output timing, or
Adjusts the timing of the PN code input to the number of correlation processors.
Timing adjustment means to adjust the timing
Gate for sequentially selecting and outputting multiple correlated processor outputs
Circuit and a correlator sequentially output from the gate circuit
Solve the Walsh function for each of the two orthogonal components of
From multiple high-speed converters and these multiple high-speed converter outputs
And correlation value strength calculating means for calculating the correlation value strength.
A search processing means .
The invention according to claim 7 is the same as the invention according to claim 6, except that the transmission symbol
Transmission symbol determination that determines the signal and generates a decision feedback signal
Means, wherein the search processing means comprises:
Identify from correlation value strength of transmission candidate symbol by signal
Selector for selecting the correlation value strength of the Walsh function of
And a decision feedback type search processing means.

The invention according to claim 8 determines a transmission symbol.
Transmission symbol determination means for generating a determination feedback signal
And multiplying the complex reception signal by a predetermined spreading code
Processing unit that obtains the output of two orthogonal components by adding in a combination
And the Walsh of two orthogonal components from the output of the correlator.
A high-speed converter that correlates with a function and the output of this high-speed converter
A correlation value strength calculation circuit for calculating the correlation value strength of the
Signal and a predetermined spreading code are multiplied and added in a predetermined combination.
Multiple timing correlations to obtain two orthogonal component outputs
Processor and the outputs of these multiple timing correlation processors.
Delay means for delaying, outputs from these delay means, or
Or, if necessary, output through a time-sharing gate circuit.
And timing for solving correlation with Walsh function
Converter and the phases solved by these high-speed timing converters.
Of the Walsh function selected by the decision feedback signal
Correlation value strength calculation circuit for calculating correlation value strength, and this calculation
Averages the output differences of the calculated correlation value intensities and supplies the spreading code
A loop filter that controls timing
Digital receiver . The invention of claim 9
Determines the transmission symbol and generates a decision feedback signal.
Signal symbol determining means, and a synchronously detected complex reception signal.
A correlation processor for multiplying and adding the signal and a predetermined spreading code,
Solve the Walsh function of the correlation processor output and calculate the correlation value intensity
High-speed converter to output the complex received signal and the predetermined spread
Multiply the codes and add them in the determined combination to obtain the orthogonal two-component
A plurality of timing correlators for obtaining outputs, and
Delay means for delaying the output of a number of timing correlators
And a specific Walsh function based on the decision feedback signal
Function generating means and output of a plurality of delay means
And the Walsh given by the Walsh function generator.
Plural correlations for obtaining orthogonal correlations with two functions
Means and the correlation intensity from the outputs of the plurality of correlating means.
And a plurality of correlation value intensity calculation means for calculating the respective correlation value intensities.
Using the output of the correlation value strength calculation means.
Digital receiver that controls supply timing
, Equipped with.

[0036]

In the spread spectrum signal receiver according to the present invention, in the case of the first aspect, a synchronous detection type searcher receiver is provided, wherein the timing of the output signal from the correlator is shifted, and enters the converter, and the FHT or the like A transformer that solves the Walsh function of is used in a time division manner. A second aspect of the present invention is a synchronous detection type searcher receiver in which data of a specific Walsh function is further selected. This eliminates unnecessary calculation of the Walsh function. A third aspect of the present invention is a synchronous detection type digital data receiver. In the timing setting means, a correlation value of a specific Walsh function obtained from another demodulated data is selected, and the timing is tracked. This allows
Unnecessary calculation of the Walsh function is eliminated, and reliable timing can be set.

According to a fifth aspect of the present invention, there is provided a searcher receiver.
The correlation strength at the data demodulation timing given by the data is multiplied by the correlation strength of the transmission candidate symbol of the timing conversion output of the digital data receiver. The symbols are fed back to the search receiver and digital data receiver of each diversity. This reduces the probability that an incorrect correlation value will be selected.

According to a sixth aspect of the present invention, in the searcher receiver, the timing of the output signal from the correlator is shifted, the signal enters the converter, and the converter for solving the candidate symbol is used in a time division manner. According to a seventh aspect of the present invention, there is provided a searcher receiver, wherein another transmission symbol determining means selects a correlation value of the specified transmission symbol and outputs the correlation value. This eliminates calculations for unnecessary transmission symbols. The digital data receiver is a digital data receiver. In the digital data receiver, the timing setting means selects a correlation processing value of a specific candidate symbol obtained from another demodulated data, and performs timing tracking. This allows
Calculation for unnecessary transmission symbols is eliminated, and timing can be reliably set.

[0039]

[Embodiment 1] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 shows the synchronization detection provided at the base station (CelSate).
FIG. 3 is a block diagram showing an overall configuration of a wave type searcher receiver . In the case of synchronous detection, the carrier frequency of the received signal
Separate receiver for carrier wave recovery circuit etc. to recover wave number and phase
I have it. Quadrature detection signal is detected by using a local oscillator which are orthogonal to each other from the received SS signal r _I, r _Q are input to the search processing circuit 610, PN signals and Uorusshu function number is released. Here, this processing is performed at a plurality of different timings, and the result is serially output as parallel data. That is, the processing results for the 64 Walsh functions are output in parallel, and those whose observation timing is shifted are sequentially output. The output signal of this search processing circuit is input to the maximum value determination section 612, where the signal having the largest absolute value is selected from the outputs of the 64 search processing circuits.

Here, the maximum value judging section 612 does not use a squaring circuit absolute value circuit or the like to judge the absolute value.
For example, the maximum value may be determined in a portion excluding the sign bit. That is, for the sake of simplicity, it is assumed that the input data is 4 bits, and (0010) = +
2, (1011) =-3, (0001) = + 1, (11
When (00) -4 is input, data excluding the most significant bit indicating the polarity is (010) = 2, (011) = 3
Reading is performed as (001) = 1 and (100) = 4, and the maximum value 4 is selected. The output selected by the maximum value determination unit 612 is input to the adder 616, and the output of the frame memory 618 is fed back via the multiplier 620.
A cyclic addition is performed by the multiplier 620. Here, the frame memory 618 has a capacity corresponding to the observation time, and the multiplier 620 multiplies a weight less than 1 so that the addition result does not diverge. Therefore, with this configuration, cyclic addition is performed in units of observation time.

In this manner, the maximum value output selected by the cyclic addition is averaged, and an output signal at a timing from which noise has been removed is supplied to a processor or the like of the receiver.

Embodiment 2 FIG. FIG. 2 shows the overall configuration of another embodiment of the synchronous detection type searcher receiver of the present invention. In this example,
Delay circuit 622 instead of maximum value determination section 612 in FIG.
And a selector 624. The selector 624 selects and outputs a specific result from the processing results for the 64 Walsh functions according to a decision feedback signal input from the outside. Therefore, the selection is not made based on the magnitude of the processing result for the Walsh function at that time. Further, the delay circuit 22 has a required time (for example,
This is for obtaining the time until the decision feedback signal is input or one data symbol time corresponding to one cycle of the spread code.

Next, a specific configuration of the search processing circuit 610 will be described with reference to FIG. Quadrature detection signal r
_I and r _Q are input to shift registers 630 and 632, respectively. In this example, shift registers 630, 632
Has a capacity of 4 chips corresponding to an observation time of 4 chips and 1 chip / sample, and is divided into four sections.

It should be noted that an observation time other than 4 chips and a sample other than 1 chip can be used. Furthermore, one chip is
Instead of 1-bit data (binary), it may be composed of, for example, 8-bit data (256 values). Also, "64" in the data bus is 6 bits for an 8- bit or more bus.
It means that there are four. The signals from the sections of the shift registers 630 and 632 are respectively
It is input to the correlation processors 634, 636, 638, 640. That is, the last data (newest data) of the shift registers 630 and 632 are input to the correlation processor 634, the next data is the correlation processor 636, and the next data is
The most preceding data (oldest data) is input to the correlation processor 638, and is input to the correlation processor 640.

The correlation processors 634 , 636 , 63
Numerals 8 and 640 are for multiplying the received data by a PN code, solving the multiplied PN code on the transmission side, and outputting only the Walsh function. Normal correlation processing
In After product vessel, but outputs the correlation value subjected to integral operation, the correlation processor in the present invention 634,636,638,6
In 40, the integration operation after the product is executed when the Walsh function is solved by the FHT described later.

The spread signals PN _I ′ and PN _Q ′ are input to the correlation processors 634 to 640, respectively, and a multiplication and addition process of the input signal and the spread signal is executed. Then, due to the presence of the shift registers 630 and 632, the correlation processors 634 to 640 execute the product addition processing of the input signal and the spread signal at a timing shifted by one chip. Further, the spreading code PN _I 'and PN _Q' are supplied to these correlators 634-640 may, PN code PN _I for I and Q signals, the user PN signal PN _U allocated to each user PN _Q are multiplied It was formed. Arbitrary Walsh function series
W, if the phase difference (known) between the transmitting and receiving carriers is θ, then PN
If the sign timing is correct,
The output Y of the adder 80 in the correlation processor 634 has the following value. Y = W portion of [2 (cosθ + sinθ) +2 PN Q 'PN I' (cosθ-sinθ)] late _{2 PN Q 'PN I' (} cosθ-sinθ) is random, the average to zero the integration ,
After all, only the following values are significant: W2 (cos θ + sin θ) = W2 ^1/2 · cos (θ−π / 4 ) Therefore, if θ = π / 4, a significant signal is generated at the output of the adder.
The signal component can be maximized.

The output of the correlation processor 634 is sent to the serial / parallel converter 648 via the shift register 642 for three chips, and the output of the correlation processor 636 is sent to the serial / parallel converter 6 via the shift register 644 for two chips.
50, the output of the correlation processor 638 is sent to the serial / parallel converter 652 via the shift register 644 for one chip.
Meanwhile, the output of the correlation processor 640 is directly input to the serial / parallel converter 654. Therefore, the serial-to-parallel converters 648 to 654 provide the signals obtained at the same timing.
The output of the correlated processor is input and converted to a parallel signal. That is sequentially input to the gate circuit 656 as parallel data for 64 correlation signals sequentially input solves the Walsh function sequence length 64.

The gate circuit 656 operates according to an input gate signal.
Signals from 48 to 654 are sequentially output in a time-division manner. The output of the gate signal is sequentially supplied to the FHT 658,
Here, the fast Hadamard transform is performed, and the Walsh function is solved. Therefore, if the timing of the PN code to be multiplied with the received data coincides, only one of the 64 outputs of the FHT 658 increases. That is , noiseless
When the output of F HT64 is the correlation output for 64 Walsh functions, and the input data is, for example, all 0's
, Only the processing (correlation) result relating to Walsh 0 [W0] becomes a value corresponding to the signal amplitude, and the other values appear as output values. If the input signal is another Walsh function, only the processing output of the corresponding function number has a value corresponding to the signal amplitude . Then, data corresponding to the four input data of the FHT 658 are sequentially output. Then, the output of the FHT 658 is sequentially output from the search processing circuit 610.

[0049] Thus, among the FHT output when the PN code timing is multiplied with the received data match, only the correlation output of Uorusshu function corresponding to the transmission data signal
A value corresponding to the signal amplitude (maximum), and the correlation output of other Walsh functions is only a noise component if there is no multi-bus component. At other times, a correlation output corresponding to the correlation characteristic between the PN code and the Walsh function is obtained,
The value is relatively smaller than the maximum value . In some cases, the noise component, the delay wave component, and the correlation component due to the timing shift have a considerably large value.However, since they behave randomly, it is possible to reduce the value to a sufficiently small value by performing cyclic addition. is there. If FIG.
When the search processing circuit 610 is applied, the maximum value is detected for the output from the search processing circuit 610 and the cyclic addition is performed, so that the received signal power corresponding to the despread timing is obtained. Can be

Therefore, by repeating the cyclic addition,
If there are multiple buses, a reception power value corresponding to the strength of each bus is obtained at a timing point (point corresponding to the frame memory in the cyclic addition) corresponding to the signal arrival timing of each bus, and the signal arrival timing Other than small enough
The Sana value. Therefore, by looking at the contents of the frame memory, information as to what level of signal has arrived at which signal timing is obtained, and this is output to the control processor. This information is used when timing tracking becomes impossible due to fading or the like in a timing recovery circuit or the like described later, or a signal obtained from a plurality of data demodulators in a diversity synthesis circuit or the like described later is used as an effect. It is used as information for the purpose of composition.

As described above, in the embodiment of FIG. 3, in order to search for the received power according to the arrival time of each bus, the FHTs that originally required four FHTs are adjusted by adjusting the timing. Since the FHT is used in a time-sharing manner, the hardware scale can be reduced. In this embodiment, the shift registers 630 and 632 in FIG. 3 have four stages, that is, the case where the observation time (observation window size) is four chip times, but by increasing the number of stages of the shift registers. The observation time can be easily increased, and in this case, the effect of reducing the hardware scale by using the time-sharing of the FHT is further increased.

FIG. 4 shows a preferred configuration example of the correlation processors 634 to 640. The multipliers 660, 662 in FIG.
664 and 666 are multipliers for solving the PN code.
As shown in FIG. 4, the outputs of the multipliers 660 and 664 are input to the adder 668, and the outputs of the multipliers 662 and 666 are input to the adder 70. This is because when there is a phase difference between the carrier and the local oscillator, the quadrature detection signal r
The phase difference between _I and r _Q effectively removes the influence of having signal components between the orthogonal axis components. That is, the multiplier 662 extracts the transmission-side Q-axis component leaked into r _I , and the multiplier 664 extracts the transmission-side I-axis component leaked into r _Q. The effects described above can be obtained by adding the results with the adders 668 and 670 with the polarities shown in FIG. Also,
After the influence of the phase difference is removed and the different PN codes are solved, the same component is output to both, so that the adder 680 adds the signal components to effectively combine the signal components. That is, the synchronous detection method, Filter retardation sender and receiver (i.e. theta = to [pi / 4) It is possible, the output of the adder 680 is the transmission side of the signal effectively reproduce it can.

The output of the adder 680 is converted into 4-parallel data in a 1/4 serial-parallel converter 682, and four data are output at the same time. Is calculated. Therefore, the data of the four chips of the PN signal are summed by the summing circuit 684 to form one data. This is because the Walsh function in the reverse link is PN4
For chips, the Walsh function is one chip.
Are multiplied, in FHT658, when solving Uorusshu is because it is necessary that a sequence of data Uorusshu 1 per chip.

Embodiment 3 FIG. Digital data receiver of synchronous detection system according to the present invention
FIG. 5 shows an example of the configuration. When demodulating data,
The repetition period of the Walsh function (also referred to as a symbol period, and each piece of data of the Walsh function is referred to as one chip, and this period is referred to as a chip period), and the generation timing of a PN code synchronized with this are detected. There must be. For this reason, a timing detection circuit is required.

In the digital data receiver , the signal r
Accept _I , r _Q to solve PN signal, Walsh
Correlation processor 700, serial / parallel converter 702, F
HT704. Then, performed in the correlation processor 700, a spreading code PN _I ', PN _Q' processing for solving. The configuration of this correlation processor is as follows:
It has the same configuration as the correlation processor of the searcher receiver shown in FIG. Then, the phases compiled for each PN4 chip
The output of the processing unit is input to the serial / parallel converter 702 and converted into 64 parallel data.
The HT 704 performs a Hadamard transform and solves a Walsh function. Here, solving the Walsh function means taking a correlation with each Walsh function. From the orthogonality of the Walsh functions, when the timings match, only the transmitted Walsh function has a value corresponding to the signal amplitude, and the correlation result with the other Walsh functions is zero. Due to the correlation with the delayed wave, noise, etc., all the correlation outputs will have some value, but it is determined that the Walsh function having the largest correlation value has been transmitted from these, and the corresponding data is Demodulated simultaneously as transmission information data (here, 6 bits). As a result, demodulated data is obtained.

On the other hand, the signals r _I and r _Q are supplied to the correlation processor 71.
Is inputted to 0,712, wherein the spreading code PN _I 'delta and PN _I' - [delta supplied at different Ru timing, PN
_Q 'delta and PN _Q' correlation processing each row between -Δ
Will be If the input signal supplied to the correlation processor is synchronized with the spread code, the result of calculating the correlation by shifting the spread code in the positive or negative direction should be that the energy of the resulting correlation signal becomes smaller in each case. is there. So, FH
The timing can be detected by examining the energy of the correlation value of the transmission Walsh function obtained in T718 and 720.

To this end, the outputs of the correlation processors 710 and 712 are converted into 64 parallel data by the serial / parallel converters 714 and 716, and the Walsh functions are solved by the FHTs 718 and 720, and the delay / selection circuit 72
2, 724. The delay / selection circuits 722, 7
24 denotes a delay circuit 620 and a selector 62 in FIG.
The signal is the same as that of 2, and receives a select signal indicating which Walsh is used for communication from a maximum value detection circuit or the like used when performing data demodulation, and selects and outputs a signal of the Walsh function.

The outputs from the delay / select circuits 722 and 724 are input to a subtractor 726, and the difference between the two signals is calculated.
The signal obtained in this manner is a signal corresponding to the magnitude of the synchronization shift between the input signal and the spread signal, and an unnecessary component is removed by the low-pass filter 728 to obtain a timing control signal.

[0059] Then, the timing control signal PN _I
Generator 730, PN _Q generator 732, PN _U generator 73
4 to adjust the timing of the signals generated from these generators 730, 732, 734. Therefore, the signal P generated from these generators 730, 732, 734
N _I, PN _Q, PN _U becomes that there is an input signal and timing, and that synchronization in the correlation processing, etc. has been established.

[0060] Further, the output multiplier 736 of each generator 730,734, the output from the generator 732, 734 is multiplied with a user PN code PN _U in a multiplier 738, respectively spreading signal PN _I ', PN _Q Shift register 7
40, 742. This shift register 74
0 and 742 are divided into three sections. By sequentially shifting the input signal, spread signals with different timings can be output from each section. In other words, the data in the first section is the data preceding the data in the center section by Δ, and the data in the subsequent section is
This is data that is Δ after the data in the center section. Thus, PN _I than each section ', PN _Q' and P
N _I 'Δ, PN _I' and _{-Δ, PN Q 'Δ, PN} Q' -Δ
Is obtained.

The selection in the delay / selection circuits 722 and 724 is not limited to one. For example, the output of the two Walsh function numbers for the maximum value obtained by the maximum value detection circuit and the next largest value is selected. A method is also conceivable. This is because noise is mixed in, so it is necessary to be prepared for characteristic degradation, but since data demodulation is not always performed correctly, if the wrong Walsh function number is selected, the timing tracking system This is an effective method in such a case because a correct signal component may not be input at all.

Embodiment 4 FIG. FIG. 6 shows a configuration example of another digital data receiver according to the present invention.
Shown in In this embodiment, the configuration is simplified by using the FHT in a time-sharing manner. That is, the correlation process
Output from the vessel 700,710,712 are respectively inputted to the serial-parallel converter 702,714,716, the output of the serial-parallel converter 702,714,716 is supplied to the gate circuit 754. Correlator 70
0, 710, and 712 are output from the shift register 74.
The outputs are shifted by one shift at the timings of 0 and 742, respectively, and the outputs whose timings are shifted are sequentially supplied to the gate circuit 754. Therefore, the gate circuit 754 sequentially selects the outputs from the serial / parallel converters 714, 702, and 716, and sequentially supplies them to the FHT 756. Then, the output from the FHT 756 is input to the gate circuit 758, and the signal obtained by the FHT 756 is sequentially separated and output by selecting a signal corresponding to the gate circuit 754. Thus,
The signals whose timings (code phases) have been shifted are input to delay / selection circuits 722 and 724, and the signals based on the signals from the correlation processor 700 are output to the maximum value determiner for data demodulation.

Note that the maximum value judging circuit is shown in FIGS.
Although not shown directly in the example, for example, the correlation processor 70
6 obtained by the FHT 756 based on the timing of 0
The correlation value of 4 may be used as an input, and the maximum value may be determined with respect to the correlation value. In the case where diversity combining or the like is performed in order to improve reception characteristics, the combined value of 6 after combining is determined.
4 may be used as an input, and the maximum value may be determined for this. In the case of performing diversity combining, the maximum value determining unit 510 in the embodiment using FIG. 8 described later corresponds to this.

Here, the signals input to the delay / selection circuits 722 and 724 are different in time by 2Δ. Therefore, the delay / selection circuits 722 and 724 synchronize the signals and input them to the adder 724. Therefore, in the low-pass filter 728, a timing control signal similar to that of the above-described embodiment can be obtained. According to this embodiment, only one FHT is required, and the circuit is simplified.

Embodiment 5 FIG. FIG. 7 shows a configuration example of another synchronous detection type digital data receiver of the present invention. In this embodiment, the FHT is not used in the portion where the timing control signal is generated. That is, a Walsh function is specified from the demodulated data to determine which Walsh function is used based on the determination result in the demodulation unit or the like, and the specified Walsh function is generated by the Walsh function generator 760 according to this signal. Then, this Walsh is supplied to a three-divided shift register 762 to obtain three signals shifted by a time Δ.

On the other hand, the output signals from the correlation processors 710 and 712 are passed through delay circuits 764 and 766 to the
8, 770. To the multipliers 768 and 770, the first (Δ) signal and the last (−Δ) signal from the shift register 762 are supplied, respectively.
The signals from the correlators 710, 712 are now multiplied.
Note that the delay circuits 764 and 766 include multipliers 768 and 77
This is to match the timing with the Walsh function multiplied by 0. Therefore, the multiplier 76
At 8,770, the Walsh function is solved because the Walsh function is multiplied synchronously with the signal. The signal of the result of the multiplication is integrated with an integral discharge (I & D) circuit 7.
72, 774, and in one cycle of the Walsh function
Integrate over the corresponding time and output the result
As a result, a correlation value between the received signal, the PN code, and the Walsh function is obtained. Therefore, these I & D circuits 77
2, 774, and subtracts the output from the low-pass filter 72.
8, the same timing control signal as in the above embodiment can be obtained.

Embodiment 6 FIG. FIG. 8 shows an example of the overall configuration of a spread spectrum signal receiver according to the present invention. The searcher receiver in FIG.
Second synchronization detection method of searching Ya Reshiba or an example of applying the searcher receiver Examples 7-10 below, also digital data receiver of FIG. 8, the digital data of the synchronization detection method in Example 3-5, Receiver ,
Alternatively, this is an example in which the digital data receivers of Examples 11 to 13 described later are applied. In this embodiment, four systems of receivers are provided in order to configure spatial diversity. The control processor 16 controls the whole. 18, 19, the correlation value intensity of the total of 64 of the received data and the Uorusshu functions output from digital data receiver 2 a shown in FIG. 20 or the like, FIG. 15
Are multiplied by the received signal given from the searcher receiver 1a , that is, the power of the arriving wave currently received by the digital data receiver in the multiplier 501,
The result is latched by the latch circuit 505.

The same applies to other systems, and the 64 correlation value intensities weighted by the received power of the arriving wave are latched by the respective latch circuits 505, 506, 507, and 508. The control processor can know the processing timing of each digital data receiver from the searcher receiver and the digital data receiver. When the correlation value intensities of all the systems are latched, the control processor outputs a combined timing signal to each latch circuit and adds The value is added by the unit 509 for each Walsh function number. The output of the adder 509 is input to a maximum value determination circuit 510, which determines the Walsh function number that gives the maximum correlation value among the added correlation value intensities as a transmission symbol. Unlike this, the data is also output to each searcher receiver and each digital data receiver. The searcher receiver and the digital data receiver select a correlation value with the received signal corresponding to the returned Walsh function number, and perform processing relating to timing acquisition and timing tracking, respectively. The determined Walsh function number and correlation value intensity are guided to the decoder 511, where the error correction code is decoded.

Embodiment 7 FIG. FIG. 9 shows an embodiment of the searcher receiver of the present invention.
In the present embodiment, asynchronous
The case of performing detection will be described. As an orthogonal function corresponding to transmission data, 64 Walsh functions were used as transmission symbols, and the Walsh function was spread with a 256-chip PN code (that is, Walsh 1).
A case will be described in which a signal in which a chip is multiplied by four PN codes is received. FIG. 9 is a block diagram showing the configuration of a searcher receiver in a receiver for such a spread spectrum signal. In the figure, a spread spectrum signal received by an antenna is analog-processed by an analog receiver, detected using local oscillators orthogonal to each other, and
/ D converted baseband complex received signals r _I , r _Q
Is input to the search processing circuit 10 first.

The search processing circuit 10 continuously outputs correlation values between the received signal and all transmission candidate symbols as parallel data at different timings. That is, 6
The correlation values for the Walsh functions of No. 4 are sequentially output as parallel data in the order of the correlation. This operation is sequentially repeated for each observation time. The parallel data output from the search processing circuit is added in the adding circuit 12 and is input to the cyclic adder 14. The cyclic adder 14 is, for example, an output of the adder circuit 12 and the multiplier 14
6 and a frame memory 144 for sequentially storing the addition results with a capacity corresponding to the observation time.
And the contents of the frame memory 144 are set to predetermined values,
Alternatively, it comprises a multiplier 146 for weighting with a value given by the control processor. Then, cyclic addition is performed for each observation time to reduce the influence of noise. The weight at the time of cyclic addition is usually set to less than 1 so that the addition result does not diverge. The content of the frame memory is the averaged correlation value intensity at each timing within the observation time.

The contents of the frame memory 144 are as follows:
The control processor 1 as the output of the cyclic adder 14
6 is output to the timing control unit 18. The timing controller 18 instructs the digital data receiver to output a signal strength so as to demodulate the data at a timing at which the maximum correlation value strength is obtained within the observation time. As shown in FIG. 21, when there is an optional digital data receiver, the timing controller 18 instructs the digital data receiver to demodulate data at a timing at which a second correlation value intensity is obtained. .

The specific configuration of search processing circuit 10 in FIG. 9 will be described with reference to FIG. Searcher in Examples 1 and 2
This embodiment deals with an example in which asynchronous detection is performed , while the receiver is limited to the synchronous system. That is, the baseband complex received signals r _I and r _Q are stored in the shift registers 102 and 104, respectively. In this example, each of the shift registers 102 and 104 receives one complex reception signal for one chip of the PN code, and is divided into four sections corresponding to the case where the observation time is four chips of the PN code. I have.

It is to be noted that the present invention can be applied even if the observation time is other than 4 chips, or a case where one complex reception signal is input to one chip of the PN code. Further, the complex reception signal may be composed of, for example, 8 bits (256 values) instead of 1-bit data (binary). This can improve reception characteristics by a soft decision technique well known to those skilled in the art.
Also, "64" in the data bus in the figure is 8 bits.
Or it means that there are 64 buses of more .

The shift registers 102, 10
The signals from each section of FIG.
6, 108, 110 and 112. This correlation processor corresponds to the correlation processors of the first and second embodiments.
Has a configuration suitable for asynchronous detection. The last data (newest data) of the shift registers 102 and 104 is input to the correlation processor 106, the next data is input to the correlation processor 108, the next data is input to the correlation processor 110, and the most preceding data is input. (Oldest data) is input to the correlation processor 112.

The correlation processors 106, 108, 11
0 and 112 are for multiplying the received data by a PN code, decomposing the PN code multiplied on the transmission side, and outputting a transmission symbol sequence. The detailed operation of the correlation processor will be described later. I do. In a normal correlator, an integration operation is performed after multiplication, and a correlation value is output. In the correlation processors 106, 108, 110, and 112, the integration operation after multiplication is performed only for one chip of the Walsh function. The rest is executed when the correlation value of the Walsh function is output by the FHT described later. Further, in the baseband complex reception signal, there is a phase difference between the transmitted and received carriers when the frequency conversion is performed by the analog receiver, but the correlation processor obtains the correlation value strength obtained by the correlation value strength calculation circuit 206. The correlation processing is performed without being affected by the phase difference and at a maximum.

The output of the correlation processor 106 is input to serial / parallel converters 130 and 132 after timing adjustment by the shift registers 118 and 120. Similarly, the output of the correlation processor 108 is the shift register 12
After the timing is adjusted by 2 and 124, the signals are input to serial / parallel converters 134 and 136. Similarly, the output of the correlation processor 110 is output to the serial / parallel converters 138 and 140 after the timing is adjusted by the shift registers 126 and 128. And the correlation processor 11
2 are directly output from the serial / parallel converters 142 and 144.
Is input to Therefore, the serial / parallel converter 130,
132, 134, 136, 138, 140, 142, 1
The results of the correlation processing at different timings are sequentially input to 44 in accordance with the adjusted timings. The serial / parallel converter outputs 64 parallel data to the gate circuit every time the parallel data is determined. That is, the parallel signal is determined, and the gate circuits 146, 14
8 depends on the adjusted timing, and in this embodiment, the correlation processors 106, 108,
The signals are output to the gate circuit 146 in the order of the signals processed in 110 and 112, that is, in the order of the outputs of the serial / parallel converters 130, 134, 138 and 142, and are gated in the order of the outputs of the serial / parallel converters 132, 136, 140 and 144. It is output to the circuit 148.

Gate signals corresponding to the timing at which the parallel data is determined from the respective serial / parallel converters are also input to the gate circuits 146 and 148, and the respective parallel data outputs from the serial / parallel converters are supplied in accordance with the gate signals. The correlation value is output to a correlation value calculation circuit that calculates a correlation value for all transmission candidate symbols (Walsh function). In this embodiment, the correlation value calculation circuit uses FHT
The case where the processors 150 and 152 are used is shown. The FHT processors 150 and 152 calculate and output the correlation values of the 64-chip parallel data processed by the correlation processor and the 64 Walsh functions synchronized with the spread code used by the correlation processor. . That is, the input is 64 chips of correlated parallel data corresponding to the number of sequences of the Walsh function, and the output is a correlation value for 64 Walsh functions, which are all transmission candidate symbols. The maximum value of the FHT output is the correlation value corresponding to the transmission symbol number when the parallel data subjected to the correlation processing at the same timing as the reception data is input. P if timing does not match
Due to the autocorrelation characteristic of the N code, all 64 correlation values are reduced on average, and if the Walsh function numbers differ even if the timings match, the correlation value becomes 0 due to the orthogonality of the Walsh functions. However, the noise superimposed during the communication remains according to the correlation with the signal band, the PN code, and the Walsh function.

[0078] In the search processing circuit 10, the baseband complex reception signal is input, the correlation processor and the serial-parallel converter to be described later 130-144 is configured as shown in FIG. 10, the phase difference between transmission and reception carrier Is φ, a value obtained by multiplying the amplitude correlation value with the received signal by cos φ is output to the output of the FHT 150, and a value obtained by multiplying the amplitude correlation value with the received signal by sin φ is output to the output of the FHT 152. Is done. The correlation value intensity calculation circuit 154 uses the FHT
The correlation value intensities for all the Walsh functions are calculated and output from the outputs 150 and 152, respectively, and are output from the search processing circuit 10. The correlation value intensity calculation circuit 154 is configured by, for example, a square sum calculation circuit or the like, and calculates (amplitude correlation value / cos φ) ² + (amplitude correlation value / sin φ) ² . The result is (amplitude correlation value) ² · (cos ² φ + sin ² φ) = correlation value power, and the correlation value power is obtained.

Since the searcher receiver does not judge the transmission symbol, it cannot know which correlation value among the 64 correlation values is the correlation value corresponding to the transmitted symbol. Therefore, all the correlation values of the output of the search processing circuit 10 are added. By suppressing the influence of noise by the cyclic adder 14, if there is a point where the timing with the received wave coincides within the observation time, it is possible to identify a correlation value corresponding to the power of the received wave. Further, even when a plurality of arriving waves are present due to multipath fading in the received wave, as long as there is a timing coincidence point with the arriving wave within the observation time, the correlation value power is obtained at each coincidence timing, The timing and power of the incoming wave can also be identified.

Next, the operation will be described with reference to a timing chart. FIG. 11 is a timing chart for explaining the operation of the search processing circuit of FIG. In the figure, PN indicates a PN code, and r
Indicates a received signal, W indicates a Walsh function (function number is arbitrary), and each number indicates a chip number. The timing of the received signal is a temporary timing based on the timing input to the correlation processor 106. 1 ′ and 2 ′ are the first chips of adjacent transmission symbols,
The second chip is shown, and the other “′” is the same. FIGS. 3A, 3C, 3E, and 3G show the timing relationship between the PN code and the reception signal corresponding to the correlation processors 112, 110, 108, and 106, respectively. That is, the PN code is input to each correlator at the same timing, but the reception data is input at the timing adjusted by the shift registers 102 and 104, so that the timing relationship between the PN code and the reception data is ( a), (c),
(E) and (g) are shifted one chip at a time.
(B) shows the timing relationship between the serial-parallel converters 142 and 144, and (d) shows the serial-parallel converter 1
(F) shows the timing relationship between the serial / parallel converters 134 and 136, and (h) shows the timing relationship between the serial / parallel converters 130 and 132. ( B ) remains as it is,
(D), (f), and (h) are (c), (e),
(G) shows shift registers 128 and 126 and 124 and 12
2, time shifted according to the timing adjusted by 120 and 118. However, since the timing is adjusted after the output of the correlation processor, the relative timing relationship between the PN code and the received data does not change. However, (b), (d), (f),
Since the relative relationship of (h) is different, the time for determining the parallel data in the serial / parallel converter is represented by T in the figure, and the moment of the determination is represented by a downward arrow in the figure. Shifts one chip at a time. Therefore, the gate circuit sets F in accordance with the fixed time of the parallel data.
By performing input control to the HT, time-sharing use of the FHT becomes possible. FIGS. 1 (1), (2), (3) and (4) show timing relationships when the correlation for all transmission candidate symbols is calculated by the FHT. By processing the PN code and the Walsh function chip in a synchronous correspondence, it is possible to obtain a comprehensive correlation value between the PN and the Walsh function for the received data.

Embodiment 8 FIG. Another embodiment of the search processing circuit will be described. FIG. 12 is a block diagram showing the configuration, which differs from the search processing circuit 10 of FIG. 10 in the timing adjustment means. That is, in FIG. 10, the timing adjustment by the shift register is performed on both the complex baseband reception signal and the output of the correlation processor, but in FIG. By adjusting the timing, the FHT
Of the present invention will be described.

Next, this operation will be described with reference to a timing chart. FIG. 13 is a timing chart for explaining the operation of FIG. FIGS. 7A, 7B, 7C, and 7D show the timing relationship between the received data and the PN code in the correlation processors 112, 110, 108, and 106, respectively. In other words, correlation processing is performed on the received data at the same timing by shifting the timing of the PN code by the shift registers 156 and 158. However, considering the PN code as a reference, the timing of input to the serial / parallel converter has already been adjusted, and the time for determining the parallel data is also (a), (b), (c), (d). Are shifted one chip at a time. Therefore, the time division use of the FHT can be performed by making the gate signal correspond to the determined timing. (1), (2), (3),
(4) shows the timing relationship when (a), (b), (c), and (d) determine a correlation value by FHT.

The timing relationship between the received data obtained by the timing adjusting means and the PN code and the Walsh function chip is shifted rightward in FIG. 11 and shifted leftward in FIG. 13, but the relative relationship is understood. If so, the same function can be realized as a searcher receiver.

Next, details of the correlation processor used in the seventh and eighth embodiments will be described. FIG. 14 is a diagram showing a detailed configuration of the correlation processor according to the present invention. Any Uorusshu function sequence W ', phase axis, respectively a PN code orthogonal axes PN _I', 'if the complex signal representation of the transmitted signal, W' PN _Q · a _{(PN I '+ jPN Q'} ) Become.
Assuming that the phase difference between the transmitting and receiving carriers is φ, the received signal processed by the analog receiver is multiplied by exp (jφ) = cosφ + jsinφ, and r _I and r _Q are the products, respectively. real component of the result, since the imaginary component, and _{r I = W '· (PN} I' cosφ-PN Q 'sinφ) r Q = W' · (PN I 'sinφ + PN Q' sinφ). PN on the receiving side to indicate timing mismatch
Codes PN _I ", PN _Q" if the output of the adder 1065,1066 obtained according to the configuration of the figure, _{respectively, 2W '· (PN I'} PN I "+ PN Q 'PN Q") cosφ 2W _{'· (PN I' PN I} "+ PN Q 'PN Q") becomes a sinφ. In addition, PN _I 'PN _Q "and the PN _I" P here
N _Q 'cross-terms have zero correlation on average
Is omitted on the assumption that If the timing of the PN on the transmitting side matches the timing of the PN on the receiving side, the spread modulation by the PN code is released, and the desired characteristics are obtained. Otherwise, the correlation values corresponding to the respective correlation characteristics are output. become. 1067 and 1068 in the figure are accumulators,
Since the PN4 chip corresponds to one Walsh chip,
For example, it is configured by serial-parallel converters 1069 and 1070 and adders 1071 and 1072.

As described above, in the embodiment of FIG. 9, in order to capture and monitor (scan) the received power of the arriving wave arriving at different timings during the observation time,
By adjusting the timing of what originally required four HTs, the FHT is used in a time-sharing manner, so that the hardware scale can be reduced. In this embodiment, the case where the number of stages of the shift register used for the timing adjustment means in FIGS. 10 and 12 is four at the maximum is shown. Can also be increased. In that case, the hardware scale by the time division use of the FHT is further reduced.

Embodiment 9 FIG. Another embodiment of the searcher receiver in the spread spectrum signal receiver according to the present invention will be described with reference to FIG. In FIG. 9, all outputs of the search processing circuit 10 are combined by the adder circuit 12 and then input to the cyclic adder 14, whereas in FIG. The symbol number (Walsh function number) determined by the transmission symbol determining means is fed back. With this feedback signal, in the search processing circuit, 64
Of the correlation value intensities, only one is selected and input to the cyclic adder.

FIG. 16 shows a detailed embodiment of the decision feedback type search processing circuit 20 of FIG. In FIG. 16, the correlation processor, the timing adjusting means using the shift register, and the serial / parallel conversion are the same as those in FIG. 10, and the parallel data subjected to the correlation processing becomes the serial / parallel converter output according to the adjusted timing. These outputs are input to delay and gate circuits 202 and 204, respectively. Delay and gate circuits 202, 204
Then, the parallel data is delayed until the transmission symbol is determined by another transmission symbol determination means, and when the transmission symbol is determined (the Walsh function number is fed back), the parallel data is determined according to the adjusted timing. Are output to the FHTs 150 and 152, respectively. In response to this output, the FHTs 150 and 152
6, 208, the calculated correlation values of all transmission candidate symbols are output. Selectors 206 and 208 are FHT1
Only the correlation value related to the Walsh function number (transmission symbol) that has been subjected to decision feedback from the outputs of 50 and 152 is selected and output to the correlation value strength calculation circuit 210. The correlation value strength calculation circuit 210 calculates, for example, a sum of squares of the correlation values given from the selectors 206 and 208, and sequentially outputs correlation values at different timings regarding the determined symbols as an output of the decision feedback type search processing circuit 20. Output.

Embodiment 10 FIG. Another embodiment of the searcher receiver of the present invention will be described with reference to FIG. FIG. 17 differs from FIG. 16 in the method of realizing the timing adjusting means, but the other operations are the same. A timing adjustment method other than delaying the parallel data until the Walsh function number is fed back is described in FIG.
Is the same as

At the start of communication, a known signal may be transmitted as a preamble in order to make the initial timing estimation more reliable. In such a case, even in the searcher receiver in FIG. 15, a more reliable acquisition characteristic can be realized by inputting the transmission symbol number corresponding to the known signal from the control processor without inputting the feedback signal.

Embodiment 11 FIG. One embodiment of a digital data receiver in a spread spectrum signal receiver according to the present invention is shown in FIG. The digital data receiver has timing tracking means and correlation value strength calculation means. That is, the acquisition timing given from the timing controller 18 shown in FIG. 9 or 15, calculates the correlation value between the received signal and the PN code and Uorusshu function performs timing tracking.

In FIG. 18, a digital data receiver receives a baseband complex reception signal r _I , r _Q as input, calculates a correlation with a PN code and a Walsh function, and outputs a correlation value intensity, and a serial processor 302. Parallel converters 322 and 324, FHTs 342 and 344,
It comprises a correlation value intensity calculation circuit 362. First, when in the correlation processor 302, a spreading code PN _I, correlation processing for solving PN _Q is performed, and outputs a received signal correlation processing signals accumulating the PN4 chips. The configuration of the correlation processor 302 is the same as that of FIG.
Two components, a component having osφ and a component having sinφ, are output. This output becomes, for example, 64 parallel processed parallel data in the serial / parallel converters 322 and 324 and is output to the FHTs 342 and 344, respectively. Then, the FHT calculates a correlation value between each parallel data and the Walsh function. For example, F
The HT 342 calculates a correlation value with a component having cos φ, and the FHT 344 calculates a correlation value with a component having sin φ. The outputs of the FHTs 342 and 344 are output to a correlation value strength calculation circuit 362, and for example, a sum of squares is calculated for each correlation value for the same transmission candidate symbol, and 64 correlations excluding the influence of the phase difference φ between the transmission and reception carriers are removed. The value power is output as the total correlation value intensity. Correlation processor and FH
If the processing timing at T matches the timing of the received data, only the correlation value of the transmitted Walsh function number has a value corresponding to the reception level due to the orthogonality of the Walsh function, and the other correlation values Becomes zero. Correlation between signals arriving at different times, or the like noise effects, but any correlation value also will have some value, from these correlation values strength, directly or after diversity combining, the transmission symbol judging means , The Walsh function number having the largest correlation value is determined as the transmitted symbol, and the corresponding 6-bit data is demodulated as transmission data.

On the other hand, the baseband complex reception signals r _I , r _Q
Is also input to the correlation processors 304 and 306. And
A shift register 318 for adjusting the code phase of the PN code;
320, P having a code phase (timing) difference of Δ chips from the PN code input to the correlation processor 302.
An N code is obtained. Among them, PN _I (Δ) ′ and PN _Q (Δ) ′ having a positive code phase difference are supplied to the correlation processor 304.
Also, PN _I (−Δ) ′, PN _Q having a negative code phase difference
(−Δ) ′ are input to the correlation processor 306 and subjected to correlation processing. Usually, the value of Δ is one chip or 0.5
Chips are often used. When Δ is one chip, the shift registers 318 and 320 only need to shift the PN code by a clock having the same speed as the PN code. It should be done. The two outputs of the correlation processor 304 are converted into parallel data by serial / parallel converters 326 and 328, respectively, and the output of the correlation processor 306 is output to serial / parallel converters 330 and 332. Each parallel data is supplied to delay circuits 334, 336, 338, 3
At 40, the data is delayed until another transmission symbol determination means determines a transmission symbol based on the data output from the correlation value strength calculation circuit. When the transmission symbol is determined and the Walsh function number is fed back, the output of the delay circuit is FHT 346, 348, 350, 352.
The correlation value with the Walsh function is calculated at the timing synchronized with the timing of the PN code subjected to the correlation processing. Then, of the 64 calculated correlation values, only the correlation values corresponding to the determined Walsh function number are selected by the selectors 354, 356, 358, 360,
Correlation value strength calculation circuits 364 and 366 calculate the total correlation value power when there is a code phase difference.

Then, the difference between the outputs of the correlation value intensity calculation circuits 364 and 366 is calculated by an adder 368, and the result of the loop filter 3
Averaging is performed at 70, the clock frequency of the VCO 372 is controlled according to the value of the loop filter output 370, and the PN generators 308 and 31 are controlled by the controlled clock frequency.
By controlling 0 and 312, timing tracking is executed. The PN generators 308, 310, and 312 have signal inputs and outputs to and from the control processor 16, and first adjust the code phase at the capture timing given by the control processor,
By giving the current tracking timing to 6, the control processor controls the timing together with the signal from the searcher receiver.

[0094] In the above embodiment, the serial-to-parallel converter the input to FHT of the data are correlated, there is shown a case of giving parallel-converted form, it shifted to the portion to be input to FHT It is also possible to provide a register and input the data serially. In data demodulation and timing tracking, the same operation as described above can be obtained as long as the correlation value at the timing of the received signal and the timing having a slight code phase difference can be obtained. If the correlation value is calculated, the processing amount can be reduced, and as a result, the power consumption can be reduced. Only one process is required for each data timing.

Embodiment 12 FIG. FIG. 19 shows another embodiment of the digital data receiver according to the present invention. In the embodiment of FIG. 19, the transmission symbol decision and the correlation values necessary for timing tracking, the timing of the received signal, so the correlation values at a timing having a positive and negative sign the phase difference, the correlation processor 302,30
It is possible to adjust the timing of the data subjected to the correlation processing in steps 4 and 306 by the timing adjusting means, and use the FHT in a time-division manner. FIG. 19 shows an example in which the component having cos φ in the parallel data is used for time-division use of the FHT, and the component having sin φ is used for time-division use of the FHT. The timing adjustment means includes delay circuits 334, 336, 338, and 340 and a gate circuit 374,
376 and gate circuits 382 and 384. The delay times D ₁ and D ₂ in the delay circuit are set to appropriate times until the Walsh function number is fed back or longer. Also, the gate circuit 374,
376 is controlled by the FHT to correlate the input signal with the Walsh function at a preferred time, and the gate circuit 382,
Reference numeral 384 operates to distribute signals to a system for demodulating data and a system for tracking timing.

Embodiment 13 FIG. FIG. 20 shows an embodiment of a digital data receiver according to still another configuration of the present invention. The configuration of this embodiment does not use the FHT for the timing tracking system.
That is, when the Walsh function number is determined, the Walsh function generator 410 generates a determination symbol sequence corresponding to the determined Walsh function number. The Walsh function generator may read, for example, a sequence written in a ROM or the like, or provide hardware or software for performing a process of inverse Hadamard transform for generating a corresponding symbol sequence by giving a function number. Configurations are possible. This output is sent to shift register 3
The shift register 412 adjusts the timing in the same manner as in the steps 18 and 320. Further, the product and the integration operation of the output of the correlation processor and the determination symbol sequence are performed in a timing relationship synchronized with that used in the correlation processing. A multiplier 414,
416, 418, 420, and the integrating discharge circuit 415,
417, 419 and 421. Thus, the correlation value for the received signal and the determination symbol can be calculated. Delay circuit 4
02, 404, 406, and 408 have a function of delaying the correlated data until the Walsh function number is determined and fed back. The FHT calculates correlation values for all transmission candidate symbols with respect to parallel data. In this embodiment, however, the hardware configuration is simple because multiplication of serial data with a symbol sequence and integration operation are performed easily. A converter is not required, and the circuit can be downsized.

[0097]

As described above, according to the spread spectrum signal receiver according to the present invention, the timing adjustment means is provided for the reception signal which has been subjected to the correlation processing with the PN code at different timings, and the FHT is provided. Since time-divisional use is used and the correlation value with all transmission candidate symbols is obtained at timings corresponding to different timings, there is an effect that the circuit scale can be reduced. In the searcher receiver, FH
The correlation values of all the transmission candidate symbols of the T output are delayed until the transmission symbol is determined by another transmission symbol determination unit, and only the correlation value of the determined transmission symbol is selected. Since the timing is acquired, there is an effect that unnecessary noise can be effectively removed.

Also, the timing tracking means in the digital data receiver selects only the correlation value for the determined symbol from the correlation values for all transmission candidate symbols of the FHT output, and performs timing tracking for the selected signal. Therefore, there is an effect that unnecessary noise can be effectively removed. Also, when a decision symbol sequence is generated and timing tracking is performed by obtaining correlation characteristics having positive and negative phase differences with the received signal, FHT and FH
Since the serial-parallel converter for processing the T input data is not required, there is an effect that the circuit scale can be reduced.

Further, the transmission symbol is determined from the correlation value strength after diversity combining in which the reception characteristic is effectively improved, and is fed back to the searcher receiver and the digital data receiver. Therefore, the probability of selecting the wrong symbol correlation value is determined. And the capturing and tracking characteristics are improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a searcher receiver according to an embodiment.

FIG. 2 is a block diagram illustrating an overall configuration of a searcher receiver according to another embodiment.

FIG. 3 is a block diagram illustrating a configuration of a search processing circuit.

FIG. 4 is a block diagram illustrating a configuration of a correlation processor .

FIG. 5 is a block diagram illustrating a configuration of a digital data receiver .

FIG. 6 is a block diagram showing another configuration of the digital data receiver .

FIG. 7 is a block diagram showing still another configuration of the digital data receiver .

FIG. 8 is a block diagram illustrating a configuration of a diversity receiver.

FIG. 9 is a block diagram showing the overall configuration of a searcher receiver according to an embodiment of the present invention.

FIG. 10 is a configuration diagram of a search processing circuit of FIG. 9;

FIG. 11 is a timing chart for explaining a timing relationship of the search processing circuit of FIG. 10;

FIG. 12 is another configuration diagram of the search processing circuit.

13 is a timing chart for explaining the timing relationship of the search processing circuit of FIG.

FIG. 14 is a configuration diagram of a correlation processor.

FIG. 15 is an overall configuration block diagram of a decision feedback type searcher receiver according to an embodiment of the present invention.

16 is a configuration diagram of a decision feedback type search processing circuit of FIG.

FIG. 17 is a configuration diagram showing another example of the decision feedback type search processing circuit.

FIG. 18 is a configuration diagram of a digital data receiver according to one embodiment of the present invention.

FIG. 19 is a configuration diagram showing another embodiment of the digital data receiver.

FIG. 20 is a block diagram showing another configuration of the digital data receiver according to one embodiment of the present invention.

FIG. 21 is a block diagram showing an overall configuration of a conventional spread spectrum signal communication apparatus.

FIG. 22 is a block diagram showing a detailed configuration of an analog receiver and a digital data receiver of a conventional spread spectrum signal receiver.

[Explanation of symbols]

Reference Signs List 10 search processing circuit 12 adder circuit 14 cyclic adder 142 adder 144 frame memory 146 multiplier 16 control processor 18 timing controller in control processor 102, 104 shift register 106, 108, 110, 112, 302, 304, 3
06 Correlator 114, 116 Multiplier 118, 120, 122, 124, 126, 128 Shift register 130, 132, 134, 136, 138, 140, 1
42, 144, 322, 324, 328, 330, 332 Serial / parallel converter 146, 148 Gate circuit 150, 152, 342, 344, 346, 348, 3
50,352 FHT 154,362 correlation intensity calculation circuit 156 shift register 1061,106 2, 1063,1064 multipliers 1065,1066 adder 1067,1068 accumulator 1069,1070 serial-parallel converter 1071, 1072 adder 20 determines Feedback type search processing circuit 202, 204 Delay and gate circuit 206, 208, 354, 356, 358, 360, 3
86,388 selector 210,364,366,390 correlation value strength calculation circuit 334,336,338,340 delay circuit 368 adder 370 loop filter 372 VCO 308,310,312 PN code generator 318,320 shift register 334,336 , 338, 340 delay circuit 374, 376, 382, 384 gate circuit 402, 404, 406, 408 delay circuit 410 Walsh function generator 412 shift register 414, 416, 418, 420 multiplier 415, 417, 429, 421 integral discharge Circuits 1a, 1b, 1c, 1d Searcher receivers 2a, 2b, 2c, 2d Digital data receivers 50 Diversity combining circuits 501, 502, 503, 504 Multipliers 505, 506, 507, 508 Latch circuits 509 Adder 510 Maximum value determination circuit 511 Decoder 64, 65, 66, 67 Analog receiver 610 Search processing circuit 612 Maximum value determination section 622 Delay circuit 624 Selector 626 Cyclic addition section 630, 632 Shift register 634, 636, 638, 640 Correlation Processors 642 , 644 , 646 Shift registers 648 , 650 , 652, 654 Serial / parallel converter 656 Gate circuit 658 FHT (high-speed Amadal converter) 660, 662, 664, 666 Multiplier 668, 670, 680 Adder 700, 710 , 712 correlation processor 702 , 714 , 716 serial / parallel converter 704, 718, 720 FHT 722, 724 delay / selection circuit 728 LF (loop filter) 730 PN _I generator 732 PN _Q generator 734 PN _U generator 740, 742 Shift register

Claims (9)

(57) [Claims] A complex received signal and a spreading code detected synchronously.
A plurality of the correlation processor for adding to multiplying the door, on provided on the input side or output side of the plurality of the correlation processor
The timing at which the inputs of multiple correlators are given or above
The timing at which the outputs of multiple correlation processors are given to the next stage
Adjust the output of the plurality of correlator units to different values
A timing adjusting means for outputting at a timing, and a correlator output group outputted at the different timing.
A gate circuit for sequentially selecting and outputting and a correlator output sequentially output from the gate circuit.
Fast transformation that solves Orsh function and outputs as correlation value intensity
And a search processing means comprising a searcher.
Spread spectrum using orthogonal code such as Walsh function
Signal receiver. 2. A complex detection signal and a spread code which are synchronously detected.
A plurality of the correlation processor for adding to multiplying the door, on provided on the input side or output side of the plurality of the correlation processor
The timing at which the inputs of multiple correlators are given or above
The timing at which the outputs of multiple correlation processors are given to the next stage
Adjust the output of the plurality of correlator units to different values
A timing adjusting means for outputting at a timing, and a correlator output group outputted at the different timing.
A gate circuit for sequentially selecting and outputting and a correlator output sequentially output from the gate circuit.
Fast transformation that solves Orsh function and outputs as correlation value intensity
And a search processing means comprising a converter and an output of the search processing means until a determination result is given.
And a decision feedback signal from outside the searcher receiver.
Correlation value of specific Walsh function from delay circuit output
A selector for selecting an intensity, and a cyclic selector for cyclically adding the correlation value intensity selected by the selector.
And a searcher receiver having a time adder.
Spread spectrum using orthogonal code such as Walsh function
Signal receiver. 3. A decision feedback signal is determined by determining a transmission symbol.
Transmission symbol determining means for generating, and a complex reception signal subjected to synchronous detection, and a predetermined positive phase difference and negative
Multiple timings for multiplying and adding the phase difference spreading code
Correlator, and Walsh output of the plurality of timing correlators
High speed for timing to solve function and output as correlation value intensity
A converter and any one of the following elements (1) delaying the output of the high-speed timing converter
A delay / selection circuit that is extended and selected by the decision feedback signal,
Depending on the correlation value strength selected by the delay / selection circuit,
For the input signal to the timing correlation processor
Timing control signal for controlling the supply timing of the spreading code
Low-pass filter, (2) above-format from the output fast converter for the timing to obtain the No.
Phase corresponding to a specific Walsh function by constant feedback signal
A gate circuit for selecting the intensity of the function,
A delay for selecting the selected correlation value intensity after a predetermined time delay
・ Selection circuit and correlation value selected by the delay / selection circuit
Reception of input to the timing correlation processor by intensity
Tie to control the timing of supplying spread codes to signals
Orthogonal marks such Uorusshu function low-pass filter, in digital receivers configured to obtain a timing control signal, further comprising a wherein
Spread spectrum signal receiver using signal. 4. A transmission symbol is determined and a decision feedback signal is generated.
Transmission symbol determining means for generating, and a complex reception signal subjected to synchronous detection, multiplied by a predetermined spreading code.
A correlation processor for multiplying and adding, and solving a Walsh function of the output of the correlation processor to increase the correlation value
A high-speed converter that outputs the signal as a degree, a complex reception signal that is synchronously detected, and a predetermined positive phase difference and a negative
Multiple timings for multiplying and adding the phase difference spreading code
And the outputs of the plurality of timing correlators are delayed by an appropriate time.
A delay circuit to be extended and a determination feedback signal output from the transmission symbol determination means.
Function generator for generating Walsh functions
And the outputs of the plurality of timing correlation processors and the wall
Phase with the Walsh function given by the Schiff function generator
And a plurality of correlator means for taking the correlation, and using the outputs of the plurality of correlator means,
Digital control of code supply timing
Orthogonal code such as a Walsh function , comprising a receiver
Spread spectrum signal receiver using signal. 5. A correlation between a complex input signal and a spread code is calculated.
In addition, a searcher ratio that solves the transmission candidate symbol of the correlation signal
And a complex input signal and a predetermined positive phase difference and negative phase difference spread code
And select a more specific transmission candidate symbol.
Set the timing according to the selected transmission candidate symbol
Timing setting equivalent to a digital receiver
Stage and data demodulation timing determined by the searcher receiver output.
Of the correlation value strength in the timing and the output of the timing setting means
The power to multiply by the correlation value strength of the selected transmission candidate Shinhol
And the transmission of a value obtained by adding the output of the multiplication circuit for each synthesis timing.
The maximum value is determined from the correlation values of the
The specific transmission candidate symbol determined to have a large value
Setting means and decision feedback signal to the searcher receiver
And a Walsh symbol number selecting means comprising a maximum value determining circuit that also outputs
Orthogonal codes such as Walsh functions characterized by having
Spread spectrum signal receiver using. 6. A product obtained by multiplying a complex reception signal by a spreading code.
Multiple phases to obtain the output of two orthogonal components by adding
And Seki processor, the upper is provided on the input side or output side of the plurality of the correlation processor
The input or output timing of the correlation processor
Adjusted or input to the plurality of correlators
Timing adjusting means for adjusting the timing of the PN code
And the outputs of the plurality of correlated processors whose timing has been adjusted are sequentially
A gate circuit for selecting and outputting two orthogonal correlation processor sequentially output from the gate circuit
Multiple heights to solve the Walsh function for each component
And a correlation for obtaining a correlation value intensity from the outputs of the plurality of high-speed converters
C, characterized in that it comprises a searcher receiver with the search process unit, and a value intensity calculating means
Spread spectrum signal using orthogonal code such as Orsh function
No. receiver. 7. A transmission symbol is determined and a decision feedback signal is generated.
A transmission symbol decision means for generating for the search processing means, the decision feedback signal generated as above
From the strength of the correlation value of the transmission candidate symbol.
Consists of a selector for selecting the correlation value strength of the Lusch function
Searcher search processing means
7. The spectrum according to claim 6, wherein the spectrum is provided.
Spread signal receiver. 8. A transmission symbol is determined and a decision feedback signal is generated.
Transmission symbol determination means for generating, and a combination determined by multiplying a complex reception signal and a predetermined spreading code
A correlation processor that obtains an output of two orthogonal components by adding the two components, and a Walsh function of the two orthogonal components from the output of the correlation processor.
A high-speed converter that solves the correlation between the high-speed converter and a correlation value intensity that calculates the correlation value intensity of the high-speed converter
A calculation circuit, a combination determined by multiplying a complex reception signal and a predetermined spreading code
Timing to obtain two orthogonal component outputs by adding
And a delay for delaying the outputs of the plurality of timing correlators.
And extension means, for time division according to output or required from the delay means
Phase between the output through the gate circuit and the Walsh function
The high-speed timing converter for solving the correlation and the correlation
Strong correlation value of Walsh function selected by decision feedback signal
A correlation value strength calculating circuit for calculating the degree of correlation, and averaging the output difference of the calculated correlation value strength to obtain the expanded value.
Orthogonal marks such Uorusshu function to loop filter for controlling the supply timing of diffusing code, further comprising a digital receiver, and a city wherein
Spread spectrum signal receiver using signal. 9. A transmission symbol is determined and a decision feedback signal is generated.
Transmission symbol determining means for generating, and a complex reception signal subjected to synchronous detection, multiplied by a predetermined spreading code.
A correlation processor for multiplying and adding, and solving a Walsh function of the output of the correlation processor to increase the correlation value
A high-speed converter that outputs a degree and a combination determined by multiplying the complex reception signal and a predetermined spreading code
Timing to obtain two orthogonal component outputs by adding
And a delay for delaying the outputs of the plurality of timing correlators.
A specific Walsh function is generated by the extension means and the decision feedback signal.
Walsh function generating means, outputs of the plurality of delay means , and the Walsh function generating means
The correlation with the Walsh function given by the step is orthogonal 2
A plurality of correlation means for the component, and a correlation strength calculated from the plurality of correlation means outputs.
A plurality of correlation value strength calculation means, and the output of the correlation value strength calculation means is used to provide the spread code.
Digital receiver with control of feeding timing
Orthogonal marks such Uorusshu function characterized by comprising Ba, the
Spread spectrum signal receiver using signal.