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JP2775848B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2775848B2
JP2775848B2 JP1125102A JP12510289A JP2775848B2 JP 2775848 B2 JP2775848 B2 JP 2775848B2 JP 1125102 A JP1125102 A JP 1125102A JP 12510289 A JP12510289 A JP 12510289A JP 2775848 B2 JP2775848 B2 JP 2775848B2
Authority
JP
Japan
Prior art keywords
substrate
side substrate
support
semiconductor device
supporting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1125102A
Other languages
Japanese (ja)
Other versions
JPH02303141A (en
Inventor
由弘 有本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1125102A priority Critical patent/JP2775848B2/en
Publication of JPH02303141A publication Critical patent/JPH02303141A/en
Application granted granted Critical
Publication of JP2775848B2 publication Critical patent/JP2775848B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔概要〕 半導体装置の製造方法に係り,特にSOI構造基板に形
成する半導体装置の製造方法に関し, 各素子の電位の浮遊を抑制し且つ温度上昇を防止する
ことを目的とし, 支持側基板,絶縁層,素子の形成された素子側基板か
らなるSOI構造基板の該支持側基板に,金属を拡散させ
て該支持側基板を合金化する半導体装置の製造方法によ
り構成する。
DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device formed on an SOI structure substrate, which aims at suppressing potential floating of each element and preventing a temperature rise. And a method of manufacturing a semiconductor device in which a metal is diffused into the support-side substrate of the SOI structure substrate including the support-side substrate, the insulating layer, and the element-side substrate on which the element is formed, and the support-side substrate is alloyed. .

〔産業上の利用分野〕[Industrial applications]

本発明は半導体装置の製造方法に係り,特にSOI構造
基板に形成する半導体装置の製造方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device formed on an SOI structure substrate.

高速,高密度,耐放射線LSI用基板として,Si層/酸化
膜/Si構造のSOI構造基板が有用である。
As a high-speed, high-density, radiation-resistant LSI substrate, an SOI substrate with a Si layer / oxide film / Si structure is useful.

近年,システムの巨大化,高速化に伴い,LSIの集積
度,動作速度の向上が要求されている。この要求を満た
すため,チップの消費電力が著しく増大し,素子の発熱
による温度上昇をいかにして抑制するかが,集積度,動
作速度の向上にとって大きな問題となっている。
In recent years, as the system becomes larger and faster, it is required to improve the degree of integration and operating speed of the LSI. In order to satisfy this requirement, the power consumption of the chip is significantly increased, and how to suppress the temperature rise due to the heat generation of the elements is a major problem for the improvement of the degree of integration and the operation speed.

〔従来の技術〕[Conventional technology]

従来,LSI基板ではパッケージの外部に冷却機構を付加
することによって素子の発熱による温度上昇を防止して
いる。しかし,素子を形成するSi層と支持側基板の間に
酸化膜のあるSOI構造基板では,酸化膜の熱伝導率が小
さいので,通常のバルク基板より素子の温度が上昇しや
すく,全体としての熱伝達の効率を向上させるために,
素子を形成したあと支持側基板をできるだけ薄くして金
属のパッケージにダイボンディングすることが行われ
る。
Conventionally, in a LSI substrate, a cooling mechanism is added to the outside of the package to prevent a temperature rise due to heat generation of an element. However, in an SOI substrate with an oxide film between the Si layer forming the device and the supporting substrate, the thermal conductivity of the oxide film is small, so the temperature of the device is more likely to rise than in a normal bulk substrate. To improve the efficiency of heat transfer,
After the elements are formed, the supporting side substrate is made as thin as possible and die-bonded to a metal package.

素子の温度上昇を防ぐためには,支持側基板の厚さは
薄いほど良いが,Siの機械的強度があまり大きくないた
め,ラップ加工では200μm程度が限界である。
In order to prevent the temperature of the device from rising, the thinner the supporting substrate is, the better. However, the mechanical strength of Si is not so large, so the limit for lapping is about 200 μm.

さらに薄くして熱抵抗を下げるためには,支持側基板
の機械的強度を高めることが必要である。さらに,支持
側基板の熱伝導率を上げることも有効である。
In order to further reduce the thermal resistance by reducing the thickness, it is necessary to increase the mechanical strength of the supporting substrate. Further, it is also effective to increase the thermal conductivity of the supporting substrate.

また,SOI構造では,各素子が絶縁層で支持基板と完全
に分離されるため,各素子が電気的に浮遊状態になる。
このため,外部若しくは内部ノイズによって各素子が誤
動作することがある。これを防止するためには,支持側
基板の電気伝導性を高め,支持側基板との容量性結合に
より各素子の電位を固定する必要がある。
Further, in the SOI structure, since each element is completely separated from the supporting substrate by the insulating layer, each element is in an electrically floating state.
Therefore, each element may malfunction due to external or internal noise. To prevent this, it is necessary to increase the electrical conductivity of the supporting substrate and fix the potential of each element by capacitive coupling with the supporting substrate.

ところが,支持側基板の機械的強度,熱伝導率,電気
伝導率については,ほとんど検討されていない。
However, the mechanical strength, thermal conductivity, and electrical conductivity of the supporting substrate have hardly been studied.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

従って,以上述べた問題点を踏まえてSOI構造の特徴
を発揮して高性能のLSIを実現するためには,支持側基
板に大きな電気伝導率,大きな熱伝導率,大きな機械的
強度を実現することが要求される。
Therefore, in order to realize the high-performance LSI by exhibiting the features of the SOI structure based on the above-mentioned problems, a large electrical conductivity, a large thermal conductivity, and a large mechanical strength must be realized on the supporting substrate. Is required.

本発明は,これらの問題点に応えるSOI構造を有する
半導体装置の製造方法を提供することを目的とする。
An object of the present invention is to provide a method for manufacturing a semiconductor device having an SOI structure that meets these problems.

〔課題を解決するための手段〕[Means for solving the problem]

上記課題は、単結晶シリコンからなる支持側基板、絶
縁層、及び素子の形成された単結晶シリコン素子側基板
からなるSOI構造基板の該支持側基板に、金属を拡散さ
せて該支持側基板を合金化する半導体装置の製造方法に
よって解決される。
The above object is to diffuse the metal into the support-side substrate made of single-crystal silicon, the insulating layer, and the support-side substrate of the SOI structure substrate composed of the single-crystal silicon element-side substrate on which the element is formed, thereby forming the support-side substrate. The problem is solved by a method of manufacturing a semiconductor device to be alloyed.

〔作用〕[Action]

本発明では,支持側基板1に金属を拡散することによ
って支持側基板1を合金化し,支持側基板1の電気伝導
率,熱伝導率,機械的強度を向上させている。
In the present invention, the supporting substrate 1 is alloyed by diffusing a metal into the supporting substrate 1 to improve the electrical conductivity, the thermal conductivity, and the mechanical strength of the supporting substrate 1.

機械的強度を向上させることにより,支持側基板1を
薄層化することができる。このことは熱伝導率の向上と
相まって素子から発生する熱を除去する作用を効果的に
する。
By improving the mechanical strength, the support-side substrate 1 can be made thinner. This makes the effect of removing heat generated from the element effective in combination with the improvement of the thermal conductivity.

電気伝導率の向上は素子が電気的に浮遊状態になるこ
とを抑制する作用を持つ。
The improvement in the electric conductivity has an effect of suppressing the element from being in an electrically floating state.

さらに,支持側基板1に金属を拡散する工程は素子側
基板3に素子を形成した後に行っているので,素子側基
板3がその金属に汚染される心配がない。もし,素子形
成前に支持側基板1に金属を拡散する工程を行うと,素
子形成のプロセスで素子側基板3がその金属に汚染され
るおそれがある。
Further, since the step of diffusing the metal into the support-side substrate 1 is performed after forming the element on the element-side substrate 3, there is no fear that the element-side substrate 3 is contaminated by the metal. If a step of diffusing a metal into the supporting substrate 1 is performed before the element is formed, the element-side substrate 3 may be contaminated by the metal during the element forming process.

〔実施例〕 第1図(a)乃至(e)は本発明の実施例を説明する
ための図であり,1は支持側基板,1aは厚さを減じた支持
側基板,2は絶縁層,3は素子の形成された素子側基板,4は
金属層,5は合金層,5aは厚さを減じた合金層を表す。
Embodiments FIGS. 1A to 1E are diagrams for explaining an embodiment of the present invention, in which 1 is a supporting substrate, 1a is a supporting substrate having a reduced thickness, and 2 is an insulating layer. Reference numeral 3 denotes an element-side substrate on which elements are formed, 4 denotes a metal layer, 5 denotes an alloy layer, and 5a denotes an alloy layer having a reduced thickness.

以下,第1図(a)乃至(e)を参照しながら実施例
について説明する。
The embodiment will be described below with reference to FIGS. 1 (a) to 1 (e).

第1図(a)参照 表面に絶縁層2としてSiO2膜の形成された2枚の6イ
ンチSiウエハを張り合わせた支持側基板1,絶縁層2,素子
側基板3からなるSOI構造基板の素子側基板3に,通常
のプロセスでLSIを形成する。
As shown in FIG. 1 (a), an element of an SOI structure substrate composed of a supporting side substrate 1, an insulating layer 2, and an element side substrate 3 on which two 6-inch Si wafers each having an SiO 2 film formed thereon as an insulating layer 2 are bonded. An LSI is formed on the side substrate 3 by a normal process.

各部の厚さは次の如くである。 The thickness of each part is as follows.

1.支持側基板(Si) 0.6mm 2.絶縁層(SiO2) 1μm 3.素子側基板(Si) 0.6mm 第1図(b)参照 支持側基板1を,厚さが0.3mm程度になるまでラップ
する。1aは0.3mm程度に厚さを減じた支持側基板を表
す。
1. Support-side substrate (Si) 0.6 mm 2. Insulating layer (SiO 2 ) 1 μm 3. Element-side substrate (Si) 0.6 mm See FIG. 1 (b). Wrap up. 1a represents a supporting-side substrate whose thickness has been reduced to about 0.3 mm.

第1図(c)参照 厚さを減じた支持側基板1a上に銅(cu)を約2μmの
厚さに蒸着し,金属層4を作る。
Referring to FIG. 1 (c), a metal layer 4 is formed by depositing copper (cu) to a thickness of about 2 μm on the supporting side substrate 1a having a reduced thickness.

第1図(d)参照 400℃,10時間の熱処理を行う。銅(Cu)は厚さを減じ
た支持側基板1aに拡散して支持側基板1aのSiと合金化
し,厚さを減じた支持側基板1aはSiとCuの合金層5とな
る。
Referring to FIG. 1 (d), a heat treatment is performed at 400 ° C. for 10 hours. Copper (Cu) diffuses into the reduced support-side substrate 1a and alloys with Si of the support-side substrate 1a, and the reduced-support-side substrate 1a becomes an alloy layer 5 of Si and Cu.

第1図(e)参照 合金層5を厚さが0.1mm程度になるまでラッピングす
ることにより,厚さを減じた合金層5aを形成する。この
ラッピングの際,合金層5の形成により支持側基板の機
械的強度が上がっているので,破壊することはない。
Referring to FIG. 1 (e), the alloy layer 5 is wrapped to a thickness of about 0.1 mm to form an alloy layer 5a having a reduced thickness. At the time of this lapping, the mechanical strength of the support-side substrate is increased by the formation of the alloy layer 5, so that the substrate is not broken.

その後,チップに切断し,パッケージにダイボンディ
ングする。
Then, it is cut into chips and die-bonded to a package.

このようにして,熱伝導率,電気伝導率がともに高い
支持側基板を持つSOI構造の半導体装置が実現する。
In this manner, a semiconductor device having an SOI structure having a supporting substrate having high thermal conductivity and high electrical conductivity is realized.

なお,厚さを減じた支持側基板1a上に蒸着する金属と
して,銅(Cu)の他に金(Au),バリウム(Ba)等450
℃以下の温度でシリコン(Si)と合金化する金属をいる
ことができる。合金化のための熱処理温度が450℃を超
えると,配線のAlがSiと反応して断線したり,pn接合を
破壊したりするので望ましくない。
In addition to copper (Cu), gold (Au), barium (Ba), etc.
There can be metals that alloy with silicon (Si) at temperatures below ° C. If the heat treatment temperature for alloying exceeds 450 ° C., Al in the wiring reacts with Si to cause disconnection or break the pn junction, which is not desirable.

また,厚さを減じた支持側基板1a上に銅を蒸着すると
き,その支持側基板1aを450℃以下に加熱し,蒸着と合
金化を同時に行ってもよい。
When depositing copper on the support-side substrate 1a having a reduced thickness, the support-side substrate 1a may be heated to 450 ° C. or lower, and the deposition and alloying may be performed simultaneously.

〔発明の効果〕〔The invention's effect〕

以上説明した様に,本発明によれば,支持側基板の機
械的強度を増大して支持側基板のラッピングによる薄層
化を可能にし,さらに支持側基板の熱伝導率を増大して
素子から発生する熱の流れに対する熱抵抗を低減し,素
子の温度上昇を防ぐことができる。
As described above, according to the present invention, the mechanical strength of the supporting substrate is increased, the thickness of the supporting substrate can be reduced by lapping, and the thermal conductivity of the supporting substrate can be increased to improve the device performance. It is possible to reduce the thermal resistance to the generated heat flow and prevent the temperature of the element from rising.

また,支持側基板の電気伝導率の向上により,各素子
の電位の浮遊を抑制することができ,ノイズによる素子
の誤動作を防ぐことができる。
In addition, by improving the electrical conductivity of the support-side substrate, floating of the potential of each element can be suppressed, and malfunction of the element due to noise can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

第1図は実施例 である。図において, 1は支持側基板であってシリコン基板, 1aは厚さを減じた支持側基板, 2は絶縁層であってSiO2膜, 3は素子の形成された素子側基板であってシリコン基
板, 4は金属層であってCu層, 5は合金層, 5aは厚さを減じた合金層 を表す。
FIG. 1 shows an embodiment. In the figure, 1 is a support side substrate and a silicon substrate, 1a is a support side substrate having a reduced thickness, 2 is an insulating layer and an SiO 2 film, and 3 is an element side substrate on which an element is formed and is a silicon substrate. The substrate, 4 is a metal layer and is a Cu layer, 5 is an alloy layer, and 5a is an alloy layer with reduced thickness.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】単結晶シリコンからなる支持側基板、絶縁
層、及び素子の形成された単結晶シリコン素子側基板か
らなるSOI構造基板の該支持側基板に、金属を拡散させ
て該支持側基板を合金化することを特徴とする半導体装
置の製造方法。
An SOI structure substrate comprising a support-side substrate made of single-crystal silicon, an insulating layer, and a single-crystal silicon device-side substrate on which elements are formed. And a method for manufacturing a semiconductor device.
JP1125102A 1989-05-18 1989-05-18 Method for manufacturing semiconductor device Expired - Lifetime JP2775848B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1125102A JP2775848B2 (en) 1989-05-18 1989-05-18 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1125102A JP2775848B2 (en) 1989-05-18 1989-05-18 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02303141A JPH02303141A (en) 1990-12-17
JP2775848B2 true JP2775848B2 (en) 1998-07-16

Family

ID=14901901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1125102A Expired - Lifetime JP2775848B2 (en) 1989-05-18 1989-05-18 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2775848B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4869546B2 (en) 2003-05-23 2012-02-08 ルネサスエレクトロニクス株式会社 Semiconductor device
WO2005059961A2 (en) * 2003-12-10 2005-06-30 The Regents Of The University Of California Low crosstalk substrate for mixed-signal integrated circuits

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60186036A (en) * 1984-03-05 1985-09-21 Nippon Telegr & Teleph Corp <Ntt> Semiconductor substrate and manufacture thereof

Also Published As

Publication number Publication date
JPH02303141A (en) 1990-12-17

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