JP2775066B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor integrated circuit device,
In particular, the present invention relates to a technique which is effective when used in a method of manufacturing a semiconductor integrated circuit device such as a one-chip microcomputer having a ROM (read only memory) in which a program is written.

[Conventional technology]

One-chip microcomputers that perform desired information processing in accordance with programs and data stored in a ROM are widely used. In order to easily perform verification (debugging) of a system using such a one-chip microcomputer, a ROM is more preferably a mask ROM (hereinafter simply referred to as an MROM) that writes storage information in a fixed manner during a manufacturing process. It is convenient to use an erasable and programmable read only memory (EPROM) that can be electrically written after production. EPROM is capable of electrically writing information and erasing information by irradiation with ultraviolet light. For this type of technology,
For example, there is JP-A-59-188234.

[Problems to be solved by the invention]

When the initial evaluation is completed and the program and data for controlling the microcomputer are determined, it is not necessary to use an EPROM as the storage element. The EPROM has a memory cell composed of a field effect transistor having a two-layer gate electrode structure of a control gate and a floating gate, so that the manufacturing process is complicated and the number of manufacturing steps is large.
Further, the EPROM requires a window for erasing ultraviolet light, which increases the manufacturing cost of the package, and in addition, requires a program to be written in each EPROM individually mounted, which increases the manufacturing time.

Therefore, as shown in FIG. 8, a semiconductor integrated circuit device LSI1 having a microcomputer on which the above-described EPROM is mounted.
When mass-producing semiconductor integrated circuit device LSI2 with the same function after system verification using
It can be replaced with ROM.

However, the circuit block that is performed when the EPROM is replaced with the MROM is only the ROM block, and the I / O
(Input / output circuit), TIM (timer circuit), ADC (analog / digital converter), DAC (digital / analog converter), CPU (microprocessor) and RAM
No consideration is given to changing other circuit blocks such as (random access memory), and it is even considered that it is desirable to form other circuits as they are from the viewpoint of system stability. Therefore, by replacing the EPROM with the MROM as described above, the manufacturing process can be simplified by forming the field effect transistor having the single-layer gate structure from the double-layer gate structure as described above, and the writing time can be reduced. You can only get the advantage. Hereinafter, in the present application, an insulated gate field effect transistor (IGFET) is abbreviated as MOSFET.

The present inventors have taken advantage of the fact that with the advancement of automatic design technology using a computer, it is possible to easily reduce the element size and change the layout under the same circuit.
At the time of replacement, the miniaturization of the chip size of the semiconductor integrated circuit device itself was considered.

An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device which has improved manufacturing efficiency.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
Using a first semiconductor integrated circuit device equipped with a circuit composed of a first nonvolatile memory element capable of electrically writing or writing and erasing, predetermined writing is performed on the nonvolatile memory element, The first semiconductor integrated circuit device is made operable by determining the stored information, and a circuit having substantially the same function as that of the first semiconductor integrated circuit device and including the nonvolatile memory element is manufactured in a manufacturing process. In forming a second semiconductor integrated circuit device having a circuit replaced with a storage element into which storage information is fixedly written, the chip size of the second semiconductor integrated circuit device is changed to the chip size of the first semiconductor integrated circuit device. Make it smaller.

[Action]

According to the above-described means, the number of chips (number of acquisitions) that can be formed on one semiconductor wafer increases, and the manufacturing efficiency of a semiconductor integrated circuit device such as a one-chip microcomputer can be increased.

Embodiment 1 FIG. 1 is a block diagram showing one embodiment of a two-chip microcomputer formed by a manufacturing method according to the present invention. Each circuit block in the figure is drawn in proportion to the actual geometric arrangement and size formed on the semiconductor substrate.

The semiconductor integrated circuit device LSI1 shown in FIG.
Is a one-chip microcomputer having, but not particularly limited to, the following circuit blocks. The CPU is a microprocessor (central processing unit). I / O is an input / output circuit for outputting address signals and transmitting / receiving data. ADC and DAC are analog / digital
A comparator and a digital-to-analog comparator. TIM is a timer circuit. RAM is random
An access memory, which is not particularly limited, is constituted by a static RAM, and is used for temporary storage of data and the like. The EPROM is an erasable & program ROM, and stores a program or the like as a data processing procedure by the microprocessor CPU. 1 above
The microcomputer of the chip is configured by connecting the respective circuit blocks of FIG. 1 to each other by a data bus, an address bus, and a control bus (not shown) centering on the microprocessor CPU.

The semiconductor integrated circuit device LSI is used at the time of system development. That is, when mounted on a specific electronic device, a program necessary for controlling the electronic device is written in the EPROM. This program verifies (debugs) the system. For example, not only the circuit is operated, but also various operation checks are performed under an environment suitable for the actual operating condition. Therefore, although not particularly limited, it is mounted on an actual pilot product and sent to the market, and a failure analysis of results used by various users is also performed. From these results, the EP that has been finally verified
When mass production is performed by directly replacing the contents of the ROM with the MROM, the semiconductor integrated circuit device LSI2 shown in FIG.
To reduce the chip size. That is, EPROM
Except for the part that replaces the part with MROM, the layout design technology of the semiconductor integrated circuit device using the graphic processing technology using a computer without substantial change of the circuit, and the reduction of each circuit block, accompanying the reduction The layout is changed and the arrangement of the blocks is changed.

The following table shows how to reduce the chip size.
It is shown in FIG. Table 1 shows the semiconductor integrated circuit device LSI1
2 shows a combination of the element dimensions and the change of the matching margin based on the EPROM in FIG.

Here, K1, K2> 1.

The first shrink method is based on the reduction of the element size as shown in the upper part of Table-1.

The MROM 1 reduces the planar size of elements in all circuit blocks constituting the semiconductor integrated circuit device LSI2. Here, the planar size of the element means, for example, the channel length and channel width of the MOSFET, the width of the element isolation region, the contact size, and the wiring pitch of the gate electrode or aluminum wiring. Such reduction of a graphic pattern itself can be easily realized by reducing a graphic by an automatic design technique using a computer. However, it is rare that each circuit block can be reduced at the same magnification as in the semiconductor integrated circuit devices LSI1 and LSI2 in FIG. Therefore, in each circuit block, the layout is changed by the possible reduction, and the layout is changed so that the whole can be efficiently fitted in the semiconductor chip. Since the layout design and arrangement of such circuit blocks are performed regularly, they can be easily performed by a circuit pattern automatic design technique using a computer. In the above MROM1, if the plane size of each element is reduced to 1 / K1, the size of a circuit block using this element is approximately 1 / K1.
Can be reduced to K1.

The second method of shrinking is based on the reduction of the alignment margin as shown in the lower part of Table-1.

The MROM2 reduces the alignment margin in the manufacturing process of all circuit blocks constituting the semiconductor integrated circuit device LSI2 to 1 / K2. Here, the following three methods are typical as means for reducing the alignment margin in the manufacturing process.

(1) Use an etching method and a manufacturing apparatus for reducing a dimensional shift after pattern formation with respect to a mask dimension. (2) Use a method and a manufacturing apparatus for improving alignment accuracy.

(3) Change the stepper from 1: 1 to 1: 5.

It is desirable to combine the above (1) to (3).

In the MROM3, the above two shrink methods are performed simultaneously. As a result, the chip size can be made smallest among the semiconductor integrated circuit devices LSI2 on which the three MROM1 to MROM3 are mounted.

When changing from an EPROM to an MROM, the EPROM requires a MROM like a writing circuit or a high-voltage circuit.
Then, by removing unnecessary circuits, MROM
It is needless to say that the size is reduced.
Similarly, of the circuit blocks and functions initially mounted as necessary in the semiconductor integrated circuit device LSI1,
It goes without saying that a circuit that is determined to be unnecessary in the system development process may be deleted.

2A to 2E show schematic manufacturing process diagrams of one embodiment of a method for manufacturing a semiconductor integrated circuit device according to the present invention.

Hereinafter, a method of reducing the element size will be described with reference to FIGS. 2A to 2E.

In FIG. 2A, the left side is a cross-sectional view of a main part of a nonvolatile memory element QME corresponding to the semiconductor integrated circuit device LSI1 equipped with an EPROM, a high voltage MOSFET QMH used for writing, and a MOSFETQL used for normal logic circuits such as reading. The right side shows a cross-sectional view of a main part of a storage element QMM corresponding to the semiconductor integrated circuit device LSI2 equipped with the MROM, and a MOSFETQL used for a normal logic circuit such as reading.

Needless to say, the MOSFET QL is also used as a MOSFET constituting another circuit block such as a CPU, a RAM or a TIM other than the EPROM and the MROM.

The nonvolatile memory element QME includes a first gate insulating film 4, a floating gate 5, a second gate insulating film 6, which are sequentially formed on the P-type semiconductor substrate 1 as described later, and a control formed integrally with the word line. The semiconductor device includes a gate 8 and a pair of N ⁺ -type semiconductor regions 9 formed on the surface of the semiconductor substrate 1 so as to sandwich the first gate insulating film 4 from both sides. The pair of semiconductor regions 9 function as a source and a drain.

The high-breakdown-voltage MOSFET QMH is formed on the surface of the semiconductor substrate 1 so as to sandwich the gate insulating film 4 and the gate electrode 5 and the gate insulating film 4 formed on the P-type semiconductor substrate 1 from both sides as described later. It is composed of a pair of formed N ⁺ type semiconductor regions 9. The gate insulating film 4 and the gate electrode 5 are formed in the same process as the first gate insulating film 4 and the floating gate 5 of the nonvolatile memory element QME, respectively. The pair of semiconductor regions 9 function as a source and a drain.

The MOSFETQL includes a gate insulating film 7 and a gate electrode 8 sequentially formed on the P-type semiconductor substrate 1 in the same manner as described above.
And a pair of N ⁺ -type semiconductor regions 9 formed on the surface of the semiconductor substrate 1 so as to sandwich the gate insulating film 7 from both sides.
It is composed of The gate electrode 8 is formed of the nonvolatile memory element
It is formed in the same step as the control gate 8 of QME.
The pair of semiconductor regions 9 function as a source and a drain.

Here, each element is separated by a field insulating film 2 having a large thickness and a P-type channel stopper 3 formed on a P-type substrate thereunder. Reference numeral 11 denotes a wiring (including a contact), and reference numeral 10 denotes an interlayer insulating film.

In FIG. 2A, the storage element QMM corresponding to the semiconductor integrated circuit device LSI2 equipped with the MROM shown on the right side has the same structure as the MOSFETQL used for ordinary logic circuits such as reading. That is, storage MOSFET QMM and MOSFE of logic circuit etc.
The TQL corresponds to the one in which the nonvolatile memory element QME, the high voltage MOSFET QMH and the logic MOSFET WQL of the semiconductor integrated circuit device LSI1 are replaced, and is formed sequentially on the P-type semiconductor substrate 1 in the same manner as described above. And a pair of N ⁺ -type semiconductor regions 9 formed on the surface of the semiconductor substrate 1 so as to sandwich the gate electrode 8 and the gate insulating film 7 ′ from both sides. Here, the high breakdown voltage MOSFET QMH used for writing to the EPROM is also used for a part of reading, so when it is replaced with the MROM, it has the same structure as the MOSFETQL for logic and the like.

In this semiconductor integrated circuit device LSI2, similarly to the case of the semiconductor integrated circuit device LSI1, each element has a thick field insulating film 2 and a P-type channel stopper 3.
Separated by Each element has an interlayer insulating film 10
, And the individual MOSFETs QMM and QL are appropriately connected by the wiring 11. Although not shown, the wiring 11 is covered with a passivation film.

The difference between the MOSFET QL of the semiconductor integrated circuit device LIS1 and the MOSFET QL of the LSI 2 is that in order to reduce the size of the semiconductor integrated circuit device LSI2, the MOSFET of the semiconductor integrated circuit device
The gate insulating film 7 'of QL is the MO of the semiconductor integrated circuit device LSI1.
It is thinner than the gate insulating film 7 of SFETQL. When the gate insulating film 7 'is formed thin as described above, the short channel effect is suppressed, and the gate size can be reduced. As a result, the element size of the MOSFET using such a thin gate insulating film 7 'is reduced, and the circuit block using such an element is reduced, so that the chip size of the semiconductor integrated circuit device LSI2 can be reduced. become.

For example, in FIG. 2A, the gate insulating film 7 and the gate dimensions of the MOSFETQL in the semiconductor integrated circuit device LSI1 with the EPROM mounted thereon are 25 nm and 1.2 μm, respectively.
When the ROM is mounted, by setting the gate insulating film 7 'to 20 nm, the gate size can be reduced to 1.0 μm.
Of course, it is needless to say that the overall chip size is reduced by reducing the wiring pitch of the wiring 11, the element isolation regions 2, 3, and the like.

Hereinafter, the manufacturing method will be specifically described with reference to FIGS. 2B to 2E. In the following description, in the semiconductor integrated circuit device LSI1 with the EPROM mounted and the semiconductor integrated circuit device LSI2 with the MROM mounted, the same process is performed once,
If different, each will be described.

In FIG. 2B, a thick field insulating film 2 is formed on one main surface of a P ⁻ type semiconductor substrate 1 by a selective oxidation method or the like. The P-type channel stopper 3 is formed in substantially the same process. Here, in the N-type well region for forming the P-channel MOSFET constituting the CMOS (complementary MOS) circuit, a well region is formed before this step. When the N-type substrate 1 is used, P
A channel MOSFET is formed, and an N-channel MOSFET constituting a CMOS circuit is formed in a P-type well region formed before this step.

In FIG. 2C, the first nonvolatile memory element QME of the EPROM
Gate insulating film 4 and floating gate 5, high voltage MOSF
The gate insulating film 4 and the gate electrode 5 are formed by ETQMH. The gate insulating film 4 is the insulating film 101 used when the thick field insulating film 2 is formed in FIG. 2B.
Is formed by thermal oxidation. The floating gate 5 of QME and the gate electrode 5 of QMH
Is formed by patterning after depositing polycrystalline silicon to reduce the resistance.

In FIG. 2D, gate insulating films 7 and 7 'of MOSFETQL and a gate electrode 8 are formed. Further, the second gate insulating film 6 and the control gate 8 of the nonvolatile memory element QME are formed in substantially the same step.

In the semiconductor integrated circuit device LSI1 equipped with EPROM,
After removing the first gate insulating film 4 on the P ⁻ type semiconductor substrate 1, a new gate insulating film 7 and a second gate insulating film 6 of QME are newly formed at the same time. The gate insulating film 7 and the second
The gate insulating film 6 is formed by a thermal oxidation method. The gate insulating film 7 and the second gate insulating film 6 may be formed in separate steps.

In the semiconductor integrated circuit device LSI2 on which the MROM is mounted, the gate insulating film 7 'is formed by a thermal oxidation method after removing the insulating film 101 used when forming the thick field insulating film 2. The gate insulating film 7 'is formed under the condition that the gate insulating film 7' is thinner than the gate insulating film 7 of the MOSFETQL of the semiconductor integrated circuit device LSI1 as described above.

Thereafter, the gate electrode 8 is formed by depositing the second polycrystalline silicon to reduce the resistance and then patterning.
In the nonvolatile memory element QME constituting the EPROM, the floating gate 4, the second gate insulating film 6, and the control gate 8 are simultaneously patterned. The patterning of the gate electrode 8 of the MOSFETQL on the side of the semiconductor integrated circuit device LSI2 on which the MROM is mounted is performed so as to be thinner than the gate electrode 8 of the semiconductor integrated circuit device LSI1 on which the EPROM is mounted as described above. The gate electrode 8 is formed of not only the above-described polycrystalline silicon but also a high-melting-point metal such as tungsten or a silicide thereof, or a laminated structure in which a high-melting-point metal such as tungsten or a silicide is provided on polycrystalline silicon. It may be something.

In FIG. 2E, an N ⁺ type semiconductor region 9 constituting a source and a drain is formed. These semiconductor regions 9
Is not particularly limited, but arsenic As
Is formed by injecting about 5 × 10 ¹⁵ (1 / cm ² ).

Thereafter, by forming the interlayer insulating film 10, the wiring 11, and a passivation film (not shown), the semiconductor integrated circuit devices LSI1 and LSI2 are completed on the semiconductor wafer. Here, the semiconductor integrated circuit device LS on which the MROM is mounted
The size of the wiring 11 on the I2 side is formed smaller than the wiring 11 on the side of the semiconductor integrated circuit device LSI1 on which the EPROM is mounted.

Storage element QMM formed in semiconductor integrated circuit device LSI2
The following method is used to change the threshold voltage for storing the same information as the corresponding nonvolatile memory element QME.

(1) The film pressure of the gate insulating film 7 'is changed. For example, the process is performed depending on the presence or absence of the field insulating film 2 having a large thickness.

(2) Before forming the gate electrode 8, an impurity is implanted for changing the threshold value. This can be done by ion implantation.

(3) After the gate electrode 8 is formed, impurity implantation for changing the threshold value is performed. This can be done by ion implantation. In this case, the impurity may be implanted in any of the steps after forming the gate electrode, after forming the interlayer insulating film 10, and after forming the wiring 11.

The writing of the storage information of the MROM may be configured by the presence or absence of the connection of the storage element QM to the bit line (data line or digit line) in addition to the above-described change of the threshold value. That is, by selecting a word line corresponding to the storage element QMM, whether a current path is substantially formed between the bit line and the ground potential of the circuit is made to correspond to the logic “1” and the logic “0”. Anything should do.

The operational effects obtained from the above embodiment are as follows. That is, (1) a microcomputer equipped with an EPROM is
When replacing a microcomputer with a microcomputer, the gate dimensions of the MOSFET can be reduced by configuring the thickness of the gate insulating film of the MOSFET that constitutes the individual circuit blocks that make up the microcomputer, and the wiring width can be reduced. The chip size of a microcomputer equipped with an MROM can be reduced. This gives 1
The effect of increasing the number of semiconductor chips formed by one semiconductor wafer and increasing the manufacturing efficiency is obtained.

(2) The microcomputer equipped with the above MROM is
Since the circuit configuration is the same except for the part where the EPROM is changed to the MROM, the layout change and the accompanying mask formation for reducing the chip size can be easily performed by an automatic design technique using a computer. The effect is obtained.

(3) MO that constitutes individual circuit blocks of the microcomputer when replaced with MROM with EPROM mounted
Since the basic element structure of the SFET is the same, and since the MROM and the other circuit blocks can have the same structure, the manufacturing process can be simplified.

(4) According to the above (1) to (3), an effect is obtained that the cost of the microcomputer mounted with the MROM which is mass-produced can be significantly reduced.

[Embodiment 2] Fig. 3 is a schematic sectional view of the element structure for explaining another embodiment of the present invention. In the following embodiments, a high breakdown voltage MOSFET QMH in which a semiconductor integrated circuit device equipped with an EPROM is formed is omitted because it is the same as the previous embodiment. Similarly to the above, the elements of the semiconductor integrated circuit device LSI1 equipped with the EPROM are shown on the left side, and the elements of the semiconductor integrated circuit device LSI2 equipped with the MROM are shown on the right side.

In FIG. 3, the source and the drain of the MOSFET QL are the low-concentration N ⁻ type semiconductor regions 103 formed below the side walls 104.
And a high-concentration N ⁺ type semiconductor region 9.

Also in this embodiment, the nonvolatile memory element QME is
In the case of the MOSFET QL, the thickness of the gate insulating film 7 ′ is reduced and the gate dimension is reduced. Then, the storage element QMM has the same structure as the MOSFETQL of the logic circuit. Also, the nonvolatile memory element QME constituting the EPROM
Also has an LDD structure as described above. However, low concentration of N
The concentration of the semiconductor region 102 is determined by the N ^- type semiconductor region of the MOSFETQL.
It is formed higher than 103, generates a lot of hot carriers, and increases the writing speed of the EPROM.

The method for forming the LDD structure according to the present embodiment will be briefly described as follows.

First, the N-type semiconductor region 102 contains 1 × 10 ¹⁵ (1 / c
m ²⁾ is formed by the extent implantation, N ^- -type semiconductor region 103 is formed by further ^{1 × 10 13 (1 / cm} 2 phosphorus P) extent implantation.

In this embodiment, since the element has the LDD structure, the short channel effect can be suppressed as compared with the MOSFET having the single drain structure as in the embodiment of FIG. 2A and the like. it can.
As a result, an effect is obtained that the chip size of the semiconductor integrated circuit device LSI2 on which the MROM constituted by these MOSFETs QL is mounted can be further reduced.

[Embodiment 3] Figs. 4 to 6 are schematic cross-sectional views of the element structure for explaining still another embodiment of the present invention.

In this embodiment, the element structure is changed in addition to forming the gate insulating film 7 'thinner to reduce the element size.

In the embodiment shown in FIG. 4, a semiconductor integrated circuit device LSI1 having an EPROM uses a single drain structure MOSFET, whereas a semiconductor integrated circuit device LSI2 having an MROM uses an LDD structure MOSFET. It is. As a result, the MOSFET having the single drain structure can be
By changing to OSFET, the ratio of the reduction ratio can be increased. In other words, the size ratio of the semiconductor integrated circuit device LSI2 to the semiconductor integrated circuit device LSI1 can be further reduced.

In the embodiment of FIG. 5, similarly to the above, the MOSFET constituting the semiconductor integrated circuit device LSI1 on which the EPROM is mounted has a single-ended structure, and the semiconductor integrated circuit device LSI2 on which the MROM is mounted has a low concentration of the N ⁻ type semiconductor region 105. And high concentration of N ⁺
MOSFET with double-drain structure composed of semiconductor region 9
Has been changed to. The N ⁻ type semiconductor region 105 is formed by implanting about 1 × 10 ¹³ (1 / cm ² ) of boron B by an ion implantation method. The N ⁻ type semiconductor region 105 is formed before or after the N ⁺ type semiconductor region 9 is formed.

In the embodiment of FIG. 6, the same way the MOSFET constituting the semiconductor integrated circuit device LSI1 mounting the EPROM as a single-ended structure, a low concentration in the semiconductor integrated circuit device LSI2 mounting the MROM N ^- -type semiconductor region 103 LDD MOSFET with P-type punch-through stopper area 106 underneath
Has been changed to. P-type punch-through stopper area 10
6 is an ion implantation method, and boron B is 1 × 10 ¹³ (1 / cm ² )
It is formed by implantation to a certain degree. The P-type punch-through stopper region 106 is formed before or after the N ⁻ type semiconductor region 103 is formed.

According to the above embodiment, the following operation and effect can be obtained in addition to the effects of the above embodiment.

When forming a semiconductor integrated circuit device LSI2 such as a microcomputer in which the EPROM was replaced by an MROM, not only the gate insulating film of the MOSFET was made thinner, but also the source and drain structures were changed, and the EPROM was mounted. As compared with the case, the short channel effect can be further suppressed, so that the effect that the chip size accompanying the reduction of the gate size can be further reduced can be obtained.

[Embodiment 4] Fig. 7 is a schematic sectional view of the element structure for explaining still another embodiment of the present invention. In this embodiment, in addition to a MOSFET, a resistor R
And a capacitor C are also shown. Such a resistor R and a capacitor C are used for an analog / digital converter ADC.
Alternatively, it is used when configuring an analog circuit such as a digital-to-analog converter DAC or an operational amplifier circuit.
As a result, the one-chip microcomputer of this embodiment can be used for a device that processes analog signals, such as an audio device or a car.

In the figure, the resistor R is formed in the same layer as the floating gate 5 of the EPROM, and the capacitor C is formed in the same layer as the floating gate 5, the first gate insulating film 6, and the control gate 8. Thus, the resistor R and the capacitor C can be formed by using the step of forming the nonvolatile memory element QME, and it is necessary to add a special step to form these elements R and C.

In this embodiment, a semiconductor integrated circuit device equipped with an MROM
When forming LSI2, QME with Q
Change to MM. In this case, the gate insulating film 7 'of the QMM and the QL of the semiconductor integrated circuit device LSI2 is formed to be thinner than the gate insulating film 7 of the MOSFETQL of the semiconductor integrated circuit device LSI1, and Gate dimensions are reduced. At this time, a semiconductor integrated circuit device equipped with an MROM
The first gate insulating film 6 ', which is a dielectric film of the capacitor C formed in the LSI 2, is formed to be thinner than the first gate insulating film 6 formed in the semiconductor integrated circuit device LSI1, and obtains the same capacitance. Area is reduced. Note that the insulating film as the dielectric of the capacitor C may have the same thickness.

The method of manufacturing each element in this embodiment is the same as that of the embodiment shown in FIGS. 2B to 2E, and a detailed description thereof will be omitted.

According to this embodiment, even when the EPROM of a semiconductor integrated circuit device such as a microcomputer equipped with an EPROM having a resistor and a capacitor using a two-layer gate electrode structure is replaced with an MROM, the semiconductor integrated circuit such as a microcomputer is also used. Since the size of the MOSFETs constituting the device can be reduced, the chip size of a semiconductor integrated circuit device such as a microcomputer equipped with an MROM can be reduced accordingly.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it can be variously changed without departing from the gist of the invention. not. For example, an EEPROM may be used instead of the EPROM. Thus EE
When a PROM is used, it is not necessary to form an erasing window in the package. The EPROM and the EEPROM may be used to store a program or data of a microcomputer, or may constitute a PLA (programmable logic array) storing a microprogram or the like. The MROM may be a vertical ROM other than a horizontal ROM corresponding to an EPROM or an EEPROM. The above EP
When replacing the ROM or the EEPROM with the MROM, the MOSFET having the single drain structure may be changed to the MOSFET having the double drain structure equipped with the MROM, and further, the MOSFET having the LDD structure may be changed. The field insulating film may be formed by a selective oxidation method in a semiconductor integrated circuit device equipped with an EPROM, and may be changed to a trellis isolation structure in a semiconductor integrated circuit device equipped with an MROM. The wiring layer has a one-layer wiring structure in a semiconductor integrated circuit device equipped with an EPROM, and a semiconductor integrated circuit device equipped with an MROM has a multi-layer wiring structure of two or more layers. It may promote the conversion.

INDUSTRIAL APPLICABILITY The present invention can be widely used for various types of semiconductor integrated circuit devices whose operations and functions are performed in accordance with information written in a ROM, in addition to a microcomputer.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the first semiconductor integrated circuit device equipped with an EPROM or an EEPROM is used, predetermined writing is performed on the nonvolatile storage element, desired storage information is determined, and the first storage device is determined.
Of the above-mentioned EPROM or E
In forming the second semiconductor integrated circuit device having substantially the same function by replacing the EPROM with the MROM, the chip size of the second semiconductor integrated circuit device must be smaller than the chip size of the first semiconductor integrated circuit device. Accordingly, the number of chips (number of acquisitions) that can be formed on one semiconductor wafer increases, and the manufacturing efficiency can be increased.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a structure formed by a manufacturing method according to the present invention.
FIG. 2A to FIG. 2E are schematic manufacturing process diagrams for explaining an embodiment of a method of manufacturing a semiconductor integrated circuit device according to the present invention. FIG. 3 is a schematic cross-sectional view of an element structure for explaining another embodiment of the present invention, and FIGS. 4 to 6 are schematic elements for explaining still another embodiment of the present invention. FIG. 7 is a schematic sectional view of an element structure for explaining still another embodiment of the present invention, and FIG. 8 is a block diagram of a microcomputer showing an example of the prior art. LSI1, LSI2 ... Semiconductor integrated circuit device, CPU ... Microprocessor, ADC ... Analog-to-digital converter, DAC ... Digital-to-analog converter, I / O ...
… I / O circuit, TIM… Timer circuit, RAM… Random access memory, EPROM… Erasable & program read only memory, MROM… Mask type read only memory, QME… Nonvolatile storage Element, Q
MM: memory element, QMH: high voltage MOSFET, QL: logic circuit MOSFET, R: resistor, C: capacitor 1: P ^- substrate, 2: field insulating film, 3: channel stopper, 4 First gate insulating film, 5 Floating gate, 6, 6 'Second gate insulating film, 7,
7 ': gate insulating film, 8: control gate, 9
... N ⁺ type semiconductor region, 10 ... interlayer insulating film, 11 ... wiring, 101 ... insulating film, 102 ... N type semiconductor region, 103 ...
N ^- type semiconductor region, 104 side wall, 105 N ^- type semiconductor region, 106 P-type punch-through stopper region

Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/112 29/788 29/792 (72) Inventor Masaru Iwabuchi 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Musashi, Hitachi, Ltd. In the factory (56) References JP-A-2-262363 (JP, A) JP-A-62-190767 (JP, A) JP-A-2-19771 (JP, A) (58) Fields investigated (Int. . ^6, DB name) H01L 21/82 H01L 27/04 H01L 27/10 - 27/115 H01L 29/788 - 29/792

Claims (5)

(57) [Claims] A step of forming a first semiconductor integrated circuit device on which a circuit comprising a first nonvolatile memory element capable of electrically writing or writable and erasable is mounted; A process of performing predetermined writing, determining desired storage information and enabling the first semiconductor integrated circuit device, wherein the non-volatile storage device has substantially the same function as the first semiconductor integrated circuit device. A circuit consisting of elements
In forming a second semiconductor integrated circuit device having a circuit replaced with a storage element to which storage information is fixedly written in a manufacturing process, the chip size of the second semiconductor integrated circuit device is changed to the first semiconductor integrated circuit device. A process for reducing the size of the semiconductor integrated circuit device from the chip size. 2. The means for reducing the chip size of the second semiconductor integrated circuit device from the chip size of the first semiconductor integrated circuit device is achieved by an automatic design technique using a computer. 2. The method according to claim 1, wherein the method is performed by reducing the size of the wiring by reducing the wiring width, and by changing the shape and arrangement of the circuit function block accompanying the reduction. 3. The manufacturing of a semiconductor integrated circuit device according to claim 1, wherein said reduction in element size includes reducing the thickness of a gate insulating film of a MOSFET. Method. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said reducing the element size includes reducing the gate electrode width of the MOSFET. 5. A circuit comprising a nonvolatile memory element has a stacked gate structure having a control gate and a floating gate, and stores an electric charge in the floating gate to perform a storage operation. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said EEPROM is an EEPROM which performs a storage operation by accumulating charges in trap levels in a film.