JP2774580B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a field-effect transistor in which a heterojunction is formed using a new compound semiconductor.

(Prior Art) An element using SiC has attracted attention as an element which operates at a higher temperature and has a higher breakdown voltage than a conventional semiconductor active element using Si or GaAlAs. However, when SiC is used, an excellent gate insulating film such as a SiO ₂ film in the case of Si cannot be obtained, and it is difficult to form an insulated gate field effect transistor. In addition, it is impossible to change the band gap while maintaining lattice matching.
It is difficult to form a device having a heterojunction such as MT. Therefore, a high-performance transistor cannot be manufactured.

(Problems to be Solved by the Invention) There has been no transistor which can operate at a high temperature and has high performance characteristics due to a heterojunction.

The present invention has been made in view of such a point, and an object of the present invention is to provide a field-effect transistor having a heterojunction and capable of operating at a high temperature.

[Structure of the Invention] (Means for Solving the Problems) The field effect transistor according to the present invention has, for example, a stacked structure of a BP layer and a Ga _1-x Al _x N (0 ≦ x ≦ 1) layer as a heterojunction. And a gate electrode and source / drain electrodes disposed with the gate electrode interposed therebetween. That is, the field effect transistor of this example is
By using a heterojunction between the BP layer and the Ga _1-x Al _x N layer, the conductivity of the BP layer is controlled by using a portion near the heterojunction interface as a channel region.

(For work) Ga _1-x Al _x N has a normal wurtzite crystal structure, would not lattice-matched to the BP with zinc blende type crystal structure. However, according to the experiments of the present inventors, the BP layer and Ga _1-x Al _x
When an N layer is formed by lamination, Ga _1-x
It has been found that the Al _x N layer has a zinc-blende type crystal structure and a heterojunction with good lattice matching can be obtained. Therefore, according to the present invention, a heterojunction of a Ga _1-x Al _x N layer having a wide band gap close to an insulator and a BP layer having a band gap of about twice as large as that of Si makes it possible to form two Can form a channel in a three-dimensional electron gas state,
Excellent transistor characteristics can be obtained by controlling the channel conductivity by the gate. This heterojunction consists of GaAs and Al
Since the band gap difference is much larger than that of the GaAs heterojunction, the carrier concentration of the channel can be increased even if the impurity doping amount is small, so that a low on-resistance can be obtained. The material system of the present invention can operate at high temperatures because of its wide band gap, and can provide an element that can be used in a high-temperature region, which was impossible with a conventional element.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a field effect transistor according to the first embodiment. Using a semi-insulating (100) GaP substrate 1, a 1 μm undoped GaP layer 2 is formed thereon as a buffer layer,
An undoped BP layer 3 and an n-type Ga _1-x Al _x N layer 4 are sequentially formed thereon. n-type Ga _1-x Al _x N layer 4 is, for example, Si 10 ¹⁷ /
It is doped with about cm ³ to 10 ¹⁸ / cm ³ . n-type Ga _1-x Al
_{On the xN} layer 4, n is formed as a contact layer with the gate region interposed therebetween.
Type BP layer 5 is formed, and the n-type
A gate electrode 6 is formed on the Ga _1-x Al _x N layer 4, and a source electrode 7 and a drain electrode 8 are formed on the BP layer 5. The gate electrode 6 is, for example, an Au electrode, and is Ga _1-x Al _x N
A Schottky junction is formed with the layer 4. The source electrode 7 and the drain electrode 8 are ohmic electrodes made of Au / AuGe. Each semiconductor layer on the substrate is MO
It is formed by a CVD method.

With such a configuration, the n-type Ga _1-x Al _x N layer 4 and the BP layer 3
The electrons of the n-type Ga _1-x Al _x N layer 4 exude to the heterojunction interface of the BP layer 3 to form a channel in a two-dimensional electron gas state. By controlling the conductivity of this channel by the gate electrode, a field effect transistor characteristic can be obtained.

FIG. 2 shows static characteristics of the field effect transistor according to this embodiment. The transconductance g _m = 10 ms / mm obtained with device dimensions of a gate length of 5 μm and a gate width of 200 μm. The drain withstand voltage was about 100V. It was confirmed that these characteristics were almost constant up to a high temperature of 200 ° C. or higher.

MOCV used for forming each semiconductor layer of the device of the example below
The method D will be described.

FIG. 7 shows a multi-chamber type metal organic chemical vapor deposition (MOCVD) apparatus used for manufacturing a device. In the figure, 11,
Numerals 12 and 13 denote reaction tubes made of quartz, and necessary raw material gases are taken in from gas introduction ports located above the respective reaction tubes.
These reaction tubes 11, 12 and 13 are vertically mounted in one chamber 14 through the upper lid. The substrate 15 is placed on a graphite susceptor 16, and each reaction tube 11, 12,
13 and is heated to a high temperature by an external high-frequency coil 17. The susceptor 16 is attached to a quartz holder 18 and can be moved at a high speed below each of the reaction tubes 11, 12, and 13 by a drive shaft via a magnetic fluid seal. Driving is performed by a computer-controlled motor installed outside. A thermocouple 20 is placed at the center of the susceptor, monitors the temperature immediately below the substrate, and takes it out. The cord portion uses a slip ring to prevent twisting due to rotation. The reaction gas is extruded by a fast down-flow of hydrogen gas from the upper jet port 21 and is exhausted from the exhaust port 22 by a rotary pump while the mutual mixing is suppressed as much as possible.

With such a MOCVD apparatus, a desired source gas is flowed through each of the reaction tubes 11, 12, and 13, and a substrate 15 is moved by a motor controlled by a computer, so that an arbitrary lamination period and an arbitrary composition are provided on the substrate 15. To produce a multilayer structure. In this method, a sharp concentration change that cannot be obtained by the gas switching method can be easily realized. Also in this method,
Since it is not necessary to switch the gas at a high speed in order to form a steep hetero interface, the problem that the decomposition rate of NH ₃ or PH ₃ as a raw material gas is slow can be solved by setting the gas flow rate low.

Using this MOCVD apparatus, an element wafer specifically shown in FIG. 1 was produced. The source gases used were methyl organic metal trimethylgallium (TMG), trimethylaluminum (TMA), trimethylboron (TEB), and ammonia (NH
₃ ) and phosphine (PH ₃ ). Substrate temperature is 850 ~ 115
The gas flow rate was set so that the temperature was 0 ° C., the pressure was 0.3 atm, the total flow rate of the raw material gas was 1 / min, and the growth rate was 1 μm / h. The specific flow rate of each raw material gas is 1 × 10 ^-6 mol / m in TEB.
In, TMG is 1 × 10 ⁻⁶ mol / min, TMA is 1 × 1006 mol / min, PH ₃ is 5 × 10 ⁻⁴ mol / min, and NH ₃ is 1 × 10 ⁻³ mol / min. Silane (SiH ₄ ) was used as a doping material.

Next, some other embodiments of the present invention will be described. In the following embodiments, portions corresponding to FIG. 1 are denoted by the same reference numerals as in FIG. 1, and detailed description is omitted.

FIG. 3 shows a field effect transistor according to a second embodiment of the present invention. The field effect transistor of this embodiment is an n-type Ga _1-x A which is a carrier supply layer in the embodiment of FIG.
The l _x N layer 4 is replaced by an undoped Ga _1-x Al _x N layer 41 and an n-type Ga
_It has a laminated structure of _1-x Al _x N layers. Except for this point, it is the same as the embodiment of FIG.

Even when the Ga _1-x Al _x N layer on the channel layer is partially doped with impurities as in this embodiment, the same transistor characteristics as those of the first embodiment can be obtained, and the same effects can be obtained. .

FIG. 4 shows a field effect transistor according to a third embodiment of the present invention. In this embodiment, the channel layer is an n-type BP layer 31 doped with an impurity, and an undoped layer is formed thereon.
A Ga _1-x Al _x N layer 43 is laminated. The structure of this embodiment is
Unlike the first embodiment, it can be said that the Ga _1-x Al _x N layer 43 does not function as a carrier supply layer but functions as a gate insulating film.

FIG. 5 shows a field effect transistor according to a fourth embodiment of the present invention. In this embodiment, the portion where the channel region below the n-type Ga _1-x Al _x N layer 4 is formed is also the n-type BP layer 31 with respect to the embodiment of FIG.

As described above, by appropriately doping the channel region with an impurity as necessary, the threshold voltage can be appropriately set, and a low on-resistance can be obtained.

FIG. 6 shows a field effect transistor according to a fifth embodiment of the present invention. In this embodiment, a recess is formed in the gate region with respect to the device structure shown in FIG.

With the introduction of such a recess structure, the resistance between the gate and the source can be reduced, and the performance of the field effect transistor can be improved. A similar recess structure can be applied to the device of the embodiment shown in FIGS.

The present invention is not limited to the above embodiment. For example, in the example, the Ga _1-x Al _x N layer was used in a portion below the gate electrode, but this portion was a superlattice layer in which a BP layer and a Ga _1-x Al _x N layer were alternately stacked. Can also. This contributes to stabilization of the crystal structure of this portion. In addition, Ga _x Al _y
A mixed crystal layer of B _1-xy N _{x + y} P _1-xy (0 ≦ x, y ≦ 1) can also be used. In addition, a small amount of
Al, Ga, N, etc. may be doped, or the BP layer and Ga _1-x Al
_xN layers are alternately laminated to form a superlattice layer, Ga _x Al _y B
It is also possible to form a mixed crystal layer of _1-xy N _{x + y} P _1-xy (0 ≦ x, y ≦ 1). When a superlattice layer is used, the Ga _1-x Al _x N layer and the B
By appropriately selecting the thickness ratio of the P layer or the composition x, and using a mixed crystal layer of Ga _x Al _y B _1-xy N _{x + y} P _1-xy (0 ≦ x, y ≦ 1) The band gap can be changed by changing the composition, for example, the B composition.

Further, in the embodiment, Si is used as the n-type impurity, but Se, Sn, S, Te and the like can be used. When forming a field-effect transistor using holes as carriers, Mg is doped as a p-type impurity, or Zn, B
e, Cd or the like may be doped. In the embodiment, the active layer is always doped with an impurity. However, the carrier may be generated at an appropriate concentration without actively doping the impurity, and the present invention is applicable to the case where the entire active layer is undoped. It is valid.

MOCVD raw materials include triethyl gallium (TEG) as a Ga raw material, and triethyl aluminum (TEG) as an Al raw material.
A) and B raw materials such as trimethyl boron (TMB) and diborane (B ₂
H _6), or the like can be used. In addition to ammonia, hydrazine (N ₂ H ₄ ), Ga (C ₂ H ₅ ) ₃ .NH ₃ , Ga
An organometallic compound called an adduct such as (CH ₃ ) ₃ · N · (CH ₃ ) ₃ can be used. When Mg is used as a doping material, cyclopentadienyl magnesium (Cp ₂ Mg) or Mg (thd) 2 (2,2,6,6, -Tetram
ethyl-3,5-Heptanedion Magnesium).

Further, in addition to GaP, SiC, BP, or Si can be used as the substrate.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a field-effect transistor capable of operating at a high temperature and having a heterojunction interface formed using a new compound semiconductor material.

[Brief description of the drawings]

FIG. 1 is a diagram showing a field effect transistor according to a first embodiment of the present invention, FIG. 2 is a diagram showing its voltage-current characteristics, and FIG. 3 is a diagram showing a field effect transistor according to a second embodiment of the present invention. FIG. 4 is a view showing a field-effect transistor according to a third embodiment of the present invention. FIG. 5 is a view showing a field-effect transistor according to a fourth embodiment of the present invention. FIG. 7 is a view showing a field-effect transistor according to a fifth embodiment. FIG. 7 is a view showing an MOCVD apparatus used for manufacturing the transistor of the present invention. 1 ... Semi-insulating GaP substrate, 2 ... Undoped GaP layer (buffer layer), 3 ... Undoped BP layer (channel layer), 4 ...
... n-type Ga _1-x Al _x N layer (carrier supply layer), 5 ... n-type BP
Layer (contact layer), 6: gate electrode, 7: source electrode, 8: drain electrode, 41: undoped Ga _1-x Al _x
N layer, 42: n-type Ga _1-x Al _x N layer, 43: undoped Ga _1-x A
l _x N layer, 31 ... n-type BP layer.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-49275 (JP, A) JP-A-60-92663 (JP, A) Journal of the Japanese Association for Crystal Growth, 13 [4] (1986), p. 218-225 Journal of Applied Physics, 53 [10] (1982) 6844-6848 (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095-27/098 H01L 29/775-29/778 H01L 29/80-29 / 812

Claims (6)

(57) [Claims] An underlying semiconductor region, a Ga _1-x Al _x N (0 ≦ x ≦ 1) layer forming a heterojunction with the underlying semiconductor region,
A gate electrode provided on the Ga _1-x Al _x N layer;
A field effect transistor provided on a _1-x Al _x N layer, comprising source and drain electrodes sandwiching the gate electrode. 2. The field effect transistor according to claim 1, wherein said base semiconductor region is a semiconductor region on which a BP layer is formed. 3. The field effect transistor according to claim 2, wherein said Ga _1-x Al _x N layer is at least partially doped with impurities, and said BP layer is not doped with impurities. 4. The field effect transistor according to claim 2, wherein said BP layer is at least partially doped with impurities, and said Ga _1-x Al _x N layer is not doped with impurities. 5. The field effect transistor according to claim 2, wherein the Ga _1-x Al _x N layer and the BP layer are both doped with impurities. 6. The field effect transistor according to claim 1, wherein said gate electrode is a Schottky gate electrode.