JP2770580B2 - Method for manufacturing semiconductor element isolation region - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor element isolation region.

[0002]

2. Description of the Related Art High integration and high performance of semiconductor devices have been achieved by miniaturizing semiconductor devices. At the same time, miniaturization of an element isolation region for electrically isolating each element is indispensable for high integration.

[0003] Conventionally, a silicon semiconductor element is separated by an LO.
The COS method has been used. However, LOCOS separation has a limit in miniaturization. That is, there are problems that the isolation region is expanded by bird's beak, a narrow channel effect is caused by lateral diffusion of boron as a channel stopper, and a deep isolation region cannot be formed. On the other hand, the trench isolation is a structure suitable for fine element isolation because a deep and narrow isolation region can be formed. However, leakage current due to inversion of the trench side surface and electric field concentration at the corner has become a problem. .

The applicant of the present invention has proposed a device isolation structure and a manufacturing method for solving these problems in Japanese Patent Application No. 1-1260067 filed on May 19, 1999. The structure is shown in FIG.
As shown in FIG. 5, an insulating film isolation pattern composed of a silicon oxide film 19, a CVD silicon oxide film 21, and a silicon nitride film 20 provided on a P-type silicon substrate 11, and a width smaller than the isolation pattern width under the region. Silicon oxide film 1
9 and a silicon nitride film 20 having a groove buried with an insulator.

FIGS. 8 to 12 show a method of forming this structure.
As shown in (1), a part of the silicon oxide film 12 to be an element isolation region in the silicon oxide film 12 formed on the P-type silicon substrate 11 is removed using a resist 13 pattern formed by a lithography process as a mask. .
[FIG. 8] Next, after depositing the CVD silicon oxide film 14, a boron diffusion layer 15 serving as a channel stopper is formed (FIG. 9).

Next, a CVD silicon oxide film 16 is deposited (FIG. 10), and the CVD silicon oxide film 16 and the CVD silicon oxide film 14 are etched by using the RIE technique.
After leaving the CVD silicon oxide films 14 and 16 at the end of the opened silicon oxide film 12, a groove 17 is provided in the exposed silicon substrate 11, and a boron diffusion layer 18 serving as a channel stopper is formed at the bottom of the groove 17 [FIG. 11].

Next, after the silicon oxide films 12, 14 and 16 are removed, a thin silicon oxide film 19 is formed by a thermal oxidation method, a silicon nitride film 20 is deposited by a CVD method, An oxide film 21 is deposited. [FIG. 12].

Next, using a resist 22 pattern formed by a lithography process as a mask, the CVD silicon oxide film 21, the silicon nitride film 20, and the silicon oxide film 19 are etched to form an element isolation region covering the groove 17 on the silicon substrate. 11 (FIG. 7).

[0009]

According to the above-mentioned manufacturing method, after a groove pattern is formed once, an insulating film pattern serving as an isolation region is formed again by a lithography step, so that misalignment occurs. As a result, when the isolation pattern covering the upper portion of the groove becomes asymmetric or the element isolation region becomes finer, the isolation pattern may not cover the lower groove pattern.

[0010]

According to the manufacturing method of the present invention, a region where a device isolation is to be formed is opened in a sacrificial film deposited on the surface of a semiconductor substrate, and a first insulating film of a different material is formed on a side wall of the opened sacrificial film. Forming a groove in the exposed semiconductor substrate, embedding a second insulating film in the groove and an opening region above the groove, and selectively removing the sacrificial film. The above problem has been solved.

[0011]

According to the method of manufacturing a semiconductor device of the present invention, an isolation region is formed in a single lithography step, and the size of the protruding width of the element isolation region that covers the trench is formed. Is determined by the thickness of the insulating film deposited on the side wall of the sacrificial film. As a result, even when miniaturized, the trench buried with the insulating film and the separation pattern covering the trench become symmetric.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings showing the manufacturing steps in order.

FIGS. 1 to 6 are sectional views showing a manufacturing method for forming an element isolation region on a P-type silicon substrate according to this embodiment. A silicon oxide film 2 is formed on the surface of a P-type silicon substrate 1 by thermal oxidation, and then a silicon nitride film 3 is deposited by a CVD method. A pattern of the resist 4 is formed using lithography technology, and the silicon nitride film 3 is reactive ion-etched (RI
E) Removal by method. Next, when a boron diffusion layer 5 serving as a channel stopper is formed on the surface of the silicon substrate opened by ion implantation, the structure shown in FIG. 1 is obtained.

Next, when a CVD silicon oxide film 6 is deposited, the structure shown in FIG. 2 is obtained.

Next, the CVD silicon oxide film 6 is etched back by the RIE method to leave the CVD silicon oxide film 6 only on the side wall of the silicon nitride film 3, exposing the surface of the P-type silicon substrate 1. A trench 7 is formed in the P-type silicon substrate 1 using the silicon nitride film 3 and the CVD silicon oxide film left on the side walls as a mask. After a silicon oxide film 8 is formed on the groove surface by thermal oxidation, a boron diffusion layer 9 serving as a channel stopper is formed at the bottom of the groove 6 by ion implantation, as shown in FIG.

Next, a CVD silicon oxide film 10 is deposited and the trench 7 and the opened area are buried, as shown in FIG.

Next, when the surface of the silicon nitride film 3 is exposed by etching back the CVD silicon oxide film 10, FIG.
Becomes Next, the silicon nitride film 3 is selectively removed, and the silicon oxide film 2 existing on the silicon nitride film 3 is removed.
The element isolation region having the structure shown in FIG.

In this embodiment, the silicon nitride film is used as the sacrificial film. However, the present invention is not limited to this. A film made of a material that can be selectively removed from the silicon oxide film, such as a polycrystalline silicon film, may be used. . In this embodiment, the method for forming and forming the isolation region on the P-type silicon substrate has been described. However, the isolation region may be formed on an N-type substrate or on a substrate having both conductive regions.

[0019]

According to the structure of the present invention, only one lithography step is required for forming the element isolation region. Further, even if the size is reduced, the groove buried with the insulating film and the separation pattern covering the groove are symmetric.

[Brief description of the drawings]

FIG. 1 is a sectional view in the order of steps for explaining one embodiment of the present invention.

FIG. 2 is a cross-sectional view in the order of steps for explaining one embodiment of the present invention.

FIG. 3 is a cross-sectional view in the order of steps for explaining one embodiment of the present invention.

FIG. 4 is a sectional view in order of process for explaining one embodiment of the present invention.

FIG. 5 is a sectional view in order of process for explaining one embodiment of the present invention.

FIG. 6 is a cross-sectional view in the order of steps for explaining one embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a conventional element isolation structure.

8A to 8C are cross-sectional views in a process order for explaining a conventional method for manufacturing an element isolation region.

FIG. 9 is a sectional view in order of process for explaining a conventional method for manufacturing an element isolation region.

FIG. 10 is a sectional view in order of process for explaining a conventional method for manufacturing an element isolation region.

FIG. 11 is a process sectional view for explaining a conventional method for manufacturing an element isolation region.

FIG. 12 is a sectional view in order of process for explaining a conventional method for manufacturing an element isolation region.

[Explanation of symbols]

 1,11 P-type silicon substrate 2,8,12,19 Silicon oxide film 3,20 Silicon nitride film 4,13,22 Resist 5,9,15,18 Boron diffusion layer 6,10,14,16,21 CVD silicon Oxide film 7, 17 groove

Claims (1)

(57) [Claims] Forming a first insulating film of a different material on a side wall of the opened sacrificial film, wherein the first semiconductor film is made of a different material; Forming a groove in a substrate, embedding a second insulating film in the groove and the opening region thereon, and selectively removing the sacrificial film. Production method.