JP2770398B2 - Method of forming contact hole - Google Patents
Method of forming contact holeInfo
- Publication number
- JP2770398B2 JP2770398B2 JP9336789A JP9336789A JP2770398B2 JP 2770398 B2 JP2770398 B2 JP 2770398B2 JP 9336789 A JP9336789 A JP 9336789A JP 9336789 A JP9336789 A JP 9336789A JP 2770398 B2 JP2770398 B2 JP 2770398B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- sog
- forming
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 claims description 15
- 230000001681 protective effect Effects 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 description 13
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 229910004298 SiO 2 Inorganic materials 0.000 description 10
- 239000010410 layer Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- -1 ammonia peroxide Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は、コンタクトホールの形成方法に関し、更に
詳しくは、SOG(Spin on Glass)を積層した絶縁膜への
コンタクトホールの形成に係るものである。Description: TECHNICAL FIELD The present invention relates to a method for forming a contact hole, and more particularly, to a method for forming a contact hole in an insulating film in which SOG (Spin on Glass) is laminated. is there.
[発明の概要] この発明は、コンタクトホールの形成方法において、 層間絶縁膜上にSOG膜を形成し、該SOG膜に開口部を形
成し、該開口部の側壁に保護膜を形成し、次いで前記絶
縁膜に開口部を形成することにより、 コンタクトホール周壁に損傷が発生するのを防止して
信頼性の高い配線層を形成することができるようにした
ものである。[Summary of the Invention] The present invention provides a method of forming a contact hole, comprising: forming an SOG film on an interlayer insulating film, forming an opening in the SOG film, forming a protective film on a side wall of the opening, By forming an opening in the insulating film, damage to the peripheral wall of the contact hole is prevented, and a highly reliable wiring layer can be formed.
[従来の技術] 近年、半導体装置の高集積化に伴い、層間絶縁膜を平
坦化する技術が必要となっている。この技術の一つとし
てSOGを用いる平坦化方法が知られている。このSOGを用
いた半導体装置におけるコンタクトホールの形成方法と
しては、例えば第2図に示すように、先ず、シリコン基
板1上に、層間絶縁膜であるSiO2膜2をCVD法により形
成し、次に、SOG膜3を形成し、さらに、SiO2でなる絶
縁膜4をCVD法により形成し、その後、絶縁膜4上にレ
ジストマスクを形成して、このレジストマスクをマスク
として異方性エッチングを行なってコンタクトホールを
形成する。そして、このようにして露出したシリコン基
板1上の自然酸化膜(SiO2)を除去するために、エッチ
ング液(希フッ酸溶液等)を用いてライトエッチングを
行なった後アルミニウム等の配線材料をコンタクトホー
ル内に埋込み、配線5を形成している。[Prior Art] In recent years, as semiconductor devices become more highly integrated, a technique for flattening an interlayer insulating film is required. As one of the techniques, a planarization method using SOG is known. As a method for forming a contact hole in a semiconductor device using this SOG, for example, as shown in FIG. 2, first, an SiO 2 film 2 as an interlayer insulating film is formed on a silicon substrate 1 by a CVD method. Next, an SOG film 3 is formed, and an insulating film 4 made of SiO 2 is formed by a CVD method. Thereafter, a resist mask is formed on the insulating film 4, and anisotropic etching is performed using the resist mask as a mask. To form contact holes. Then, in order to remove the natural oxide film (SiO 2 ) on the silicon substrate 1 exposed in this manner, light etching is performed using an etching solution (dilute hydrofluoric acid solution or the like), and then a wiring material such as aluminum is removed. The wiring 5 is formed by being buried in the contact hole.
また、第4図に示す従来例は、フォトリソグラフィ技
術の限界以下の小径なコンタクトホールを形成するよう
に工夫されたものであって、基板6の上に被エッチング
体7を形成し、この被エッチング体7の上に第1のマス
ク層8を形成し、この第1のマスク層8の開口内周壁に
第2のマスク層9を形成して、これらマスク層8,9をマ
スクとして異方性エッチングを行ないコンタクトホール
を形成しようというものである(特開昭63-110728号公
報参照)。The conventional example shown in FIG. 4 is devised so as to form a contact hole having a diameter smaller than the limit of the photolithography technology. A first mask layer 8 is formed on the etching body 7, a second mask layer 9 is formed on the inner peripheral wall of the opening of the first mask layer 8, and anisotropically using these mask layers 8, 9 as a mask. In this method, a contact hole is formed by performing reactive etching (see Japanese Patent Application Laid-Open No. 63-110728).
[発明が解決しようとする課題] しかしながら、上記したような二つの従来例にあって
は、以下に述べるような問題点を有している。[Problems to be Solved by the Invention] However, the above two conventional examples have the following problems.
即ち、前者にあっては、ライトエッチングを行なう
と、第2図に示すように、コンタクトホールに面するSO
G膜3はSiO2に比べてエッチレートが大きいため浸食さ
れて後退し空隙3aが生じたり、第3図に示すように、SO
G膜3の上下の層との間にはがれ(図は上層のはがれを
示している)3bを生じたりして半導体装置の信頼性を著
しく損なう問題点がある。That is, in the former, when light etching is performed, as shown in FIG.
Since the G film 3 has a higher etch rate than SiO 2 , it is eroded and receded to form voids 3 a, and as shown in FIG.
There is a problem that the reliability (removal) of the semiconductor device is remarkably impaired due to the occurrence of peeling 3b between the upper and lower layers of the G film 3 (the upper layer is shown in the figure).
また、後者において基板6がシリコンから成り、被エ
ッチング体7がSOGで成るものとすると、被エッチング
体7の異方性エッチングの後に上記したようなライトエ
ッチングを行なった場合、第5図に示すように、やはり
空隙7aが生じる問題点があた。Assuming that the substrate 6 is made of silicon and the object 7 to be etched is made of SOG in the latter case, the light etching as described above is performed after the anisotropic etching of the object 7 to be etched, as shown in FIG. As described above, there is still a problem that the void 7a is generated.
[課題を解決するための手段] そこで、本発明は、層間絶縁膜上にSOG膜を形成し、
該SOG膜に開口部を形成し、該開口部の側壁に保護膜を
形成し、次いで前記絶縁膜に開口部を形成することを、
その解決手段としている。[Means for Solving the Problems] Accordingly, the present invention provides a method of forming an SOG film on an interlayer insulating film,
Forming an opening in the SOG film, forming a protective film on a side wall of the opening, and then forming an opening in the insulating film;
This is the solution.
[作用] SOG膜に形成した開口部の側壁には保護膜が形成され
るため、例えばライトエッチングが行なわれた場合、SO
G膜に損傷等が生ずるのを防止する。また、層間絶縁膜
に開口部を形成する場合、保護膜がコンタクトホール
(開口部)の小径化に寄与し、例えばリソグラフィ技術
における解像限界以下の小さなコンタクトホールの形成
を可能にする。[Operation] Since a protective film is formed on the side wall of the opening formed in the SOG film, for example, when light etching is performed, SO
Prevents the G film from being damaged. In the case where an opening is formed in the interlayer insulating film, the protective film contributes to the reduction of the diameter of the contact hole (opening), and enables the formation of a contact hole smaller than the resolution limit in lithography, for example.
[実施例] 以下、本発明に係るコンタクトホールの形成方法の詳
細を図面に示す実施例に基づいて説明する。なお、本実
施例においては、例えば半導体層中の拡散層や、ソース
・ドレイン電極や、LOCOS分離膜等の説明は省略する。EXAMPLES Hereinafter, details of a method for forming a contact hole according to the present invention will be described based on examples shown in the drawings. In the present embodiment, description of, for example, a diffusion layer in a semiconductor layer, source / drain electrodes, a LOCOS separation film, and the like will be omitted.
先ず、本実施例においては、シリコン基板10の上に、
SiO2絶縁膜11をCVD法によって形成し、さらに、SiO2絶
縁膜11上に反応性イオンエッチング時にSOGと選択比が
とれる窒化シリコン(SiN)膜12を堆積させる。上記し
たSiO2絶縁膜11と窒化シリコン膜12とは、層間絶縁膜を
構成する。First, in this embodiment, on the silicon substrate 10,
An SiO 2 insulating film 11 is formed by a CVD method, and a silicon nitride (SiN) film 12 having a selectivity with SOG at the time of reactive ion etching is deposited on the SiO 2 insulating film 11. The above-mentioned SiO 2 insulating film 11 and silicon nitride film 12 constitute an interlayer insulating film.
次に、窒化シリコン膜12の上にSOGを塗布して平坦化
を行ないSOG膜13を形成し、さらに、層間膜であるPSG
(リンシリケートガラス)膜14を堆積させる。Next, SOG is applied on the silicon nitride film 12 to perform planarization to form an SOG film 13, and furthermore, PSG which is an interlayer film is formed.
(Phosphosilicate glass) film 14 is deposited.
さらに、PSG膜14の上には、SOG及び窒化シリコン(Si
N)に対して、反応性イオンエッチング時に選択比のと
れる窒化チタン(TiN)膜15を堆積させる(第1図
A)。Further, on the PSG film 14, SOG and silicon nitride (Si
N), a titanium nitride (TiN) film 15 having a selectivity at the time of reactive ion etching is deposited (FIG. 1A).
次いで、フォトリソグラフィ法を用いて設計値よりや
や大きめのレジストマスク(図示省略する)を配し、こ
れをマスクとして反応性イオンエッチングを行なって開
口部を形成してゆき、第1図Bに示すように窒化シリコ
ン膜12が露呈した時点でエッチングを止める。Next, a resist mask (not shown) slightly larger than the designed value is provided by using a photolithography method, and an opening is formed by performing reactive ion etching using this as a mask, as shown in FIG. 1B. The etching is stopped when the silicon nitride film 12 is exposed as described above.
次に、窒化シリコンを、第1図C中破線で示すよう
に、CVD法により、全面に堆積させた後、エッチバック
を行なって、開口部の側壁に上記窒化シリコンで成る保
護膜16を形成する(第1図C)。Next, as shown by a broken line in FIG. 1C, after depositing silicon nitride on the entire surface by the CVD method, the silicon nitride is etched back to form the protective film 16 made of the silicon nitride on the side wall of the opening. (FIG. 1C).
最後に、保護膜16をマスクとして反応性イオンエッチ
ングを行ない、SiO2絶縁膜11に開口部を形成して、シリ
コン基板10上にコンタクトホール17が完成する(第1図
D)。Finally, reactive ion etching is performed using the protective film 16 as a mask, an opening is formed in the SiO 2 insulating film 11, and a contact hole 17 is completed on the silicon substrate 10 (FIG. 1D).
なお、本実施例において窒化チタン膜15を形成した理
由は、保護膜16を形成した後、反応性イオンエッチング
を行なうと、もしPSG膜14が露出しているとするとこの
膜14もエッチングされてしまうため、これを防止するた
めである。The reason for forming the titanium nitride film 15 in the present embodiment is that, after forming the protective film 16 and performing reactive ion etching, if the PSG film 14 is exposed, this film 14 is also etched. This is to prevent this.
また、コンクタクト開口後窒化チタン膜15は、不要で
あればアンモニア過水等でエッチングすることも可能で
ある。In addition, the titanium nitride film 15 after the contact opening can be etched with ammonia peroxide if necessary.
而して、完成したコンタクトホール17に配線の埋込み
を行なう前に、シリコン基板10表面の自然酸化膜の除去
に供されるライトエッチングを行なっても、SOG膜13は
露出していないため、浸食による後退やはがれが生じる
不都合が無い。Thus, even if the light etching for removing the natural oxide film on the surface of the silicon substrate 10 is performed before embedding the wiring in the completed contact hole 17, the SOG film 13 is not exposed, There is no inconvenience that retreat and peeling occur due to.
以上、実施例について説明したが、本発明は、これに
限らず、各種の半導体装置の製造プロセスに適用可能で
あり、上記実施例のような材料,構造に限定されるもの
ではない。要は、SOG膜による平坦化の前に、SOGと選択
比が十分にある材料膜が予め形成されたものであればよ
く、しかも前記材料膜と同種又はSiO2と選択比のある材
料を、用いて保護膜を形成し、層間膜の最上層にはSi
O2,SiNと選択比のとれる材料を堆積させるものであれば
よい。Although the embodiments have been described above, the present invention is not limited to this, but can be applied to various semiconductor device manufacturing processes, and is not limited to the materials and structures as in the above embodiments. In short, before the planarization by the SOG film, a material film having a sufficient selectivity with SOG may be formed in advance, and a material having the same type as the material film or a selectivity with SiO 2 may be used. A protective film is formed using
What is necessary is just to deposit a material having a selectivity with O 2 and SiN.
[発明の効果] 以上の説明から明らかなように、本発明に係るコンタ
クトホールの形成方法においては、SOG膜の露出が防止
され、反応性イオンエッチングなどの異方性エッチング
によるSOG膜の損傷は勿論のこと、ライトエッチングに
よるSOG膜の損傷(浸食,界面劣化等)を防止して、信
頼性の高いコンタクト部の形成が出来る効果がある。[Effects of the Invention] As is clear from the above description, in the method for forming a contact hole according to the present invention, exposure of the SOG film is prevented, and damage to the SOG film due to anisotropic etching such as reactive ion etching is prevented. Needless to say, there is an effect that the SOG film can be prevented from being damaged (erosion, interface deterioration, etc.) by light etching, and a highly reliable contact portion can be formed.
また、本発明は、保護膜形成により、フォトリソグラ
フィ技術における解像限界以下の微細なコンタクトホー
ルの形成を可能にする効果がある。Further, the present invention has an effect of forming a fine contact hole having a resolution equal to or less than the resolution limit in the photolithography technology by forming the protective film.
第1図A〜第1図Dは本発明に係るコンタクトホール形
成方法の実施例の工程図、第2図〜第5図は従来例を示
す断面図である。 11……SiO2絶縁膜、12……窒化シリコン膜、13……SOG
膜、14……PSG膜、15……窒化チタン膜、16……保護
膜。1A to 1D are process diagrams of an embodiment of a contact hole forming method according to the present invention, and FIGS. 2 to 5 are cross-sectional views showing a conventional example. 11 ... SiO 2 insulating film, 12 ... Silicon nitride film, 13 ... SOG
Film, 14 PSG film, 15 Titanium nitride film, 16 Protective film.
Claims (1)
開口部を形成し、該開口部の側壁に保護膜を形成し、次
いで前記絶縁膜に開口部を形成することを特徴とするコ
ンタクトホールの形成方法。An SOG film is formed on an interlayer insulating film, an opening is formed in the SOG film, a protective film is formed on a side wall of the opening, and then an opening is formed in the insulating film. Characteristic method of forming contact holes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9336789A JP2770398B2 (en) | 1989-04-13 | 1989-04-13 | Method of forming contact hole |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9336789A JP2770398B2 (en) | 1989-04-13 | 1989-04-13 | Method of forming contact hole |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02271646A JPH02271646A (en) | 1990-11-06 |
JP2770398B2 true JP2770398B2 (en) | 1998-07-02 |
Family
ID=14080324
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9336789A Expired - Fee Related JP2770398B2 (en) | 1989-04-13 | 1989-04-13 | Method of forming contact hole |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2770398B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3638711B2 (en) | 1996-04-22 | 2005-04-13 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
-
1989
- 1989-04-13 JP JP9336789A patent/JP2770398B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH02271646A (en) | 1990-11-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5470793A (en) | Method of via formation for the multilevel interconnect integrated circuits | |
KR100510558B1 (en) | Method for forming pattern | |
US6184142B1 (en) | Process for low k organic dielectric film etch | |
US6171951B1 (en) | Dual damascene method comprising ion implanting to densify dielectric layer and forming a hard mask layer with a tapered opening | |
US20010014525A1 (en) | Process for forming trenches and contacts during the formation of a semiconductor memory device | |
JPH079934B2 (en) | Method for manufacturing semiconductor device | |
US5663108A (en) | Optimized metal pillar via process | |
JP3214475B2 (en) | Method of forming dual damascene wiring | |
US6028363A (en) | Vertical via/contact | |
US6924172B2 (en) | Method of forming a bond pad | |
JP3267199B2 (en) | Method for manufacturing semiconductor device | |
US5427982A (en) | Method for fabricating a semiconductor device | |
JP2770398B2 (en) | Method of forming contact hole | |
US5877082A (en) | Method of manufacturing semiconductor device without plasma damage | |
US5077236A (en) | Method of making a pattern of tungsten interconnection | |
JP3897071B2 (en) | Manufacturing method of semiconductor device | |
US6060371A (en) | Process for forming a trench device isolation region on a semiconductor substrate | |
US6171938B1 (en) | Method for fabricating semiconductor device capable of minimizing damage of lower layer using insulating layer resided in opening | |
US20060019489A1 (en) | Method for forming storage node contact of semiconductor device | |
JP2590711B2 (en) | Method for manufacturing semiconductor device | |
US6281092B1 (en) | Method for manufacturing a metal-to-metal capacitor utilizing only one masking step | |
KR20010004803A (en) | Method for forming metal line of a semiconductor device | |
JPH10116903A (en) | Method for manufacturing semiconductor device | |
JPS6254427A (en) | Manufacture of semiconductor device | |
JPH02133924A (en) | Semiconductor device and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |