JP2769304B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a high quality liquid crystal display device having improved display quality by preventing display unevenness.

[0002]

2. Description of the Related Art A horizontal electric field type liquid crystal driving device for displaying an image on a liquid crystal display panel by applying an electric field parallel to a substrate surface between a pixel electrode and a common electrode to a liquid crystal is disclosed in -913.

FIG. 16 is a block diagram showing a schematic configuration of a driving circuit of a liquid crystal display device of a horizontal electric field type.

[0006] In FIG. 16, reference numeral 101 denotes a transverse electric field type T.
FT liquid crystal display panel (TFT-LCD), 1 is a gate drive circuit, 2 is a drain drive circuit, 10 is a timing controller (display control device), 3 is a common voltage generation drive circuit, 106 is a thin film transistor (TFT), 6 is a drain Signal line, 7 is a gate signal line, 5 is a common electrode signal line, 7
02 indicates a green pixel, 703 indicates a blue pixel, and 704 indicates a red pixel.

In the liquid crystal display device of the horizontal electric field type shown in FIG. 16, a plurality of pixels are provided in a matrix, and each of the plurality of pixels is provided with a plurality of thin film transistors (TFs).
T) 106 and the plurality of thin film transistors (TFT)
And a pixel electrode connected to the source electrode 106.

The drain electrodes of the plurality of thin film transistors (TFTs) 106 in the column direction among the thin film transistors (TFTs) 106 provided in a matrix are connected to the same drain signal line 6, and the plurality of drain signal lines are connected. 6 is a TFT liquid crystal display panel (TFT-LCD) 10
At the top of 0, it is connected to the drain drive circuit 2.

The gate electrodes of a plurality of thin film transistors (TFTs) 106 arranged in a matrix in each row direction are connected to the same gate signal line 7, and the plurality of gate signal lines are connected to each other. 7
Is connected to the gate drive circuit 1 on one side surface of a TFT liquid crystal display panel (TFT-LCD) 100.

Further, a common electrode signal line 5 for applying a drive voltage to the common electrode is formed so as to face a plurality of pixel electrodes in a row direction among the pixels arranged in the matrix,
The other side of the TFT liquid crystal display panel (TFT-LCD) 100 is connected to the common voltage generation drive circuit 3.

In the in-plane switching mode liquid crystal display device shown in FIG.
0 based on the control signal input to the gate drive circuit 1
To turn on the thin film transistor (TFT) 106,
“OFF”, and the pixel (702) is output from the drain drive circuit 2.
To 704), a gradation voltage is applied.

In the lateral electric field type liquid crystal display device shown in FIG. 16, when a liquid crystal is sealed with a certain gap between two substrates, the two substrates are fixed at the edges by spacers. The gap is obtained.

[0011]

The in-plane switching mode liquid crystal display device also employs an alternating drive system for converting the voltage applied to the liquid crystal layer into an alternating current. There is an AC driving method in which a driving voltage applied to a liquid crystal layer is inverted.

When a pulse voltage is applied to a signal line having a resistor R and a capacitor C, distortion occurs in the pulse voltage.

FIG. 17 is a circuit diagram showing an equivalent circuit of a transmission path of a driving voltage applied to a common electrode in the in-plane switching mode liquid crystal display device shown in FIG. 16, and FIG.
FIG. 18 is a diagram illustrating a waveform of a drive voltage at each point illustrated in FIG. 17.

In the horizontal electric field type liquid crystal display device shown in FIG. 16, the transmission path of the driving voltage applied to the common electrode is provided with the resistance 5 of the common electrode signal line 5 as shown in FIG.
0, the resistance 51 of the common electrode wiring between the common voltage generation drive circuit 3 and the common electrode signal line 5 and the pixel (702 to 70
4) There is a storage capacity 53 in.

Therefore, when the liquid crystal layer is driven by the AC drive voltage, the resistance of the common electrode signal line 5 and the resistance of the common electrode wiring between the common voltage generation drive circuit 3 and the common electrode signal line 5 are reduced. The waveform of the drive voltage (pulse voltage) supplied to the common electrode from the common voltage drive circuit 52 in the common voltage generation drive circuit 3 is caused by the storage capacitor 53 in the pixel (702 to 704).

A pixel common voltage waveform 5 at a point D shown in FIG.
4. As can be seen from the pixel common voltage waveform 55 at point E, the pixel common voltage waveform 56 at point F, and the pixel common voltage waveform 57 at point G, the waveform distortion of the drive voltage supplied to this common electrode is:
It becomes larger as it becomes the far end with point D, point E, point F and point G.

As a result, the electric field between the pixel electrode and the common electrode in each pixel is different, and uneven brightness (uneven display) occurs along the common electrode signal line 5, thereby reducing the display quality of the liquid crystal display panel. There was a problem of being damaged.

In particular, this has been a serious problem when an alternating drive system in which the drive voltage applied to the liquid crystal layer is inverted for each line is employed.

Further, when the common electrode signal line 5 is broken even in one place, the driving voltage cannot be supplied to the common electrode of the pixel after the broken place, so that the liquid crystal cannot be driven. There is a problem that the display quality of the image is deteriorated.

Furthermore, in the configuration according to the conventional technique, the difference between the lead-out part and the non-lead-out part of the drain signal line 6 and the gate signal line 7 is the same as the thickness of the signal line. There is a problem that the display quality of the liquid crystal display panel is impaired.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a liquid crystal display device having good viewing angle characteristics and improving display quality. To provide technology.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0023]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, a typical one will be briefly described as follows.
It is as follows.

[0024] (1) a pair of substrates, a plurality of active elements wherein each formed on one display area on the substrate, wherein formed on one substrate of a plurality which are respectively connected to the plurality of active elements A pixel electrode, a plurality of scan electrodes formed in the row direction on the one substrate and applying a scan voltage to each active element in the row direction, and a plurality of scan electrodes formed in the column direction on the one substrate and arranged in the column direction. A plurality of signal electrodes for applying a signal voltage to the active element,
A plurality of common electrodes formed on the one substrate in the row direction and applying an electric field substantially parallel to the substrate surface to the liquid crystal layer between the respective pixel electrodes in the row direction, and sandwiched between the pair of substrates; A liquid crystal layer, a scanning electrode driving unit for driving the scanning electrode, a signal electrode driving unit for driving the signal electrode, and a common electrode driving unit for driving the common electrode. Arranged in rows
A common electrode signal line connected to each common electrode
Each of the common electrode signal lines arranged in the column direction has both ends.
Part is formed by the common electrode wiring formed outside the display area.
And the common electrode wiring is connected to the common electrode.
It is characterized by having a lower resistance than the polar signal line .

(2) In the means (1), a dummy line having the same material and the same thickness as the common electrode wiring is provided in the non-display area on the one substrate.

(3) In the means of (1) or (2), a portion other than an intersection between the common electrode wiring and the scanning electrode or the signal electrode and a connecting portion between the common electrode wiring and the common electrode are used. In a non-intersecting portion, a thickness adjusting film having the same material and the same thickness as the scanning electrode is provided above or below the common electrode wiring.

(4) In the above-mentioned means (1) or (2), a portion other than an intersection between the common electrode wiring and the scanning electrode or the signal electrode and a connecting portion between the common electrode wiring and the common electrode are provided. In the non-intersecting portion, a film thickness adjustment film having the same material and the same thickness as the signal electrode is provided above or below the common electrode wiring.

[0028]

According to the means (1), both ends of the common electrode signal line are connected to the common electrode wiring and the resistance of the common electrode wiring is made smaller than the resistance of the common electrode signal line. It is possible to reduce the waveform distortion of the driving voltage of the common electrode supplied from the voltage driving circuit, the electric field strength between the pixel electrode and the common electrode in each pixel becomes nearly uniform in the panel, and the common electrode signal It is possible to reduce uneven brightness occurring along the line.

Further, even if one common electrode signal line is broken in the middle, a common voltage can be supplied from both ends of the common electrode signal line and the liquid crystal of each pixel can be driven. It is possible to prevent the display quality from being impaired due to the inability to drive the liquid crystal of the previous pixel from the location.

Further, by forming the cross-sectional structure of the region where the common electrode wiring is provided to be the same as the cross-section of the intersection of the common electrode wiring and the gate signal line or the drain signal line, the common electrode wiring is formed. The unevenness of the film thickness at the edge of the substrate can be reduced, whereby the gap length between the two substrates can be made constant, and the unevenness of the gap of the liquid crystal display device can be reduced.

[0031]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, parts having identical functions are given same symbols and their repeated explanation is omitted.

Embodiment 1 FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display device according to an embodiment (Embodiment 1) of the present invention.

In the liquid crystal display device of this embodiment, a matrix substrate 8 having pixels 12 arranged in a matrix, a counter substrate 9, a timing controller 10, a drain drive circuit 2, a gate drive circuit 1, a common voltage generation drive circuit 3, It is composed of liquid crystal (not shown) sealed between the matrix substrate 8 and the counter substrate 9.

The matrix substrate 8 has pixels 12
A drain signal line 6 and a gate signal line 7 for supplying a driving voltage necessary for driving the pixel 12 are arranged orthogonal to each other so as to surround the pixel 12, and the drain signal line 6 is connected to the drain drive circuit 2 to The lines 7 are each connected to the gate drive circuit 1.

Further, a common electrode signal line 5 connected to a common electrode in the pixel 12 is arranged in parallel with the gate signal line 7, and the common electrode signal line 5 is connected at both ends of the common electrode signal line 5. It is connected to the common voltage generation drive circuit 3 via the power supply.

The gate drive circuit 1 and the drain drive circuit 2 are connected to a timing controller 10.

The timing controller 10 receives a video signal and a timing signal from an external video signal source 11, generates a drive voltage corresponding to the video signal by the drain drive circuit 2, and supplies the drive voltage to the drain signal line 6 according to the timing signal. I do.

The gate drive circuit 1 takes in the video signal and the timing signal supplied from the timing controller 10, generates a drive voltage corresponding to the video signal, and supplies it to the gate signal line 7 according to the timing signal.

As a result, it becomes possible to sequentially apply the drain voltage according to the video signal to the pixels 12 in the matrix substrate 8.

In this embodiment, the common electrode signal line 5
Are connected to the common electrode wiring 4 at both ends.

At this time, since the common electrode wiring 4 is formed in the non-display area of the matrix substrate 8, the wiring width of the common electrode wiring 4 can be widened. It can be smaller than the resistance value of the electrode signal line 5.

FIG. 2 is a circuit diagram showing an equivalent circuit of a transmission path of the drive voltage applied to the common electrode in the liquid crystal display device of the present embodiment. FIG. 3 is a circuit diagram showing the drive voltage at each point shown in FIG. It is a figure which shows the waveform of.

Since the resistance 59 of the common electrode wiring 4 is smaller than the resistance 58 of the common electrode signal line 5, the resistance D shown in FIG.
Common voltage drive circuit 60 at points E, F, and G
The voltage waveform of the common electrode driving voltage supplied from FIG.
D point pixel common voltage 62, E point pixel common voltage 63,
The F point pixel common voltage 64 and the G point pixel common voltage 65 are used.

According to the present embodiment, as can be seen from FIG. 3, the common voltage drive circuit 60 in the common voltage generation drive circuit 3
, The waveform distortion of the drive voltage supplied to the common electrode is reduced.

Therefore, the electric field strength between the pixel electrode and the common electrode in each pixel 12 becomes nearly uniform in the panel,
It is possible to reduce uneven brightness generated along the common electrode signal line 5.

Further, even if the common electrode signal line 5 is disconnected in the middle, a driving voltage can be supplied to the common electrode from both ends of the common electrode signal line 5, and the pixel 12 which is located beyond the disconnection point as in the conventional example.
It is possible to prevent the display quality from being impaired due to the inability to supply the driving voltage to the common electrode and the inability to drive the liquid crystal.

FIG. 4 is a diagram showing an equivalent circuit of the pixel 12 shown in FIG.

Next, the configuration of the pixel 12 will be described with reference to FIG.

The pixel 12 is a thin film transistor (TFT)
24, a pixel electrode 25, a common electrode 27, a storage capacitor 21, and a liquid crystal 20 between the pixel electrode 25 and the common electrode 27.

The gate electrode 26 of the thin film transistor 24,
The drain electrode 13 and the source electrode 14 are respectively
The gate signal line 17, the drain signal line 15, and the pixel electrode 25 are connected.

The common electrode 27 is connected to the common electrode signal line 16.
And a storage capacitor 21 is formed between the common electrode 27 and the pixel electrode 25. In addition, the liquid crystal 20 sealed between the matrix substrate 8 and the counter substrate 9 is
It is arranged between the common electrode 27 and the pixel electrode 25.

The gate signal line 17 and the drain signal line 15, and the common electrode signal line 16 and the drain signal line 1
5 at the intersection of gate and drain
8 and a common-drain cross capacitance 19 are formed.

In the thin film transistor 24, a parasitic capacitance (Cgs) 23 and a parasitic capacitance (Cgd) 22 are formed.

FIG. 5A is a plan view of the pixel 12 formed on the matrix substrate 8, and FIG.
It is sectional drawing which shows the cross section cut | disconnected by the LL 'line of (a).

As shown in FIGS. 5A and 5B, a gate electrode 30 and a common electrode 32 are
For example, it is formed using aluminum 38.

Further, the gate signal line 31 and the common electrode signal line 36 are formed at the same time, and the gate electrode 30 and the gate signal line 31 and the common electrode 32 and the common electrode signal line 36 are formed.
Are electrically connected to each other.

Next, after the aluminum oxide 39 is formed by using anodic oxidation, the gate oxide film 40 is formed of, for example, silicon nitride or the like.

Then, the gate electrode 3 of the gate oxide film 40 is formed.
For example, a semiconductor layer 44 made of hydrogenated amorphous silicon is formed in a portion opposing 0, and an ohmic layer 45a made of N-type hydrogenated amorphous silicon electrically separated from each other is formed on the semiconductor layer 44. 45b
Is provided.

Next, the source electrode 29 and the drain electrode 2
8, the pixel electrode 37 and the drain signal line 33 are simultaneously formed of, for example, two layers of chromium 41 and aluminum 42, and the source electrode 29 and the pixel electrode 35, and the drain electrode 28 and the drain signal line 33 are respectively electrically connected. Connection.

At this time, for example, there are three common electrodes 32,
The pixel electrode 37 has two comb teeth, and the comb teeth are alternately arranged at equal intervals and substantially in parallel with the drain signal line 33.
2

At the intersection of the common electrode 32 and the pixel electrode 37, a storage capacitor 35 is formed via a gate insulating film 40.

Further, a protective film 43 made of silicon nitride or the like and a polyimide-based alignment film 46 are formed.

In this embodiment, the amorphous silicon thin film transistor 24 is used as an active element. However, a polysilicon thin film transistor, a MOS transistor on a silicon wafer, or an MIM (Me
It is also possible to use a two-terminal element such as a tal-intrinsic-metal diode.

The material of each electrode and signal line is not particularly limited, but a metal having a high anticorrosive property is preferable in consideration of corrosion at a connection terminal portion with a drive circuit.

Although one thin film transistor is used in this embodiment, two or more thin film transistors may be formed for redundancy.

In this embodiment, the number of the comb teeth of the common electrode 32 and the number of the comb teeth of the pixel electrode 37 are three and two, respectively. However, it is desirable that the number is small in consideration of the aperture ratio and the like.

FIG. 6A is a plan view of the connection between the common electrode signal line and the common electrode wiring at point A of the matrix substrate 8 shown in FIG.

FIG. 6B is a diagram showing the I-I of FIG.
FIG. 6C is a cross-sectional view showing a cross section cut along line I ′, and FIG.
FIG. 7 is a cross-sectional view showing a cross section cut along the line HH ′ in FIG.

At the point A shown in FIG. 1, after the gate signal line 31 and the common electrode signal line 36 are formed on the matrix substrate 8 by using aluminum 38,
Aluminum oxide 39 is formed on the signal line.

At this time, the terminal of the common electrode signal line 36 is
A resist is used in advance to prevent the aluminum oxide 39 from being formed.

Next, a gate oxide film 40 is formed. At this time, a contact hole 48 is formed on the terminal portion of the common electrode signal line 36.

Next, chromium 41 and aluminum 43
Using the layer, the drain signal line 33 and the common electrode wiring 47 are formed simultaneously.

The common electrode wiring 47 is also formed on the end of the common electrode signal line 36, and the common electrode wiring 47 and the common electrode signal line 36 are electrically connected by the contact hole 48 at the end of the common electrode signal line 36. Connecting.

Finally, a protective film 43 is formed, and a surface treatment is performed.

FIG. 7A is a plan view of a connection portion between the common electrode signal line and the common electrode wiring at a point B of the matrix substrate 8 shown in FIG. 1, and FIG. 7B is a plan view of FIG.
It is sectional drawing which shows the cross section cut | disconnected by the JJ 'line of (a).

Aluminum 38 on the matrix substrate 8
To form a gate signal line 35, a common electrode signal line 36, and a common electrode wiring 47 at the same time, and then, using anodic oxidation, an aluminum oxide 39 is formed on the signal line,
Further, a gate oxide film 40 is formed on the aluminum oxide 39.
To form

At this time, a resist is used to prevent the aluminum oxide 39 and the gate oxide film 40 from being formed at the terminal portion of the common electrode signal line 36 and on the common electrode wiring 47 by using a resist before performing anodic oxidation. Keep it.

Next, chromium 41 and aluminum 42
A drain signal line 33 is formed using the layer, and chromium 41 and aluminum 42 are also formed on the common signal line 47 at the same time.

As a result, the common electrode wiring 47 is made of aluminum 38, chromium 41, and aluminum 42 and has a low resistance.

Finally, a protective film 43 is formed, and a surface treatment is performed.

FIG. 8A is a plan view of the intersection of the drain signal line and the common electrode line at point C of the matrix substrate 8 shown in FIG. 1, and FIG. 8B is a plan view of FIG.
It is sectional drawing which shows the cross section cut | disconnected by the KK 'line of (a).

Aluminum 38 on matrix substrate 8
After forming a gate signal line and a common electrode signal line 47 by using, the aluminum oxide 39 is formed on the signal line by using anodic oxidation.

After forming the gate oxide film 40, the drain signal line 33 is connected to chromium 41 and aluminum 4
2 is formed using two layers.

Finally, a protective film 43 is formed, and a surface treatment is performed.

In FIG. 6, the common electrode signal line 3
6 and the common electrode wiring 47 (contact hole 4
8) is formed in a region between the common electrode wiring 47 and the drain signal line 33, but is not necessarily limited to this. For example, as shown in FIG. It is also possible to form a contact hole 48 in a region opposite to the signal line 33.

FIG. 9A is a plan view of another example of the connection between the common electrode signal line and the common electrode wiring at point A of the matrix substrate 8 shown in FIG.

FIG. 9B is a graph showing the Q-value of FIG. 9A.
FIG. 9C is a cross-sectional view showing a cross section cut along the line Q ′, and FIG.
FIG. 10 is a cross-sectional view showing a cross section cut along the line RR ′ in FIG.

At the point A shown in FIG. 1, after the gate signal lines 31 and the common electrode signal lines 36 are formed on the matrix substrate 8 using aluminum 38,
Aluminum oxide 39 is formed on the signal line.

At this time, the terminal of the common electrode signal line 36 is
A resist is used in advance to prevent the aluminum oxide 39 from being formed.

Next, a gate oxide film 40 is formed. At this time, a contact hole 48 is formed on the terminal portion of the common electrode signal line 36.

Next, chromium 41 and aluminum 43
Using the layer, the drain signal line 33 and the common electrode wiring 47 are formed simultaneously.

The common electrode wiring 47 is also formed on the end of the common electrode signal line 36, and the common electrode wiring 47 and the common electrode signal line 36 are electrically connected by the contact hole 48 at the end of the common electrode signal line 36. Connecting.

Finally, a protective film 43 is formed and a surface treatment is performed.

In the example shown in FIG. 9, aluminum oxide 39 is provided at the intersection of common electrode signal line 36 and common electrode line 47.
Is formed.

In general, aluminum oxide 39 is also formed on gate signal line 31. Therefore, it is necessary to form a contact hole in a connection portion connecting gate signal line 31 and gate drive circuit 1. is there.

Then, in a portion where a contact hole is to be formed, aluminum oxide 3
9 is not formed.

In this case, in the example shown in FIG. 6, it is necessary to accurately form a resist for forming a contact hole 48 connecting the common electrode signal line 36 and the common electrode wiring 47.

However, in the example shown in FIG. 9, by forming a resist on the periphery of the matrix substrate 8 in a region opposite to the drain signal line 33 with respect to the common electrode wiring 47, the common electrode signal line 36 is formed. And common electrode wiring 47
And the contact hole connecting the gate signal line 31 and the gate drive circuit 1 can be formed together, and the precision of direct writing of resist can be reduced. Becomes possible.

As described above, the gate signal lines 31,
With the same material and the same manufacturing process as the drain signal line 33, the common electrode wiring 47 can be formed at the edge of the panel, and can be connected to both ends of the common electrode signal line 36.

FIGS. 10 and 11 are diagrams showing another example of the arrangement of the common electrode wiring in this embodiment.

The common electrode wiring 47 does not need to be routed to the entire panel edge as shown in FIG. 1, and the common electrode wiring 49 has the drain signal line 33 connected to the drain drive circuit 2 as shown in FIG. It is also possible to route around avoiding the area.

As a result, it is possible to reduce the cross parasitic capacitance generated at the intersection between the common electrode wiring 47 and the drain signal line 33.

As shown in FIG. 11, the common electrode wiring 47 is divided into a plurality of common electrode wirings 34a and 34b,
It is also possible to pull out from the panel and connect it in the peripheral drive circuit.

As a result, the length of the common electrode wiring in the panel can be reduced.

[Embodiment 2] The schematic configuration of the liquid crystal display device of Embodiment 2 is the same as that of the liquid crystal display device of Embodiment 1 described above.

Hereinafter, differences between the liquid crystal display device of the second embodiment and the first embodiment will be described.

FIG. 12A is a plan view of a connection portion between the common electrode signal line and the common electrode wiring at a point corresponding to the point A of the matrix substrate 8 shown in FIG. 1 in the liquid crystal display device of the second embodiment. It is.

FIG. 12B is a diagram showing the relationship between M and M in FIG.
FIG. 12 is a cross-sectional view showing a cross section cut along line -M ′,
FIG. 12C is a cross-sectional view illustrating a cross section cut along the line NN ′ in FIG.

As shown in FIG. 12A, A shown in FIG.
At points corresponding to the points, the gate signal lines 31 and the common electrode signal lines 36 are formed on the matrix substrate 8 using aluminum 38, and at the same time, the film thickness adjusting film 66 is formed.

The film thickness adjusting film 66 is formed in an island shape at least between the gate signal lines 31 and has a structure that is not electrically connected to the gate signal lines 31.

Next, using the same signal line material as the drain signal line 33, the common electrode wiring 67 is
6 so as to pass therethrough.

FIG. 13A is a plan view of a connection portion between the common electrode signal line and the common electrode wiring at a point corresponding to the point B on the matrix substrate 8 shown in FIG. 1 in the liquid crystal display device of the second embodiment. It is.

FIG. 13B is a diagram showing an example of O in FIG.
It is sectional drawing which shows the cross section cut | disconnected by the -O 'line.

As shown in FIG. 13A, B shown in FIG.
At a point corresponding to the point, the gate signal line 35, the common electrode signal line 36, and the common electrode wiring 67 are simultaneously formed using aluminum 38 on the matrix substrate 8, and then, via the gate oxide film 40, Drain signal line 3
3, and a film thickness adjusting film 66 is formed.

At this time, the film thickness adjusting film 66 is formed on the common electrode wiring 67.

FIG. 14A is a plan view of the intersection of the drain signal line and the common electrode wiring at a point corresponding to the point C of the matrix substrate 8 shown in FIG. 1 in the liquid crystal display device of the second embodiment. is there.

FIG. 14B is a graph showing the relationship between P and P in FIG.
It is sectional drawing which shows the cross section cut | disconnected by the -P 'line.

As shown in FIG. 14A, the C shown in FIG.
At a point corresponding to the point, a gate signal line and a common electrode signal line 67 are formed using aluminum 38 on the matrix substrate 8, and then the drain signal line 33 and the film thickness adjusting film are formed via the gate oxide film 40. 66 is formed.

The film thickness adjusting film 66 is formed on at least the drain signal lines 33 in an island shape.
3 and is formed on the common electrode wiring 67.

As a result, the thickness of the portion where the common electrode wiring 67 is formed becomes the same because the cross-sectional structure becomes equal due to the insertion of the thickness adjusting film 66.

As a result, the film thickness of the common electrode wiring 67 formed at the edge of the substrate can be made constant, the thickness unevenness at the edge of the substrate can be reduced, and the gap length between the two substrates can be made constant. It is possible to reduce gap unevenness of the liquid crystal display device.

FIG. 15 is a diagram showing another arrangement example of the common electrode wiring in the second embodiment.

When the common electrode wiring 67 is routed to the edge of the panel, the area where the common electrode wiring 67 is not provided is placed in the region where the common electrode wiring 67 is not provided.
As shown in FIG. 5, it is also possible to form the dummy signal line 68 with the same material and the same film thickness as the common electrode wiring to reduce the unevenness of the film thickness at the edge of the panel.

As described above, the invention made by the present inventor is:
Although the present invention has been described in detail with reference to the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the scope of the invention.

[0126]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, both ends of the common electrode signal line are connected to the common electrode wiring, and the resistance of the common electrode wiring is made smaller than the resistance of the common electrode signal line. It is possible to reduce the waveform distortion of the drive voltage of the common electrode supplied from the drive circuit, the electric field strength between the pixel electrode in each pixel and the common electrode becomes nearly uniform in the panel, and the common electrode signal line Can be reduced.

(2) According to the present invention, since both ends of the common electrode signal line are connected to the common electrode wiring, even if one of the common electrode signal lines is broken halfway, the common electrode signal line is disconnected. Since a common voltage can be supplied from both ends of the line and the liquid crystal of each pixel can be driven, it is possible to prevent the liquid crystal of the previous pixel from being driven from a broken portion as in the conventional example, thereby preventing display quality from being impaired. Can be.

(3) According to the present invention, the cross-sectional structure of the region where the common electrode wiring is provided is the same as the cross-sectional structure of the intersection between the common electrode wiring and the gate signal line or the drain signal line. Therefore, it is possible to reduce the unevenness of the film thickness at the edge of the substrate on which the common electrode wiring is formed, thereby making it possible to make the gap length between the two substrates constant, and to make the gap unevenness of the liquid crystal display device. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a liquid crystal display device according to an embodiment (Example 1) of the present invention.

FIG. 2 is a circuit diagram illustrating an equivalent circuit of a transmission path of a driving voltage applied to a common electrode in the liquid crystal display device of the present embodiment.

FIG. 3 is a diagram showing a waveform of a driving voltage at each point shown in FIG. 2;

FIG. 4 is a diagram showing an equivalent circuit of the pixel shown in FIG.

FIG. 5 is a diagram showing a plane and a cross section of a pixel formed on a matrix substrate.

6 is a diagram showing a plane and a cross section of an example of a connection portion between a common electrode signal line and a common electrode wiring at a point A on the matrix substrate shown in FIG. 1;

7 is a diagram showing a plane and a cross section of a connection portion between a common electrode signal line and a common electrode wiring at a point B on the matrix substrate shown in FIG. 1;

8 is a diagram showing a plane and a cross section of an intersection between a drain signal line and a common electrode line at a point C of the matrix substrate shown in FIG. 1;

9 is a diagram showing a plane and a cross section of another example of a connection portion between the common electrode signal line and the common electrode wiring at a point A on the matrix substrate shown in FIG. 1;

FIG. 10 is a diagram showing another arrangement example of the common electrode wiring in the first embodiment.

FIG. 11 is a diagram illustrating another arrangement example of the common electrode wiring in the first embodiment.

12 is a diagram showing a plane and a cross section of a connection portion between a common electrode signal line and a common electrode wiring at a point corresponding to point A on the matrix substrate shown in FIG. 1 in the liquid crystal display device of Example 2. FIG.

13 is a diagram showing a plane and a cross section of a connection portion between a common electrode signal line and a common electrode wiring at a point corresponding to point B on the matrix substrate shown in FIG. 1 in the liquid crystal display device of Example 2. FIG.

14 is a diagram showing a plane and a cross section of an intersection between a drain signal line and a common electrode line at a point corresponding to point C on the matrix substrate shown in FIG. 1 in the liquid crystal display device of Example 2. FIG.

FIG. 15 is a diagram showing another example of the arrangement of the common electrode wiring in the second embodiment.

FIG. 16 is a block diagram illustrating a schematic configuration of a driving circuit of a liquid crystal display device of a horizontal electric field type.

17 is a circuit diagram showing an equivalent circuit of a transmission path of a drive voltage applied to a common electrode in the in-plane switching mode liquid crystal display device shown in FIG.

18 is a diagram showing a waveform of a driving voltage at each point shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Gate drive circuit, 2 ... Drain drive circuit, 3 ... Common voltage generation drive circuit, 4,47,49,67 ... Common electrode wiring, 5,16,36 ... Common electrode signal line, 6,15,33
... Drain signal lines, 7, 17, 31 ... Gate signal lines, 8
... Matrix substrate, 9 counter substrate, 10 timing controller, 11 video signal source, 12 pixels, 13,
28 ... drain electrode, 14, 29 ... source electrode, 18 ...
Gate-drain cross capacitance, 19 common-drain cross capacitance, 20 liquid crystal, 21 storage capacitance, 22 parasitic capacitance (Cgd), 23 parasitic capacitance (Cgs), 24 thin-film transistor, 25, 37 pixel electrode, 26, 30 ... gate electrode, 27, 32 ... common electrode, 34a, 34b ... common electrode wiring, 35, 61 ... storage capacitor, 38 ... aluminum, 39 ... aluminum oxide, 40 ... gate oxide film, 4
1: Chromium, 42: Aluminum, 43: Protective film, 44
... semiconductor layers, 45a and 45b ... ohmic layers, 46 ... alignment films, 48 ... contact holes, 66 ... film thickness adjustment layers, 6
8 ... Dummy signal line.

Claims (4)

(57) [Claims] 1. A pair of substrates, a plurality of active elements formed in a display area on the one substrate, and a plurality of pixel electrodes formed on the one substrate and connected to the plurality of active elements, respectively. A plurality of scan electrodes formed on the one substrate in a row direction and applying a scan voltage to each active element in the row direction; and a plurality of active elements formed on the one substrate in a column direction and in the row direction A plurality of signal electrodes for applying a signal voltage to the liquid crystal layer; and A common electrode, a liquid crystal layer sandwiched between the pair of substrates, a scan electrode driving means for driving the scan electrodes, a signal electrode drive means for driving the signal electrodes, and a common electrode for driving the common electrodes. And a common electrode connected to each common electrode arranged in the row direction in a liquid crystal display device having at least
Each common electrode signal line having a pole signal line and arranged in the column direction
Are common electrodes whose both ends are formed outside the display area.
Are connected in common by pole wiring, and this common electrode wiring
Is a liquid crystal display device having a lower resistance than the common electrode signal line . 2. An area where the common electrode wiring is not provided.
2. The liquid crystal display device according to claim 1, further comprising a dummy line having the same material and the same thickness as the common electrode wiring. 3. An upper or lower layer of the common electrode wiring at an intersection between the common electrode wiring and the scanning electrode or the signal electrode and at a non-intersection other than a connection between the common electrode wiring and the common electrode. 3. The liquid crystal display device according to claim 1, further comprising a film thickness adjusting film having the same material and the same thickness as the scanning electrode. 4. An upper layer or a lower layer of the common electrode wiring at an intersection between the common electrode wiring and the scanning electrode or the signal electrode, and at a non-intersection other than a connection between the common electrode wiring and the common electrode. 3. The liquid crystal display device according to claim 1, further comprising a film thickness adjustment film having the same material and the same thickness as the signal electrode.