JP2768736B2 - Charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a charge coupled device (CCD).
More particularly, the present invention relates to a charge transfer device using a surface channel CCD system for a signal input unit and a buried channel CCD system for a signal transfer unit and a signal output unit.

(Prior Art) When a charge transfer device for transmitting an analog signal by using a CCD is configured in a semiconductor integrated circuit, the charge input device, the signal transfer portion, and the signal output portion adopt a buried channel CCD system, thereby increasing the cost. Transfer efficiency, high sampling rate, and high signal-to-noise ratio are obtained.

However, one of the problems of the buried channel CCD system is often the deterioration of the linearity particularly at the signal input section, and in order to improve this, the surface channel CCD input is changed to the surface channel CCD system. It is not uncommon to employ a method.

Here, the operation principle of the conventional N-channel charge transfer device employing the surface channel CCD input method will be described.
FIG. 7 shows the configuration of the charge transfer device in a simplified manner, and shows how the potential in the substrate changes during operation. A pair of clocks φ1 and φ2 output from the clock generation circuit 80 in FIG. Is shown in FIG.

That is, a high-concentration impurity (N ⁺ ) diffusion region 70 for the input source region is formed on the surface of the semiconductor substrate, and an impurity (N) diffusion region 75 for forming a charge injection well at a position further away from this. A low concentration impurity (N ⁻ ) diffusion region 76 and an impurity (N) diffusion region 77 for forming a buried channel are alternately formed in the charge transfer direction. A gate insulating film (not shown) on the semiconductor substrate
, A first input gate electrode 71 to a fourth input gate electrode 74 are sequentially formed, and a plurality of pairs of a transfer device 78 and a storage electrode 79 are formed in the charge transfer direction. The first to third input gate electrodes 71 to 73 are:
The fourth input gate electrode 74 is located on the surface channel between the N ⁺ diffusion region 70 and the N diffusion region 75,
Located above 75. The transfer electrode 78 and the storage electrode 79 of each pair are respectively located on the N ⁻ diffusion region 76 and the N diffusion region 77 adjacent thereto. Note that the transfer electrode 78 and the storage electrode 79 are commonly connected, and the third input gate electrode 73 and the fourth input gate electrode 74 are commonly connected.

The clock generation circuit 80 outputs two layers of clocks φ1 and φ2 which are almost in opposite phases to each other as shown in FIG.
The clock φ1 is supplied to the first input gate electrode 71 and the odd-numbered pairs of transfer electrodes 78 and storage electrodes 79, and the clock φ2 is supplied to the third input gate electrode 73, the fourth input gate electrode 74, and the even-numbered Are supplied to the transfer electrode 78 and the storage electrode 79 of each pair. That is, the first input gate unit 71
Have a third input gate unit 73 and a fourth input gate unit 74
And a clock having the same phase as that of the third input gate unit 73 and the fourth input gate unit 74. Then, a DC potential Vx (for example, Vcc power supply potential) is applied to the second input gate electrode 72, and an analog signal input Vin is applied to the N ⁺ diffusion region 70 for the input source region together with the DC bias.

In the above configuration, the level relationship between the clocks φ1 and φ2 (the relationship between the low level “L” and the high level “H”) corresponds to the potentials in the substrate corresponding to the times t1, t2, t3, and t4 shown in FIG. The charge changes as shown in FIG.

That is, at time t1, the charge Q having the potential of P1 is filled under the N ⁺ diffusion region 70 for the input source region. This potential P1 is determined by the DC bias value of the input signal, and no charge transfer is performed at this time t1. Next, at time t2, the potential under the first input gate electrode 71 moves to a position higher than the potential under the second input gate electrode 72, and the potential under the first input gate electrode 71 and the second input gate Potential below electrode 72
Filled with charge with P1. At the same time, the potentials under the odd-numbered transfer electrodes 78 and storage electrodes 79 move to higher positions, and charges are transferred from the preceding stage. Next, at time point t3, the potential below the first input gate electrode 71 moves to a lower position again, and the electric charge keeps the potential P1.
What is returned under the N ⁺ diffusion region 70 for the input source region;
The second input gate electrode 72 is divided into two. At the same time, the potentials under the odd-numbered transfer electrodes 78 and the storage electrodes 79 move to lower positions again, and the charges are stored under the storage electrodes 79. Next, at time t4, the electric charge accumulated under the second input gate electrode 72 is injected under the fourth input gate electrode 74. At the same time, the potential under the even-numbered transfer electrodes 78 and storage electrodes 79 moves to a higher position, and charges are transferred from the preceding stage. Thereafter, the same operation as the above-described operation in the cycle from time t1 to time t4 is repeated, and injection and transfer of signal charges are repeatedly performed.

FIG. 9 shows the relationship between the gate voltage VG applied to the first input gate electrode 71 to the fourth input gate electrode 74 and the potential PW formed under each gate electrode. Here, when the gate voltage VG is lower than a certain gate voltage VGx, the relationship (charge transfer characteristic) between the gate voltage VG and the potential PW becomes non-linear. Conversely, when the gate voltage VG is higher than a certain gate voltage VGx, the gate voltage VG becomes higher. The relationship between VG and potential PW is linear.

By the way, conventionally, for example, using a Vcc power supply potential of 9 V,
When the "H" level of the clocks φ1 and φ2 is set to the Vcc power supply potential, the DC transfer bias applied to the second input gate electrode 72 is set to an appropriate value, so that the charge transfer at the signal input unit is performed. Can be performed within the range of the linear region I shown in FIG. 9, and the charge can be injected into the signal transfer unit without deteriorating the linearity at the signal input unit.

However, when attempting to realize a charge transfer device that can operate even at a low Vcc power supply potential in order to reduce power consumption,
Even if the "H" level of the clocks φ1 and φ2 is set to the Vcc power supply potential with the configuration of the conventional charge transfer device, the “H” level potential is lower than in the conventional case. In other words,
Since the "H" level of the clock applied to the first input gate electrode 71, the third input gate electrode 73, and the fourth input gate electrode 74 is lower than in the conventional case, the first input gate electrode 71, Third input gate electrode 73, fourth input gate electrode
Part or all of the charge transfer under 74 is performed within the range of the non-linear region II shown in FIG. 9, which causes a problem that the linearity at the signal input portion is deteriorated.

(Problems to be Solved by the Invention) As described above, the charge transfer device employing the conventional surface channel CCD input method operates at a low power supply potential, and the "H" level of the clock applied to the input gate portion , And part or all of the charge transfer at the input gate portion is performed within the range of the non-linear region of the charge transfer characteristic, which causes a problem that the linearity at the signal input portion is deteriorated.

The present invention has been made to solve the above problems,
The purpose is to be able to operate without deteriorating the linearity at the signal input part even when using a low power supply potential,
An object of the present invention is to provide a charge transfer device that can achieve low power consumption.

[Means for Solving the Problems] The present invention relates to a charge transfer device using a surface channel charge-coupled device method for a signal input unit and a buried channel charge-coupled device method for a signal transfer unit. The clock applied to the signal input unit is a clock boosted by a boosting circuit so that the “H” level is equal to or higher than a power supply potential supplied to a clock generation unit that generates a clock. I do.

(Operation) The operation principle of this charge transfer device is basically the same as that of the above-described conventional charge transfer device.
A clock whose voltage has been boosted so that the “H” level is equal to or higher than the power supply potential supplied to the clock generation unit that generates the clock is applied to the signal input unit, so that the signal input unit has a higher potential. By the way, signal charges are handled.

Therefore, if a low power supply potential is used to reduce the power consumption and the "H" level of the boosted clock is boosted to, for example, substantially the same as the conventional power supply potential, the electric charge at the signal input unit is increased. The transfer can be performed completely within the range of the linear region, and the linearity at the signal input unit does not deteriorate. When the “H” level of the clock applied to the signal transfer unit is set to the power supply potential, the “H” level potential of this clock becomes lower than before, but the signal transfer unit uses the embedded channel CCD method. Therefore, the linearity does not deteriorate.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a simplified configuration of a charge transfer device employing a surface channel CCD input method, and shows how the potential and charge in the substrate change during operation. Compared with the above-described conventional charge transfer device, (1) a pair of clocks φ1 and φ2 as described above and a pair of two-phase clocks φ1 ′ and φ2 having substantially opposite phases to each other are generated from the clock generation circuit 10. And the pair of clocks φ1 ′ and φ2 ′ are input to the pulse booster circuit 11, where the “H” level changes to the clock generation circuit.
The two-phase clocks φ1 ″ and φ2 ″ of substantially opposite phases, which are boosted to a potential equal to or higher than the power supply potential Vcc supplied to 10, are replaced with the first pair of clocks φ1 and φ2 at the first signal input unit. The difference is that the voltage is applied to the input gate electrode 71, the third input gate electrode 73, and the fourth input gate electrode 74, and the other components are the same.

That is, in FIG. 1, a high-concentration impurity (N ⁺ ) diffusion region 70 for an input source region is formed on the surface of a semiconductor substrate, and an impurity for forming a charge injection well at a position further away from the high concentration impurity (N ⁺ ) region. An N) diffusion region 75 is formed, and adjacent thereto, low-concentration impurity (N ⁻ ) diffusion regions 76 and impurity (N) diffusion regions 77 for forming a buried channel are alternately formed in the charge transfer direction. A first input gate electrode 71 to a fourth input gate electrode 74 are sequentially formed on a semiconductor substrate via a gate insulating film (not shown), and a transfer electrode 78 is formed.
A plurality of pairs of the storage electrodes 79 are formed in the charge transfer direction. The first input gate electrode 71 to the third input gate electrode 73 are located on a surface channel between the N ⁺ diffusion region 70 and the N diffusion region 75, and the fourth input gate electrode 74
Are located on the N diffusion region 75.

The transfer electrode 78 and the storage electrode 79 of each pair are respectively located on the N ⁻ diffusion region 76 and the N diffusion region 77 adjacent thereto. In addition, each pair of transfer electrodes
The 78 and the storage electrode 79 are commonly connected, and the third input gate electrode 73 and the fourth input gate electrode 74 are commonly connected. An analog signal input Vin is applied to the N ⁺ diffusion region 70 for the input source region together with a DC bias as in the conventional case, and the DC potential Vx is applied to the second input gate electrode 72 as in the conventional case. The clock φ1 is applied to the transfer electrode 78 and the storage electrode 89 as usual, and the clock φ2 is applied to the even-numbered pairs of the transfer electrode 78 and the storage electrode 79 as before.

In this embodiment, the clock φ1 ″ is applied to the first input gate electrode 71, and the clock φ2 ″ is applied to the third input gate electrode 73 and the fourth input gate electrode 74.

FIG. 2 shows each of the clocks φ1, φ2, φ1 ', φ2', φ
The timing relationship and potential of 1 ″ and φ2 ″ are shown. Here, Vcc + Va indicates a boosted potential.

In the charge transfer device of the above embodiment, the potential and charge in the substrate corresponding to the time points t1, t2, t3, and t4 shown in FIG. 2 change as shown by the solid line in FIG. The relationship between the gate voltage VG applied to the gate electrode 71 to the fourth input gate electrode 74 and the potential PW formed below each gate electrode is as shown in FIG.

That is, the basic operation of the charge transfer device of the above embodiment is the same as that of the conventional charge transfer device described above with reference to FIG. Since the clocks φ1 ″ and φ2 ″ which have been boosted so that the level becomes equal to or higher than the Vcc power supply potential are applied, the signal charge is handled at a higher potential at the signal input portion. different.

Therefore, according to the charge transfer device of the above embodiment, when a low Vcc power supply potential is used to reduce power consumption,
If the "H" level of the clocks φ1 ″ and φ2 ″ applied to the signal input unit is boosted so as to be, for example, substantially the same as the conventional Vcc power supply potential, the charge transfer in the signal input unit is completely completed. This can be performed within the range of the middle linear region I, and the linearity at the signal input portion does not deteriorate.

When the "H" level of the clocks φ1 and φ2 applied to the signal transfer unit is set to the Vcc power supply potential, the potential of the “H” level of the clocks φ1 and φ2 becomes lower than before, but the signal transfer unit Since the indented channel CCD method is used, the linearity does not deteriorate.

Further, according to the charge transfer device of the above embodiment, even when the "H" level of the clocks φ1 and φ2 is set to the Vcc power supply potential using the same Vcc power supply potential (for example, 9 V) as the conventional one,
Since the clocks φ1 ″ and φ2 ″ whose “H” level is higher than the Vcc power supply potential are applied to the signal input portion, the linearity in the signal input portion is good.

Since the third input gate electrode 73 and the fourth input gate electrode 74 are connected in common, only one booster circuit for outputting the clock φ2 ″ to be applied to them is required. , The timings of the clocks applied to the third input gate electrode 73 and the fourth input gate electrode 74 can be easily matched.

In FIG. 1, the potentials and charges shown by solid lines correspond to the above-described embodiment in which the Vcc power supply potential is applied to the second input gate electrode 72, but as another embodiment,
When an appropriate DC potential that has been boosted above the Vcc power supply potential is applied to the second input gate electrode 72, the potential and charge become as shown by the dotted lines in FIG. In this way, among the input charges stored under the second input gate electrode 72, the “H” level clock φ2 ″ is applied to the third input gate electrode 73 and the fourth input gate electrode 74. In this case, a mode in which only charges lower than the potential below the third input gate electrode 73 at the time of transfer can be realized, and a charge transfer device with good linearity and high transfer efficiency can be realized.

3 shows a clock φ2 ″ booster circuit section as a specific example of the pulse booster circuit 11. That is, a first circuit in which the drain and the gate are connected between the Vcc power supply potential and the ground potential Vss, respectively. The N-channel MOS transistor N1 and the second N-channel MOS transistor N2 are connected in series, and a third N-channel MOS transistor N3 is connected between the series connection point 30 of the two transistors and the boosted output node 31. Is connected to one end of a bootstrap capacitor C. The clock φ1 ′ is input to the gate of the third transistor N3, and the clock φ2 ′ is connected to the other end of the capacitor C. Enter.

In the clock φ2 ″ booster circuit section, the potential Va of the series connection point 30 of the two transistors N1 and N2 is maintained at a constant value obtained by dividing the Vcc power supply potential by resistance by the two transistors N1 and N2. ′ Is “H” level,
When the clock φ2 'is at "L" level, the third transistor
N3 is turned on, and the capacitor C is charged to the potential Va. next,
When the clock φ1 ′ goes to “L” level and the clock φ2 ′ goes to “H” level, the third transistor N3 is turned off, and the potential Vb of the boosted output node 31 is boosted to the potential of Vcc + Va. As a result, the clock φ
2 ′, the “L” level potential is Va, and the “H” level potential is Vcc + Va. The boosted clock φ2 ″ is output.

On the other hand, the clock φ1 ″ booster circuit is configured in the same manner as described above, except that the clock φ2 ′ is input to the gate of the third transistor N3, and the clock φ1 ′ is input to the other end of the capacitor C.

Note that the pulse booster circuit is not limited to the above specific example, and various modifications can be made.

Further, a pair of clocks φ1, φ
2 is output, this is branched, and a pair of clocks φ
Instead of 1 ′ and φ2 ′, they may be input to the pulse booster circuit 11.

In each of the above embodiments, the second input gate portion and / or the fourth input gate portion may be modified so as to be formed of an N ⁺ diffusion region. Shown in

The charge transfer device shown in FIG. 4 is different from the charge transfer device shown in FIG. 1 in that an N ⁺ diffusion region 41 is formed in a substrate portion under a second input gate electrode (FIG. 1). A DC potential Vx (or a DC potential boosted to a Vcc power supply potential or higher) is applied to the N ⁺ diffusion region 41, and a second input gate electrode (first
FIG. 72) is omitted, and the other parts are the same. Therefore, the same reference numerals as those in FIG.
The potential and charge in the substrate corresponding to t1, t2, t3, t4 change as shown.

The charge transfer device shown in FIG. 5 is different from the charge transfer device shown in FIG. 1 in that the N ⁺ -diffused substrate portion and the N-diffusion region 75 below the fourth input gate electrode (FIG. 74) are used. Region 51
The difference is that a clock φ2 ″ is applied to this N ⁺ diffusion region 51, and the fourth input gate electrode (FIG. 74) is omitted, and the other components are the same. The potential and charge in the substrate corresponding to time points t1, t2, t3, and t4 shown in FIG. 2 change as shown.

The charge transfer device shown in FIG. 6 is different from the charge transfer device shown in FIG. 1 in that an N ⁺ diffusion region 61 is formed in a substrate portion below a second input gate electrode (FIG. 72). , Fourth
An N ⁺ diffusion region 62 is formed in the substrate portion and the N diffusion region 75 below the input gate electrode (FIG. 74), and the DC potential Vx (or Vcc power supply potential or more) is raised in the N ⁺ diffusion region 61. Applied to the N ⁺ diffusion region 62, and a clock φ2 ″ to the second input gate electrode (FIG. 7).
2) and the fourth input gate electrode (FIG. 74) are omitted, and the other components are the same. Therefore, they are denoted by the same reference numerals as those in FIG. The potential and charge in the substrate corresponding to t2, t3, t4 change as shown.

[Effects of the Invention] As described above, according to the charge transfer device of the present invention, even when a low power supply potential is used, the operation can be performed without deteriorating the linearity in the signal input unit, and various factors associated with lower power consumption can be achieved. Effects can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing the configuration of an embodiment of the charge transfer device of the present invention, FIG. 2 is a timing diagram showing the timing relationship and potential of each clock in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing a specific example of a part of the pulse booster circuit. FIGS. 4 to 6 are explanatory diagrams each showing a modification of the charge transfer device of FIG. 1, and FIG. FIG. 8 is a timing chart showing timing relationships and potentials of respective clocks in FIG. 7, and FIG.
8 is a characteristic diagram showing a relationship between a gate voltage VG applied to an input gate electrode and a potential PW formed under the gate electrode in the charge transfer device shown in FIG. 7 and the charge transfer device shown in FIG. 10 …… Clock generation circuit, 11 …… Pulse booster circuit, 41,5
1,61,62,70... N ⁺ diffusion region, 71... First input gate electrode, 72... First input gate electrode, 73... Third input gate electrode, 74. Input gate electrode, 75,77 ... N
Diffusion region, 76 …… N ^- diffusion region, 78 …… Transfer electrode, 79 ……
Storage electrode, φ1, φ2 clock, φ1 ″, φ2 ″
Boosted clock, Vin …… Analog input signal, Vx…
... DC potential.

────────────────────────────────────────────────── (5) References JP-A-3-123037 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29/768 H01L 21/339

Claims (4)

(57) [Claims] A signal input unit of a surface channel charge-coupled device type; a signal transfer unit of a buried channel charge-coupled device type for transferring charges injected from the signal input unit;
A clock generating unit for generating a clock, wherein the signal input unit includes an impurity diffusion region, a first input gate unit, a second input gate unit, a third input gate unit, and a fourth input gate unit. An input signal and a DC bias are applied to the impurity diffusion region, the first input gate section is controlled by a first clock generated by the clock generation section, and the second input gate section Is applied with a predetermined DC potential, and the third input gate section and the fourth input gate section are generated by the clock generation section, and controlled by a second clock having a phase substantially opposite to that of the first clock. In the charge transfer device, the first and second clocks for controlling the signal input unit are supplied to a booster circuit so that the “H” level becomes equal to or higher than a power supply potential supplied to the clock generation unit. Charge transfer device which is a boosted clock Ri. 2. A clock applied to the signal transfer unit,
2. The charge transfer device according to claim 1, wherein the "H" level is a clock that becomes a power supply potential supplied to the clock generation unit. 3. The DC potential applied to the second input gate unit is a DC potential boosted to a power supply potential supplied to the clock generation unit or higher.
Or the charge transfer device according to 2. 4. The charge transfer device according to claim 1, wherein said third input gate and said fourth input gate are connected in common.