JP2767487B2 - Displacement gauge - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a displacement measuring instrument such as a laser length measuring instrument, a linear encoder, and a rotary encoder used for measuring a length, a displacement or a velocity, and more particularly to a movable object. R sin θ and R cos θ (where θ = 2πα)
/ S, S is a predetermined period), a displacement meter that obtains an electrical signal that changes at a predetermined cycle, and obtains θ from these two kinds of signals to measure α.

(Prior art)

For example, "Optical Technology Contact" Vol.26, No2 (1988),
As shown in FIG. 10 introduced on pages 107 to 108, the interference fringe counting type laser length meter is one of the above-described displacement meters.

In this laser length measuring device, linearly polarized light having a wavelength λ from a stabilized laser 1 is split by a beam splitter 2 into a reference optical path having a λ / 8 plate 3 and a fixed corner cube 4 and a length measuring optical path having a moving corner cube 5. Then, the reference light branched to the reference light path passes through the λ / 8 plate 2 twice and is converted into circularly polarized light. The circularly-polarized reference light and the linearly-polarized measurement light branched to the length-measuring optical path are again combined by the beam splitter 2 and divided into two. One of the two divisions is further divided by the polarization beam splitter 6 so that the measurement light is converted into two. The light is split into two parts so that the light is separated in the ± 45 ° direction with respect to the polarization plane, thereby obtaining three types of split light. The three types of divided light pass through the filter 7 and the polarizing plate 8, respectively, so that the three types of interference light are shifted by 90 ° in phase in order to interfere with the movement of the movable corner cube 5 in one direction. The interference light is incident on a detector 9 such as a photodiode, respectively.
The signals are converted into three types of electric signals having a phase difference of 90 ° each. The three kinds of electric signals are amplified by the operational amplifier 10 for adjusting the amplitude and the center value of the amplitude respectively, and then are sequentially divided into two sets, each of which is composed of a pair of neighbors whose phases are shifted by 90 °. R sin θ and R sin 90 ° out of phase by being input to an operational amplifier 11 for calculating sin (xy)
cos θ (where R is amplitude, θ = 2π (Lm−Lr) / λ, Lr
Is a fixed reference optical path length, and Lm is an electrical signal that changes in a length measuring optical path length that changes by 2α with a moving amount α in one direction of the moving corner cube 5, that is, an electric signal that changes in a predetermined cycle S = λ / 2. Since this electric signal is obtained from the difference between sequentially adjacent signals of three kinds of interference fringe signals whose phases are sequentially shifted by 90 °, the influence of disturbance such as intensity fluctuation of laser light is canceled out, and the center of the signal level is shifted. It is always constant, so that mistakes in the interference fringe counting can be reduced, and highly accurate measurement can be performed. A signal processing circuit 12 using a counting circuit including a comparison circuit, a differentiation circuit, a waveform shaping circuit, an OR circuit, and a pulse counter, which obtains a pulse signal from the two electrical signals and obtains a pulse signal from the two electrical signals, or
Including the D converter, θ = tan ^-1 (R sin θ / R cos θ) (1) or further Is input to a signal processing circuit 12 consisting of a digital arithmetic circuit for performing the above operation and a discriminating circuit for logically obtaining the direction of a change in θ from both electric signals, and obtains θ and thus α and ± directions or Lm.

Not only the laser length meter described above, but also the interference fringe counting type laser length meter that converts two types of interference light having a phase shift of 90 ° into an electric signal and the heterodyne interferometer using a two-frequency laser, as well as the National Technical Report Vol. .36, No2, Apr.1990,
A displacement meter such as a magnetic or optical rotary encoder or a linear encoder introduced on pages 114 to 120 also obtains output signals of R sin θ and R cos θ, and outputs these signals similarly to the signal processing circuit 12. The rotation angle and the amount of linear displacement are measured by obtaining the angle θ by performing the above processing.

The signal processing circuit 12 using the above-described counting circuit sets θ to π / 2
In order to obtain with m unit accuracy, m comparison circuits, 2m differentiation circuits and waveform shaping circuits are required for each of the two signals, and the circuit becomes complicated and expensive, and θ is fine with π / 2m unit accuracy. There is a problem that it is difficult to find. On the other hand, a signal processing circuit using the aforementioned digital arithmetic circuit
12 can determine θ with fine unit accuracy,
In order to perform high-speed calculations of equations (1) and (2), for example, MC
Even if the 68020 CPU is driven at 20 MHz and a high-speed memory that tracks non-waiting is provided and the high-speed arithmetic element of the MC68882 is used, it takes at least 10 μsec or more to obtain θ and R. 10MHz discriminating circuit to determine the direction of change
Even if the degree of change can be followed, there is a problem that the overall processing speed is reduced to 0.1 MHz or less due to the operation speed of the digital operation circuit. In the case where the A / D converter outputs an offset binary, since the center value of the amplitude of R sin θ and R cos θ has the offset value D, the digital arithmetic circuit uses θ instead of the equations (1) and (2). = Tan ^-1 {R sin θ-D) / (R cos θ-D)} (3) , And the calculation speed is further reduced.

Therefore, the present inventor does not calculate the signal of R sin θ and R cos θ in real time to obtain θ,
If the signal of nθ, R cos θ is used as a read signal for reading out the corresponding θ value from the memory that stores various θ values corresponding to various sets of R sin θ, R cos θ in advance, the cost can be reduced and the size can be reduced. With the idea that a high-precision θ can be obtained at high speed by a configurable signal processing circuit, R si
A signal obtained by digitally converting nθ and R cos θ is used as a read signal in advance to various values corresponding to a combination of various digital signals (where the value is a digital value of 0 ≦ θ = −2nπ <2π, and n is a value to be described later). The corresponding value is read from the memory storing the (count number), and the number of times that the value increases from the decrease or increases from the decrease is counted to n
And invented a displacement meter that obtains θ from the value and n. According to the displacement meter of the present invention, θ can be easily obtained at a high speed of 10 MHz or more with a phase resolution of 2π / 256.

However, in the case of using a means for digitally performing zero-cross detection in an analog circuit as conventionally used as an up / down discriminating counting means for counting n, counting cannot be performed unless the value becomes 0 each time. Therefore, if the sampling speed does not change by 1 LSB, counting may be skipped over 0, and the change speed of α is limited low.

[Problems to be solved by the invention]

The present invention has been made in order to solve the above-described problem. However, even if the count does not become 0 each time, the count is correctly performed and an accurate n can be obtained. An object of the present invention is to provide a displacement meter that can obtain θ at high speed and high accuracy.

[Means for solving the problem]

The present invention provides a method of calculating R sin θ,
An electric signal changing at R cos θ (where θ = 2πα / S, S is a predetermined cycle) is obtained, and a digital signal obtained by digitally converting the two signals is read out as a read signal. The corresponding value is read out from the memory storing various values (where the value is a digital value of 0 ≦ = θ−2nπ <2π, and n is a count number described later) corresponding to the combination, and the value increases. Counting the number of decrease or increase from decrease to obtain n,
A displacement meter that obtains θ from the value n. The condition is such that the interval between sequentially read values is set to π / k (where k is 2 or 1) or less, and is read when n is set to 0. ₀
The difference between the value and _one value read at any time thereafter based on this value The difference between the _two values read next When k is set to 2, Is the value in the fourth quadrant for ₀ , Counts up when is in the first quadrant, Is the value in the first quadrant for ₀ , Is counted in the fourth quadrant, and counting is performed by using up / down discriminating counting means that does not count otherwise.
When is set to 1, Is the value in the third or fourth quadrant, Phase difference by π Counts up when The displacement meter uses up / down discrimination counting means that counts down when it is larger, and does not count otherwise, and the above-mentioned object is achieved by this configuration.

[Action]

That is, in the displacement meter of the present invention, R sin θ, R co
The signal processing circuit for processing the signal of sθ to obtain θ is R sin
The digitally converted signals of θ and R cos θ are used to read out corresponding values from a memory in which various values obtained from the expressions (1) and (3) are stored in advance, and the expressions (1) and (2) are used. Since the arithmetic processing of the equations (3) and (4) is not performed, the value can be obtained at high speed and with high accuracy.
/ 2 or less than π, the difference between the ₀ value when n is 0, the ₁ value at any time thereafter, and the next ₂ values Is in the fourth quadrant Count up when it changes to the first quadrant From the fourth quadrant If it changes to, count down and do not count otherwise. Phase difference by π Count up when it changes to Greater than If the value changes to 2LSB or more, accurate counting can be performed. Therefore, the rate of change of α is the reading speed of the value. 1 /
Even when the frequency speed is increased to 2 or 1/4, θ can be measured, and the signal processing circuit can be configured inexpensively and compactly.

〔Example〕

Hereinafter, the present invention will be further described with reference to FIGS. 1 to 9.

FIG. 1 is a block circuit diagram showing an example of a signal processing circuit used in the displacement meter of the present invention, and FIG. 2 is R sin θ, R cos θ.
FIGS. 3 and 4 are memory graphs showing examples of memory contents of a memory and an R memory.
6 is a block circuit diagram showing an example of a clear circuit, FIGS. 6 and 8 are block circuit diagrams showing an example of an up / down discriminating circuit, and FIGS. 7 and 9 are FIGS. 6 and 8, respectively. 4 is a Lissajous graph for explaining the function of a discrimination circuit.

In FIG. 1, reference numerals 21a and 21b denote A / D converters for digitally converting the signals of R sin θ and R cos θ as shown in FIG. 8, respectively. A digital signal is used. For this, R sinθ, R cosθ
Is represented by 8 bits, and θ is also represented by 8 bits. In the Lissajous graph of FIG. 2, θ of 0 ≦ θ <2π is represented by 8 bits so as to correspond to the fastest change rate of α. Even if the LSB of θ is 2π / 256, R sin θ, R cos θ and θ are expressed in 8 bits, and θ can be obtained with a fine unit accuracy that is sufficiently satisfactory for most displacement meter purposes. . Let θ of 0 ≦ θ <2π be R sinθ,
When expressed in the same number of bits as R cos θ, R sin θ, R cos
Even if the amplitude of θ decreases to about 1/2, θ can be obtained with the unit accuracy of the LSB of θ, whereas when only θ is expressed by a larger number of bits, R sin θ and R cos θ When the amplitude decreases, the actual unit accuracy of θ obtained tends to be coarser than the LSB of θ. Therefore, it is preferable that R sin θ, R cos θ and θ of 0 ≦ θ <2π be represented by the same number of bits.

22 is the value of θ as described above, that is, 0 to 2
Various R sin θ, R co that changes according to the change up to π
From the combination of the digital signals of sθ, the value obtained by the expression (3) or (1) is calculated as R sinθ, R cos
It is a memory that is stored so that it can be read out by a digital signal of θ. The memory graph shown in FIG. 3 is similar to the Lissajous graph shown in FIG. 2 except that the value represented by 8 bits corresponding to the address 0 ≦ θ <2π specified by the 8-bit R sin θ and R cos θ is centered on the center. 5 shows an example of a memory stored so as to gradually increase in a counterclockwise direction. Not limited to this example, the memory 22 may store a value represented by a bit number other than 8 bits as described above,
The values of nθ and R cosθ may not be arranged in order.

23 has various R sin θ, R cos θ in advance as in the memory 22.
The digital value of R obtained by the equation (4) or (2) from the combination of the digital signals R sinθ, R co
This is an R memory that stores the digital signal of sθ so that it can be read. In the memory graph of FIG. 4, similarly to the Lissajous graph of FIG. 2, the R value represented by 8 bits at the address specified by the 8-bit R sin θ and R cos θ gradually increases radially outward from the center. R stored
3 shows an example of a memory 23. The R memory 23 is not limited to this example. Even if the R value is represented by a number of bits other than 8 bits,
Of course, the values of R sin θ and R cos θ may not be arranged in order. In this example, when the R value exceeds 127, it indicates that R sin θ or R cos θ overflows beyond the 8-bit range of A / D conversion.

24 sets the value read from the memory 22 to an arbitrary origin position of 0, and changes from there to the direction or direction of the Lissajous graph of FIG. This is a clear circuit that converts the value into a value and outputs it. This consists of a transparent latch circuit 24a and a full adder 24b, as shown in FIG. The transparent latch circuit 24a always outputs the complement of the value from the memory 22 when the signal ▼ is at low level 0,
When the signal changes to high level 1, the complement at that time is latched and output. And full adder 24b
Is the result of adding the value from the memory 22, the complement from the transparent latch circuit 24a and the least significant carry-in (High). The value is always 0 as a result of (-) when the signal ▲ is 0, and gives a difference between the output value of the memory 22 when the signal becomes 1 when the signal ▼ becomes 1 and a subsequent output value.

25 is Output from the clear circuit 24 to count the rotation speed n of An up / down discriminating circuit for discriminating whether a value increases from a decrease or increases from a decrease. This is illustrated in FIGS. 6 and 8.
The configuration as shown in the figure is used.

The up / down determination circuit 25 shown in FIG. Output value by next clock When the upper two bits MSB and MSB-1 of the AND gate have the relationship shown in the row of the truth table in Table 1, AND2 and AND3 of the AND gate
Output the signals shown in the same row as the count control signals S ₀ and S ₁ , respectively. Explaining the top row of Table 1, When both the MSB and MSB-1 are 0, NOR2 of the NOR gate outputs 1 and AND1 of the AND gate outputs 0 to the one-clock latch circuit 25a. One clock latch circuit 25a When the outputs of NOR2 and AND1 are input, 1 of the output of NOR2 previously input is output to NAND2 of the NAND gate, and 0 of the output of AND1 is output to NAND1 of the NAND gate. NAN
D1 and NAND2 Of the output of NOR2 and 1 of the output of AND1 due to both the MSB and MSB-1 being 1 are also input. Thereby, NAND1 outputs 1 and NAND2 outputs 0. NAND3 of the NAND gate to which both outputs are input outputs 1 to AND2 of the AND gate. The output 0 of NAND2 is also input to AND3. Since 1 of the signal is also input to AND2 and AND3, AND2 outputs ₁ as S0 and AND3 outputs ₀ as S1. The same applies to the second and subsequent columns of Table 1, When the MSB, MSB-1 is 0,1, or 1,0 Always the S _0, S ₁ is 0 and 1 when the MSB, MSB-1 is 0, 1 or 1,0. When the ▲ ▼ signal is 0, both S ₀ and S ₁ become 0. This signal is not limited to the same signal as that input to the clear circuit 24, but may be another signal.
0,0 of the counter control signals S ₀ , S ₁ clears the binary counter 26 to 0, 1,1 counts up, 1,0 counts down, 0,1 parallel input / output of the binary counter 26. This is a load that short-circuits and does not count.

In the discriminating circuit 25 shown in FIG. 6, the memory 22 stores a value representing 2π in 8 bits, so that one count of the binary counter 26 corresponds to 2π, and the interval between the sequentially read values, that is, As shown in the Lissajous graph of FIG. 7 under the condition that the difference is always equal to or less than π / 2, Is the fourth quadrant, There than 0 in the direction of the change from P ₁ to P _2, Is the first quadrant, There is to determine from 0 ₁ and beyond the 0 in the direction of the change to Q _2. Therefore, in this case,
It is necessary that the frequency of R sin θ and R cos θ, that is, the rate of change of α be 1/4 or less of the clock (CK) frequency for reading values.

Therefore, the up / down determination circuit 25 in FIG.
Even if the frequency of cosθ becomes twice as described above, the determination is performed. Under the condition that the difference is always less than or equal to π, as shown in the Lissajous graph of FIG. Of the phase difference between But greater than 0 in the direction of the change from P ₁ to P _2, Is the first or second quadrant, If it is bigger, There is for determining that exceeds the 0 in the direction of the change from Q ₁ to Q _2. The operation of the determination circuit 25 will be described below with reference to the truth table of Table 2.

The one-clock latch circuit 25b in FIG. And the next clock When you enter Is input to NOR3 of NOR gate and AND4 of AND gate, and is inverted by INV1 of inverter and returned to the output of 1 clock latch circuit 25b. Convert to this Is input to the size comparator 25c, and the size comparator 25c is shown in Table 2. Outputs a signal of 1 of YES or 0 of No to NOR3, AND4 and NAND4 of the NAND gate. NAND4 from INV1 The inverted signal of the MSB is also input. Therefore, Is the _value in the first or second quadrant based on ₀ , MSB is 0 as shown in the first to fourth rows of Table 2, MSB inverted Is 0 as shown in the first and third rows of Table 2, NAND4
Input is 1,0, so the output up / down signal is 1
The input of NOR3 is 0,0, the output is 1, the input of AND4 is 0,0, and the output is 0.
▼ The signal becomes 0. Also Is 1 as shown in the second and fourth rows of Table 2, NAND4
Input is 1,1 so the up / down signal is 0, NOR3
Are 0 and 1 and the output is 0, and the input of AND4 is 0 and 1 and the output is 0.

Is in the third or fourth quadrant, MSB of 1 is 1 as shown in columns 5 to 8 of Table 2, Is 0 as shown in the fifth and seventh rows of Table 2, NAND4
Input becomes 0,0, so the output up / down signal is 1
The input of NOR3 is 1,0, the output is 0, and the input of AND4 is 1,0
And the output is 0, so that the output of NOR4 becomes 1 with the ▲ ▼ signal. Also Is 1 as shown in the 6th and 8th rows of Table 2, NAND4
Input is 1,0, so the up / down signal is 1, NOR3
, The input is 1,1 and the output is 0, and the input of AND4 is 1,1 and the output is 1, so ▲ is 0. As a result, the counter control signals shown in Table 2 are obtained, and the combination of the up / down signal and the ▲ ▼ signal, 1,1, causes the binary counter 26 to count up, and the combination of 0,1 causes the downcount, 1,0 Is a load for short-circuiting the parallel input / output of the binary counter 26 to prevent counting.

The up / down determination circuit 25 is a binary counter 26
Since it is important to output a stable counter control signal, the one-clock latch circuits 25a and 25b shown in FIGS. 6 and 8 are operated at the rising edge of the CK signal to satisfy the requirement. Should be operated at the falling edge. In addition, the binary counter 26 has the LS of the count value n.
B is Since it is one MSB higher than the value, n and In a list of values Will be shown.

Returning to FIG. 1, 27a is the output of the clear circuit 24. A latch circuit for holding the value and the count n of the binary counter 26, a latch circuit 27b for holding the R value of the output of the R memory 23, and 28a for the latch circuit 27a Output buffer that outputs the value and n value, 28b is a latch circuit 27b
Output buffer, I ₁ ~I ₃ for outputting the held R values in the buffer, OR1, OR @ 2 is OR gate, NOR1 is a NOR gate. N value output from output buffer 8a From the value, θ is obtained as described above.

In the illustrated example, the upper two bits of the R value output from the R memory 23 become 0 in consideration of the case where the amplitudes of R sin θ and R cos θ fluctuate and decrease, and the accuracy of the obtained θ decreases. , A warning signal ALARM is output via NOR1 and OR1, and a warning is issued. Also, when the amplitude of R sin θ, R cos θ increases to exceed the maximum allowable value of the A / D converters 21a, 21b, the overflow signal OF is output from the A / D converters 21a, 21b, and OR2, ALARM is output via OR1 and a warning is issued. Further, when the MSB of the R value output from the R memory 23 becomes 1, as described above, R sin θ, R cos
Since θ overflows, ALARM is output via OR1 and a warning is issued.

 Hereinafter, more specific examples will be described.

The A / D converters 21a and 21b use an 8-bit MP-7684 manufactured by Micro Power Systems, and the memory 22 and the R memory 23 are 64K bytes and 45nsec SRAM memory of Fujitsu MB8.
1C84A-45 was used. These costs were 1/4 that of using a CPU. The memory 22 stores a value represented by 8 bits of 0 ≦ θ <2π, and the R memory 23 stores an R value represented by 8 bits. The A / D converters 21a and 21b of the switching capacitor type were driven at 13 MHz, and an 8-bit value and an R value were obtained from the memory 22 and the R memory 23 in a processing time of 13 MHz. The resolution of the 8-bit value was 2π / 256 as long as the upper two bits of the R value were not both zero. An IC composed of four high-speed TTL circuits is used for the clear circuit 24 and the latch circuit 27a at the subsequent stage. This reliably performed a clear function against a change in the value of 16 MHz. The up-down control circuit 25 was configured as shown in FIG. 6, and a counter IC was used for the one-clock latch circuit 25a. Then, 74AS869 was used for the binary counter 26. As a result, up / down was determined without any problem at a CK frequency of 16 MHz, and n could be counted. According to this, it is possible to follow the changing speed up to 4 MHz of R sin θ and R cos θ. The same applies to the case where one clock latch circuit 25a and two D latch circuits connected in series are used. The up / down determination circuit 25 is configured as shown in FIG.
The same one as the one 25a was used for the one-clock latch circuit 25b, and the 74F686 was used for the magnitude comparator 25c. And binary counter 26
The counter array 74F669 was used. This gives 16MH
Up / down was similarly discriminated at the CK frequency of z, and n could be counted. According to this, it is possible to follow the change speed up to 8 MHz with respect to the phase change of R sin θ and R cos θ of π. This is because the magnitude comparator 25c inverts the output using a one-clock latch circuit and a D-latch circuit, and operates as in a clear circuit.
It does not change even if the calculation is performed by F283 or the like and the carry C8 is monitored.

The up / down discriminating circuit 25 as shown in FIG. 6 and FIG.
This is a very efficient logic system that can be stored in the programmable array logic (PAL).
Where P3 is required, it can be accommodated in one PAL, and miniaturization and power saving can be realized. A / D converters 21a, 2
If the 1b and later are converted to LCA, further miniaturization, power saving and high reliability can be easily obtained.

In the above signal processing circuit, all circuits are 13 MHz.
It was possible to drive stably with z, and to obtain θ with a phase resolution of 2π / 256. This is because conventional displacement gauges have a processing speed of at most about 2 MHz, and have a maximum accuracy of 2π / 1.
Given that the phase resolution is about 27, the accuracy is 6 times or more and the accuracy is 2 times or more. Further, in the signal processing circuit of the embodiment, only the gain adjustment is performed on the input signal, and since there is no other analog circuit at all, the non-linearity of the phase count value does not occur electrically. Excellent effects that are not available in the law can also be obtained.

〔The invention's effect〕

In the displacement meter of the present invention, the signals of R sin θ and R cos θ obtained from the displacement of the movable object are not calculated in real time as in the conventional displacement meter to obtain θ, and R
The signal of sin θ, R cos θ is used to read out a corresponding value from a memory storing a digital value of θ of 0 ≦ θ <2π, which is obtained in advance, and is used as a value up / down discrimination counting means. Even if the value does not become 0, it uses a means that can determine in which direction the value has exceeded 0 and count based on it. Therefore, it is necessary to obtain θ at high speed and with high accuracy corresponding to a fast α change speed. In addition, an excellent effect that the signal processing circuit can be configured at low cost and compactly and power consumption can be reduced can be obtained.

[Brief description of the drawings]

FIG. 1 shows a signal processing circuit 1 used in the displacement meter of the present invention.
FIG. 2 is a Lissajous graph of R sin θ and R cos θ; FIGS. 3 and 4 are memory graphs showing examples of memory contents of a memory and an R memory;
6 is a block circuit diagram showing an example of a clear circuit, FIGS. 6 and 8 are block circuit diagrams showing an example of an up / down discriminating circuit, and FIGS. 7 and 9 are FIGS. 6 and 8, respectively. Lissajous graph for explaining the function of the discriminating circuit. FIG. 10 is a schematic configuration diagram showing an example of a displacement meter. DESCRIPTION OF SYMBOLS 1 ... Stabilized laser, 2 ... Beam splitter 3 ... λ / 8 plate, 4 ... Fixed corner cube 5 ... Moving corner cube 6 ... Polarized beam splitter 7 ... Filter, 8 ... Polarizer 9 ... ... Detector, 10 ... Amplifier 11 ... Operational amplifier, 12 ... Signal processing circuit 21a, 21b ... A / D converter, 22 ... Memory 23 ... R memory, 24 ... Clear circuit 24a ... Transparent Latch circuit 24b Full adder 25 Up / down determination circuit 25a, 25b 1-clock latch circuit 25c Large / small comparator, 26 Binary counter 27a, 27b Latch circuit 28a, 28b Output buffer

Claims (3)

(57) [Claims] 1. A method according to claim 1, wherein the amount of movement of the movable object in one direction is R sin θ,
An electric signal changing at R cos θ (where θ = 2πα / S, S is a predetermined cycle) is obtained, and a digital signal obtained by digitally converting the two signals is read out as a read signal. The corresponding value is read out from the memory storing various values (where the value is a digital value of 0 ≦ = θ−2nπ <2π, and n is a count number described later) corresponding to the combination, and the value increases. Counting the number of decrease or increase from decrease to obtain n,
This is a displacement meter that obtains θ from a value and n, and is read out when n is set to 0 when the interval between sequentially read values is set to π / k (where k is 2 or 1) or less. The difference between the read value and the value read at The difference between the next read value and When k is set to 2, Counts up when is in the first quadrant, Is the value of the quadrant of the first quadrant, Is counted in the fourth quadrant, and counting is performed by using up / down discriminating counting means that does not count otherwise.
When is set to 1, Phase difference by π Up count when smaller, A displacement meter using up / down discriminating counting means for counting down when it is larger and not counting otherwise. 2. The displacement meter according to claim 1, wherein said movable object is a moving reflection object of a laser length meter. 3. The displacement meter according to claim 1, wherein said movable object is a scale plate having a portion to be detected at an equal pitch, such as a rotary encoder or a linear encoder.