JP2767107B2 - Frame format conversion method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame format conversion method suitable for transferring data between different frame formats on a high-speed digital line having a predetermined transmission speed.

[Summary of the Invention]

The present invention provides a coded mark-in version (Coded Ma
rk Inversion: 24 multi-frame format using codes or alternate mark inversion (Alternate)
Mark Inversion: A frame format conversion method for converting a 12 multi-frame format using a code into an AMI code 12 multi-frame format (or a CMI code 24 multi-frame format) using an AMI code. Simple configuration by adding a plurality of multi-multiframe service or / and maintenance control information with 12 multiframes as one cycle to the twelfth frame synchronization bit of the multiframe. Enables transmission,
Further, service information and maintenance control information can be transferred between frames.

[Conventional technology]

Conventionally, the input “0” is changed to “01” and the input “1” as the coding rule.
The data of 24 multi-frame format using the so-called CMI code that alternately converts “00” and “11” into “1”
A so-called AMI code is used in which the DC component is suppressed by alternately sending positive and negative codes each time a signal occurs.
As shown in FIG. 5, there is a high-speed digital line for converting data into a multi-frame format, which is generally used, for example, by companies operating in the telegraph and telephone industries.

In FIG. 5, (1) shows a data terminal device (Digital
Terminal Equipment (hereinafter simply referred to as DTE), (2) Metallic cable as high-speed digital line, (3)
Stands for Digital Service Unit
t, hereinafter simply referred to as DSU), which are generally installed at the home of the user (subscriber). DTE (1) and DSU (3)
During this period, data is transferred using a CMI code in a 24-multiframe format as shown in FIG. 6 at a predetermined transmission rate, for example, 1.544 Mb / s.

(4) is, for example, an optical fiber cable as a high-speed digital line, (5) is a telephone office (or a relay station, etc.), and the transmission speed of data transmitted through the optical fiber cable (4) is also 1.544 Mb / s. It is. The data format is also a 24-multiframe format, but the transmission code format is a CMI code. Although not shown, the transmitted CMI code data of the 24 multi-frame format is not shown in the drawing.
l, hereinafter simply referred to as SLT), and furthermore, the transmission rate of each of the second, third, fourth, and fifth groups of multiplexers.
It is sequentially multiplexed with 6 Mb / s, 32 Mb / s, 100 Mb / s, and 400 Mb / s, and is transmitted to the other telephone station (7) at a remote place via an optical fiber cable (6).

The telephone station (7) reversely transmits the transmitted 400 Mb / s data in the fifth, fourth, third and second groups of the multiplexer in order of 100 Mb / s, 32 Mb / s, 6 Mb / s, It is multiplexed and demultiplexed to a transmission rate of 1.544 Mb / s, and put on a 1.544 Mb / s high-speed digital line, for example, an optical fiber cable (8) from the SLT, and the other DS
The data is transmitted to U (9), and further transmitted to DTE (11) via a metal cable (10) as a high-speed digital line. Of course, also in this case, 1.544Mb / s between the telephone office (7) and DSU (9).
The CMI code is used in the 24 multiframe format, and the CMI code is used in the 1.544 Mb / s24 multiframe format between the DSU (9) and the DTE (11).

FIG. 6 shows a 24 multi-frame format using the CMI code. That is, the frame configuration is shown in FIG.
As shown in the figure, one frame is composed of 24 channels of data with one channel being 8 bits, and 1 bit of X bits added to the leading end thereof.
44 Mb / s). In addition, 24 multiframes are configured as shown in FIG. 6B in which 24 of these frames are combined into one cycle. FIG. 6C shows the structure of X bits.
The upper column represents a received signal (DSU → DTE), and the lower column represents a transmitted signal (DTE → DSU). When receiving from DSU to DTE, F is inserted into frame 1, DNR is inserted into frame 17, UNR is inserted into frame 19, S is inserted into frame 21, and SEND is inserted into frame 23.
F to frame 1 when transmitting from DSU to DSU, frame 21
, And the X bits of the other frames are undefined bits.

Here, DNR, UNR, SEND, and S are all service information, and F is a multiframe synchronization bit. And the DNR (DCE N
ot Ready) indicates a line failure or a temporarily degraded state (instantaneous interruption, burst error, etc.), and UNR (DTE Uncontralled Not Re
ady) indicates a transmission signal loss or out-of-synchronization state between the partner DTE and the DSU, and S (Stataus) indicates a line use state.

Conventionally, for example, a power company or the like has transmitted control information of an unmanned station, online information of a business office, fax information for office use, and the like using a power line as shown in FIG.
That is, in FIG. 7, (12) is a terminal device, (13) is a metal cable as a high-speed digital line, (14) is a power communication room, and an AMI code is used for the metal cable (13). Speed
Transmission is performed at 1.544 Mb / s in a 12-multiframe format as shown in FIG. In the power communication room (14), the data of the 12 multi-frame format of the AMI code transmitted at the transmission speed of 1.544 Mb / s is not shown, but the secondary group, the third group, and the fourth group of the multiplexer each have 6 Mb. / s, 32Mb / s, 100Mb / s
Fiber optic cable (15) multiplexed sequentially to the transmission speed of
To the other power communication room (16) at a remote location.

In the power communication room (16), the transmitted 100 Mb / s data is sequentially reversed in the fourth, third, and second groups of the multiplexer.
It is multiplexed and demultiplexed into transmission rates of 32 Mb / s, 6 Mb / s and 1.544 Mb / s, and transmitted to the other terminal device (18) via a metal cable (17) as a high-speed digital line. Of course, also in this case, the distance between the power communication room (16) and the terminal device (18) is 1.544 Mb / s12.
Uses AMI code in multi-frame format.

The 12 multi-frame format using the AMI code is as shown in FIG. That is, the frame configuration is shown in FIG.
As shown in FIG. 6, the same as FIG. 6A described above, but only the frame synchronization bit F is inserted at the head. As shown in FIG. 8B, the multi-frame configuration is a 12-multi-frame configuration in which twelve frames are combined into one cycle. As shown in FIG. 8C, the frame synchronization bit F is inserted with the corresponding [10001101110] bit in each of the frames FR1 to FR11. A game alarm bit indicating the occurrence of a reception error at the partner station is inserted.

[Problems to be solved by the invention]

By the way, DTE (1), (1
1) can transmit electronic mail, can transmit a circuit drawing or the like to a large size with high accuracy, or can transmit information read from an optical disc, and can transmit multi-functions. ) And (11) are desired to be used for the terminal devices (12) and (18) in FIG.

However, as described above, the frame format used by DTEs (1) and (11) is 1.544 Mb using the CMI code.
Since this is a 24 multi-frame format of / s, the power line using the 12-frame format of 1.544 Mb / s using the AMI code has a drawback that DTE (1) cannot be used as it is.

In addition, the AMI code used for power lines is used.
In the multi-frame format, although there is no surplus bit, as can be seen from FIG. 8, the game information can be transmitted.
The service information used in the 24-multiframe format using the CMI code as shown in FIG. 6 cannot be transmitted.

The present invention has been made in view of such a point, and a DTE for processing data in a 24 multi-frame format using a CMI code is installed in a power digital line for transmitting data in a 12 multi-frame format using an AMI code. It is another object of the present invention to provide a frame format conversion method capable of mutually transmitting not only data but also service information and the like.

[Means for solving the problem]

The frame format conversion apparatus according to the present invention includes a CM
This is a frame format conversion method for converting a 24 multi-frame format using I into a 12 multi-frame format using an AMI code, wherein the 12-frame synchronization bit of the 12 multi-frame using the AMI code has 12 multi-frames. A plurality of multi-multi-frame service or / and maintenance control information bits having one frame as one cycle are added, and the second invention uses the AMI code.
A frame format conversion method for converting a 2 multi-frame format into a 24 multi-frame format using a CMI code, wherein one synchronizes 12 multi-frames with a twelfth frame synchronization bit of a 12 multi-frame using an AMI code. A plurality of multi-multi-frame service or / and maintenance control information bits are added.

[Action]

Data terminal equipment (1,11) and digital line (13,17)
Between the first multi-frame format, ie CM
A first interface unit (20A) associated with the 24 multi-frame format using the I code and a second interface unit (20B) associated with the second multi-frame format, that is, the 12 multi-frame format using the AMI code. Provide. Then, the first multi-frame format and the second multi-frame format are mutually converted between these interface units. Thus, the data terminal device (1, 11) that processes data of the first multi-frame format using the CMI code substantially uses the AMI code, and uses the second multi-frame format having a different number of frames from the first multi-frame format. The equipment can be connected to digital lines (13, 17) that transmit multi-frame format data, and the power lines can use conventional digital lines (13, 17), thus reducing equipment costs. And multi-function information transmission. In addition, service information that was transmitted in a 24-multiframe format using CMI codes
It can be transmitted in a 12-multiframe format using codes.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS.

First, an example in which the frame format converter (20, 21) according to the present invention is applied to a power line as shown in FIG. 7 will be briefly described with reference to FIG. In FIG. 2, parts corresponding to those in FIGS. 5 and 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 2, a frame format converter (20) is inserted between the cables (2) and (13), and a frame format converter (21) is inserted between the cables (10) and (17). Of course, the frame format converters (20) and (21) are exactly the same. The frame format converters (20) and (21) have a transmission rate of 1.544 using the CMI code transmitted from the DTEs (1) and (10) via the cables (2) and (10), respectively.
The Mb / s 24 multi-frame format is converted to a 1244 multi-frame format using AMI code at a transmission speed of 1.544 Mb / s, and the power communication room (14) and the power communication room (14) are connected via cables (13) and (17) respectively. Transmit to (16).

As a result, electronic mail, high-precision drawings and optical disk information that could not be transmitted conventionally can be transmitted on this power line, and conventional metal cables (13, 17) as high-speed digital lines can be used as they are. This is advantageous in terms of equipment costs.

FIG. 1 shows an example of a frame format conversion device according to the present invention. The frame format conversion device (20) shown in FIG. 2 will be representatively described. In the figure, (20A) is a CMI24 multiframe interface unit that handles data in a 24 multiframe format using a CMI code, and (20B) is an AMI12 multiframe interface unit that handles data in a 12 multiframe format using an AMI code. is there.

(21) is connected via cable (2) to DTE (1) (second
Fig.) Receiver for receiving CMI24 multi-frame data transmitted from (), (22) is a remote loop circuit, (23)
Is a conversion circuit for converting the CMI24 multi-frame data into an NRZ signal, (24) is a clock extraction circuit for extracting a clock signal having a predetermined frequency, for example, 3.088 MHz from the CMI24 multi-data, and (25) is a "0" of the CMI24 multi-frame data. A predetermined frequency such as 1.54 so that the rise matches the fall
A clock generator that generates a 4 MHz clock signal, (26)
Is a CMI synchronization detection circuit that synchronizes the output of the built-in 8kHz counter with the 24 multi-frame synchronization signal after detecting the 24 multi-frame synchronization from the CMI, CRV (Code Rule violation) signal, (2
7) is a separation circuit for separating the service information included in the CMI24 multi-frame data, for example, the terminal device use state transfer bit S, and (28) and (29) are jitter and frame phase absorption circuits using an elastic store. .

(30) is a CMI 24 multi-frame pattern generation circuit, (31) is a service information insertion circuit, (32) is a conversion circuit that converts an NRZ signal into CMI 24 multi-frame data,
(33) is a transmitter for transmitting the converted CMI24 multi-frame data to the DTE (1) (FIG. 2) via the cable (2). (34) is an external input terminal to which a clock signal is supplied from outside, and (35) is 1.54 in synchronization with a clock signal of a predetermined frequency, for example, 1.544 MHz from the external input terminal (34).
Oscillator circuit that generates a 4MHz clock signal. (36) AMI1
(2) The phase is synchronized with a clock signal of a predetermined frequency, for example, 1.544 MHz from the multi-frame interface unit (20B).
A phase-locked oscillation circuit that generates a 4 MHz clock signal, (3
7) is a switch that is switched to the oscillation circuit (35) when the device (20) acts as a master with respect to the frame format conversion device (21) on the other side, and is switched to the oscillation circuit (36) when it acts as a slave. It is. These (2
1) to (37) constitute the CMI24 multiframe interface unit (20A).

(38) is a 12 multi-frame pattern generator for AMI,
(39) is a service / maintenance control information insertion circuit, (40) is a scramble circuit, (41) is a switch, and (42) is 8
When bits “0” are consecutive, they are replaced with a specific pattern, so-called B8ZS (Bipolar with 8 Zeros Substitutio).
n) B8ZS encoding circuit for encoding the code, (43) is a switch. The scrambling circuit (40) and the B8ZS encoding circuit (42) are inserted into the transmission line when it is necessary to prevent "0" continuation on the transmission line. (44) is a manual loop circuit, (45) is a U / B conversion circuit that converts unipolar pulses (unipolar) to bipolar pulses (bipolar), and (46) is a cable (13) for AMI12 multi-frame data. A transformer for transmitting to the power communication room (14) (FIG. 2) via the cable (13), and the transformer (47) receives the AMI12 multi-frame data transmitted from the power communication room (14) via the cable (13). Transformer, (4
8) is a B / U conversion circuit that converts a bipolar pulse into a unipolar pulse.

(49) is a B8ZS decoding circuit, (50) is a switch,
(51) is a descramble circuit, (52) is a switch, (5
3) is a clock extraction circuit that extracts a 1.544 MHz clock signal from received data, (54) is a synchronization detection circuit that performs frame synchronization and multi-frame synchronization detection, and (55)
Is a service / maintenance control information separation circuit. These (2
8), (29) and (38) to (55) constitute the AMI12 multi-frame interface unit (20B).

FIG. 3 shows an AMI12 multi-frame format used in this embodiment. The frame configuration is the same as FIG. 6A as shown in FIG. 3A. Multi-frame configuration is 3rd
As shown in FIG. B, as in FIG. 8B, there are 12 multi-frame configurations in which 12 frames are grouped into one cycle. And X
The bit configuration is substantially the same as the F-bit configuration in FIG. 8C as shown in FIG. 3C, except that the twelfth multi-frame bit is further configured as a MMF1-6 MMF6. That is, the twelfth multi-frame bit has a multi-frame configuration of MMF1 to MMF6 as shown in FIG. 3D, a multi-frame synchronization bit MMSY is inserted into MMF1, and a terminal device use state transfer is transmitted to MMF2. Bit S is inserted into the MMF3, and the terminal device transmission abnormal state transfer bit UN
R is inserted, AMI reception abnormal transfer bit SEND is inserted into MMF4, remote loop bit TST between frame format converters is inserted into MMF5, and MMF6 is a spare bit. In this way, by further setting the twelfth multi-frame bit of the 12 multi-frames to have a 6-multi-frame configuration, service information can be transferred between 24 multi-frames and 12 multi-frames up to 5 items in this case.
Note that this multi-frame configuration may be further increased if the transfer speed permits.

Next, the circuit operation of FIG. 1 will be described. CMI24 received by the receiver (21) from the DTE (1) via the cable (2)
The multi-frame data passes through a loop (22), a conversion circuit (23), a clock extraction circuit (24), and a synchronization detection circuit (2).
6) supplied to. The clock extracting circuit (24) extracts a clock signal of 3.088 MHz from the CMI24 multi-frame data and supplies it to the clock generating circuit (25). The clock generation circuit (25) supplies a 1.544 MHz clock signal to the falling edge of "0" of the CMI24 multi-frame data and supplies it to the phase absorption circuit (28).

In addition, the synchronization detection circuit (26) detects the output of the built-in 8kHz counter after detecting 24 multiframe synchronization from the CMI CRV signal.
The signal is synchronized with the 24 multi-frame synchronization signal and supplied to the separation circuit (27) and the phase absorption circuit (28). Conversion circuit (23)
Then, the CMI24 multi-frame data is converted into an NRZ signal and supplied to a separation circuit (27) and an absorption circuit (28). The separation circuit (27) separates the terminal device use state transfer bit S from the NRZ signal in response to the 24 multiframe synchronization signal, and supplies it to the insertion circuit (29).

Supplied from the conversion circuit (23) to the phase absorption circuit (28)
The data of the NRZ signal is 1.544 from the clock generator (25).
This clock is written based on the clock signal of MHz and the 24 multi-frame synchronization signal from the synchronization detection circuit (26), and the clock signal of 1.544MHz from the phase synchronization oscillation circuit (36) (when this device works as a slave) and this clock The head data of the frame is read out in synchronization with the 8 kHz clock signal from the pattern generation circuit (38), which is 1/193 of the signal, whereby the synchronization information on the CMI side is separated here.

The data read from the phase absorption circuit (28) is supplied to the insertion circuit (39), where a 12 multi-frame pattern is generated by the pattern generation circuit (38) for the insertion circuit (39), The synchronizing signal for 12 multiframes from the generating circuit (38), that is, [1000110111] in FIG.
0] is inserted, a multi-frame synchronization bit of the twelfth multi-frame bit is inserted, a remote loop bit TST between the frame format converters is inserted, and a separation circuit from the interface unit (20A) is inserted. A terminal device use state transfer bit S output from (27) and a terminal device abnormal transmission state transfer bit UNR output from the synchronization detection circuit (26) are inserted.

The data from the insertion circuit (39) having the 12 multi-frame configuration is scrambled by the scramble circuit (40) when it is necessary to prevent the continuation of "0" on the transmission line, and the B8ZS encoding circuit ( At 42), a process of B8ZS encoding is performed and supplied to the U / B conversion circuit (45) through the loop circuit (44). Then, the unipolar pulse is converted into a bipolar pulse and transmitted as AMI12 multi-frame data from the transformer (46) to the power communication room (14) via the cable (13).

On the other hand, the AMI12 multi-frame data transmitted from the power communication equipment room (14) via the cable (13) is converted from a bipolar pulse into a unipolar pulse by a conversion circuit (48) to become an RZ signal. This RZ signal passes through the loop circuit (44) and is decoded by the B8ZS decoding circuit (49) when the other party's transmission side is B8ZS-encoded, and is descrambled when the other party's transmission side is scrambled. ) Is decoded into an NRZ signal. This NRZ signal is output to the synchronization detection circuit (5
4), supplied to the separation circuit (55) and the phase absorption circuit (29).

The clock extraction circuit (53) is 1.544M higher than the RZ signal.
A clock signal of Hz is extracted and supplied to a synchronization detection circuit (54), a phase absorption circuit (29), and a phase synchronization oscillation circuit (36). The synchronization detection circuit (54) performs frame synchronization and multi-frame synchronization detection in response to the clock signal from the clock extraction circuit (53), and supplies the synchronization signal to the phase absorption circuit (29) and the insertion circuit (39). At the same time, the signal is supplied to the insertion circuit (31) via the phase absorption circuit (29). The separation circuit (55) separates service / maintenance control information from the data supplied in synchronization with the synchronization signal from the synchronization detection circuit (54). The separated service information is supplied to an insertion circuit (31), and the maintenance control information TST is supplied to a loop circuit (22).

The data supplied to the phase absorption circuit (29) via the switch (52) includes an 8 kHz clock signal generated from the synchronization signal detected by the synchronization detection circuit (54) and 1.544 extracted by the clock extraction circuit (53). Synchronizes the frame top data with the 1.544 MHz clock signal written by the MHz clock signal, passed through the switch (37), and the 8 kHz clock signal from the pattern generator (30) formed by counting down to 1/193. And then read
The synchronization information on the I side is separated.

The data read from the phase absorption circuit (29) is supplied to an insertion circuit (31), where a 24 multi-frame pattern is generated by a pattern generation circuit (30) for the insertion circuit (31). The 24-multiframe synchronization signal F from the generation circuit (30), the service information from the interface section (20B), and the AMI reception abnormal transfer bit SEND from the synchronization detection circuit (26) are inserted.

The data from the insertion circuit (31) having a 24-multiframe configuration is converted by the conversion circuit (32) from the NRZ signal to C data.
The signal is converted to the MI code, passes through the loop circuit (22), and is transmitted to the transmitter (3
3) The data is transmitted to the DTE (1) side via the cable (2).

FIG. 4 shows an outline of the service / maintenance control information bit transfer. In FIG. 4, () in the high-speed digital circuit section indicates bits used in the multi-multiframe (MMF) of the AMI12 multiframe. Indicates a lamp display, and an x indicates an input disconnection or a line abnormality.

First, the DNR will be described. The DNR viewed from the DTEs (1) and (11) is calculated based on the frame format converters (20) and (2).
This indicates that the input of the AMI12 multi-frame signal in 1) is not performed, or that the frame format converters (20) and (21) cannot obtain synchronization even though the AMI12 multi-frame signal is input.

The transfer method uses a frame format converter (2
0) If there is no AMI input or synchronization is lost, DTE
(1) CMI24 multi-frame X-bit frame 17
Is changed from “0” to “1” to transfer the DNR. DTE
The DNR transfer to (11) uses a normal downlink, changes the bit SEND of MMF4 in the AMI12 multiframe from “0” to “1” and sends it to the frame format converter (21).
The conversion device (21) transfers the DNR to the DTE (11) by changing the XTE frame 17 of the CMI24 multi-frame for DTE (11) transmission from "0" to "1".

Next, the SEND viewed from the DTEs (1) and (11) is determined by the frame format converters (20) and (21) when there is no input of a CMI24 multi-frame signal or by the frame format converters (20) and (21). This indicates that CRV synchronization cannot be achieved despite the input of a multi-frame signal.

The transfer method is a frame format converter (2
If no CMI24 multi-frame signal is input or CRV synchronization is not achieved in (0) and (21), the converters (20) and (21) transmit the X bits of the CMI24 multi-frame transmitted to the DTEs (1) and (11), respectively. Is changed from “0” to “1” and SEND is transferred.

Next, the UNR as seen from DTE (1) and (11) is determined by the opposite frame format converter (20) and (21).
This indicates that there is no input of the CMI24 multi-frame signal, or that CRV synchronization cannot be achieved even if there is an input.

The transfer method is a frame format converter (2
If there is no CMI24 multi-frame signal input or CRV synchronization cannot be achieved in (0) and (21), the conversion devices (20) and (21)
Changes the bit UNR of MMF3 in the AMI12 multiframe from “0” to “1” and sends it to the conversion devices (21) and (20) on the other side. On the other hand, AMI where bit UNR of MMF3 changed from “0” to “1”
Converters (21), (2) that received 12 multi-frame signals
0) changes the XR frame 19 of the CMI24 multiframe X bit from “0” to “1”, thereby setting the UNR to DTE (1
Transfer to (1) and (1).

Next, the S bit notifies the use state of DTE (1), (2) to DTE (2), (1) on the other side. The transfer method is CMI24 output from DTE (1) and (2) when the terminal is in use.
The multi-frame X-bit frame 21 is sent to the frame format converters (20) and (21) as "1". The conversion devices (20) and (21) send the bit S of MMF2 in the AMI12 multi-frame as "1" and send it to the conversion devices (21) and (20) of the other party. On the other hand, the converters (21) and (20) that have received the AMI12 multiframe signal respectively set the CMI24 multiframe X-bit frame 21 to be “1” to “1”.
Transfer to DTE (11), (1).

Next, the operation relating to the TST will be described with reference to FIG.
First, in the case of manual operation, a manual loop circuit (44) is used,
The AMI12 multi-frame signal supplied from the AMI through the transformer (47) is converted from bipolar to unipolar by the conversion circuit (48), turned back by the loop circuit (44), and supplied to the conversion circuit (45), where it is unipolar. -The signal is bipolar-converted and returns to the AMI via the transformer (46). The CMI24 multi-frame signal transferred from the CMI side passes through the loop circuit (22) from the receiver (21), is subjected to signal processing by the phase absorption circuit (28), etc., and becomes an AMI12 multi-frame signal to become the loop circuit (44). And the phase absorption circuit (2
The signal is subjected to signal processing in 9) and the like, and again becomes a CMI24 multi-frame signal, and returns to the CMI side from the transmitter (33) via the loop circuit (22).

In the case of remote operation, a remote loop circuit (22)
The CMI24 multi-frame signal supplied from the CMI side via the receiver (21) is looped back by the loop circuit (22) and returns to the CMI side via the transmitter (33). Also, the AMI12 multi-frame signal transmitted from the AMI side passes through a transformer (47), passes through a conversion circuit (48), passes through a loop circuit (44), is subjected to signal processing by a phase absorption circuit (29), etc.
It becomes an I24 multi-frame signal, looped back by the loop circuit (22), processed by the phase absorption circuit (39), etc.
The signal becomes a multi-frame signal and returns to the AMI side from the transformer (46) via the loop circuit (44) and the conversion circuit (45).

In the case of this remote operation, the bit TST of the MMF5 in the AMI12 multiframe described above is used. That is, when the remote loop switch (not shown) is turned on by the frame format converter (21) in FIG. 4, the bit TST of the MMF5 in the AMI12 multi-frame is changed from “0” to “1” by the converter (21). It changes and sends it to the frame format converter (20). Upon receiving the AMI12 multi-frame signal, the frame format converter (20) performs the above-described remote operation by watching the change of the remote loop bit TST from “0” to “1”.

In the above-described embodiment, the CMI24 multi-frame signal and A
MI12 multi-frame signal conversion, but CMI24
The same applies to the case of conversion between a multi-frame signal and a B8ZS12 multi-frame signal.

Further, in the above embodiment, the present invention is applied to a power line, but the present invention is not limited to this, and can be applied to other lines requiring similar format conversion.

〔The invention's effect〕

As described above, according to the present invention, a data terminal device that processes data of a first multi-frame format using a CMI code and a data terminal device that uses at least an AMI code and has a different number of frames from the first multi-frame format The first multi-frame format and the second multi-frame format are mutually converted between a digital line for transmitting data of the second multi-frame format, so that data of different formats can be transmitted to each other. For example, when the present invention is applied to an electric power line, a digital line or the like which has been conventionally used can be used as it is, so that equipment costs and the like can be reduced, and multifunctional information can be transmitted. In addition, service information transmitted in the first multi-frame format using the CMI code can also be transmitted in the second multi-frame format using the AMI code, and furthermore, maintenance control information that was impossible in the past can be transmitted. , It can expand the function.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram of a power circuit to which the present invention is applied, FIG. 3 is a diagram showing an AMI12 multi-frame format according to the present invention, and FIG. FIG. 5 is a diagram showing an outline of service / maintenance control information bit transfer according to the present invention, FIG. 5 is a diagram showing a conventional communication circuit configuration, FIG. 6 is a diagram showing a CMI24 multi-frame format, and FIG. FIG. 8 is a diagram showing a conventional AMI12 multi-frame format. (1) and (11) are data terminal equipment (DTE), (13) and (1)
7) is a high-speed digital line, (20A) is a CMI24 multiframe interface unit, (20B) is an AMI12 multiframe interface unit, and (20) and (21) are frame format converters.

Continuation of the front page (72) Inventor Satoshi Suzuki 1 Higashi-Shinmachi, Higashi-ku, Nagoya City, Aichi Prefecture Inside Chubu Electric Power Co., Inc. (72) Inventor Takashi Endo 7-3-16 Kikuna, Kohoku-ku, Yokohama City, Kanagawa Prefecture Inside Oi Electric Co., Ltd. (56) References JP-A-61-156939 (JP, A) (58) Fields investigated (Int. Cl ^6, DB name) H04J 3/00 -. 3/26 H04L 5/22 - 5/26 H04L 25/49

Claims (3)

(57) [Claims] 1. A frame format conversion method for converting a 24 multi-frame format using a coded mark inversion code into a 12 multi-frame format using an alternating mark inversion code, wherein the method uses the alternating mark inversion code. A frame format conversion method, characterized by adding a plurality of multi-multiframe service or / and maintenance control information bits having one cycle of 12 multiframes to a twelfth frame synchronization bit of 12 multiframes. 2. A frame format conversion method for converting a 12 multi-frame format using an alternating mark inversion code into a 24 multi-frame format using a coded mark inversion code, wherein the method uses the alternating mark inversion code. A frame format conversion method, characterized by adding a plurality of multi-multiframe service or / and maintenance control information bits having one cycle of 12 multiframes to a twelfth frame synchronization bit of 12 multiframes. 3. The multi-multiframe according to claim 1, wherein said multi-multiframe is composed of 6 multi-multiframes.
3. A method for converting a frame format according to claim 2.