JP2766901B2 - Memory test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test device for testing a memory integrated into a semiconductor integrated circuit.

[Prior Art] FIG. 2 shows a configuration of a conventional memory test apparatus. A conventional memory test apparatus includes a pattern generator 1, a programmable data selector 2, a format 3, a driver group 4 for supplying a pattern signal and an address signal to a memory under test 5, and a data read from the memory under test 5. Comparator 6 for comparing with an expected value output from pattern generator 1
When a mismatch is detected by the comparator 6, a 1 is stored at the same address as the address given to the memory under test 5, and a failure analysis memory 7 stores a failure address of the memory 5 under test. You.

Normally, the memory under test 5 is accessed by an address signal output from the pattern generator 1, a pattern signal is written to and read from the accessed address, and the read data is compared with the expected value 6 by the comparator 6. When a mismatch is detected, 1 indicating a failure is written into the failure analysis memory 7 at the same address as the memory 6 under test.

[Problems to be Solved by the Invention] Some memories, such as a FIFO or a SAM of a dual-port memory, receive an external clock and generate an address signal inside the memory.

Conventionally, when testing such a memory, an address signal identical to the address signal generated inside the memory under test is generated by the pattern generator 1, and this address signal is applied to the failure analysis memory 7 to provide the failure analysis data. To be able to remember.

However, the same address signal as the address signal generated inside the memory as described above is applied to the pattern generator 1.
In such a case, a program for operating the pattern generator 1 is complicated, and there is a disadvantage that the production of the program is troublesome.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory test apparatus in which a pattern generator does not need to generate an address signal when a memory under test does not require an address signal.

Means for Solving the Problems According to the present invention, in a memory test apparatus having a structure including a failure analysis memory, a function of taking in an address signal given from a pattern generator as initial data, and an increment from the initial address by supplying a clock are provided. Alternatively, an address pointer having a function of decrementing and a hold function for maintaining the address at a desired address, and one of an address signal output from the address pointer and an address signal output from the pattern generator This is a structure in which a selector is provided for selecting one of them to be provided to the failure analysis memory.

[Operation] According to the configuration of the present invention, when testing a memory that does not require an address signal, the selector selects an address signal output from the address pointer and gives it to the memory under test.

The initial address given to the memory under test is given to the address pointer, and is initialized together with the memory under test. Subsequently, the same clock as the clock applied to the memory under test is applied, and the address is incremented by +1 from the initial address or -1 in synchronization with the clock.
The address signal is supplied to the failure analysis memory through the selector.

Therefore, the failure analysis memory is accessed at the same address as the internal address of the memory under test, and when an address having a failure cell is detected, 1 indicating failure can be written to the address.

As described above, according to the present invention, since the same address as the address generated inside the memory under test is generated by the address pointer, it is not necessary to generate the address signal by the pattern generator. Therefore, there is no need to modify the program for operating the pattern generator, and an advantage is obtained that the labor required for creating the program can be greatly reduced.

FIG. 1 shows an embodiment of the present invention. In the figure, 1 is a pattern generator, 2 is a programmable data selector, 3
Is a formatter, 4 is a driver group, 5 is a memory under test,
6 is the same as the conventional memory test apparatus described with reference to FIG. 2 in that it indicates a comparator and 7 indicates a failure analysis memory.

In the present invention, an address pointer 8 and a selector 9 are added to the failure analysis memory 7.

The address pointer 8 can be constituted, for example, by an up / down counter capable of loading data.

An address signal output from the pattern generator 1 from the address bus and a control signal from the data bus are supplied to the address pointer 8 constituted by the up / down counter.

With this control signal, the address pointer 8 is set to the same condition as the address generator of the memory under test 5.
In other words, the address is incremented by +1 according to the clock input,
In addition, the same address as that of the memory under test 5 is initialized by a load command signal.

The selector 9 switches between a state of selecting an address signal supplied from the pattern generator 1 to the input terminal A by the control signal output from the pattern generator 1 and a state of selecting an address signal supplied to the input terminal B from the address pointer 8. Can be switched.

When a normal memory is tested, the selector 7 selects the input terminal A and supplies an address signal output from the pattern generator 1 to the failure analysis memory 7, but the memory under test 5 does not need to supply the address signal. In the case of an element, the selector 7 is switched to the input terminal B, and the address pointer 8
Is supplied to the failure analysis memory 7. In this way, the failure analysis memory 7 accesses the same address as the memory under test 5, and when the comparator 6 detects a mismatch between the read data of the memory 5 under test and the expected value, the mismatch occurs. 1 indicating a failure can be written to the same address of the failure analysis memory 7 that has been made.

In addition, if the supply of the clock is stopped as needed, the desired address can be held.

[Effect of the Invention] As described above, according to the present invention, when testing a memory that does not require an address signal, there is no need to output an address signal for accessing the failure analysis memory from the pattern generator 1.

Therefore, a program for operating the pattern generator 1 can be simplified, and an advantage that a program can be easily created is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention, and FIG. 2 is a block diagram for explaining a conventional technique. 1: pattern generator, 5: memory under test, 6: comparator, 7: failure analysis memory, 8: address pointer, 9: selector.

Claims (1)

(57) [Claims] A. A memory test apparatus in which pattern data is provided to a memory under test, a read output of the pattern data is compared with an expected value, and a match / mismatch is determined to determine pass / fail of the memory under test. B. an address pointer having a function of taking in an address given from a pattern generator as an initial address, a function of incrementing or decrementing the address every time a clock is supplied from this initial address, and a function of holding at a desired address; C. A memory test apparatus comprising: an address signal output from the address pointer; and a selector for selecting one of the address signals supplied from the pattern generator and supplying the selected address signal to an address terminal of the failure analysis memory.