JP2762103B2 - Method for forming SOI film - Google Patents
Method for forming SOI filmInfo
- Publication number
- JP2762103B2 JP2762103B2 JP1067962A JP6796289A JP2762103B2 JP 2762103 B2 JP2762103 B2 JP 2762103B2 JP 1067962 A JP1067962 A JP 1067962A JP 6796289 A JP6796289 A JP 6796289A JP 2762103 B2 JP2762103 B2 JP 2762103B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- spe
- substrate
- exposed surface
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000000034 method Methods 0.000 title claims description 29
- 239000000758 substrate Substances 0.000 claims description 24
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 19
- 239000010410 layer Substances 0.000 claims description 18
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 239000007790 solid phase Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- -1 silicon ions Chemical class 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 229910021426 porous silicon Inorganic materials 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 10
- 229910021419 crystalline silicon Inorganic materials 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000000137 annealing Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 238000005979 thermal decomposition reaction Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000635 electron micrograph Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、単結晶シリコン基板上に絶縁膜を形成し、
さらにこの絶縁膜上に単結晶シリコン膜を成長させてSO
I〔Silicon On Insulator〕膜を形成するSOI膜の形成方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention forms an insulating film on a single crystal silicon substrate,
Further, a single crystal silicon film is grown on this insulating film to
The present invention relates to a method for forming an SOI film for forming an I [Silicon On Insulator] film.
一般に、SOI膜は、素子分離が容易であり,ラッチア
ップを防止でき,薄膜化によつて高移動度が得られるな
どの特徴を有しているため、高速・高集積デバイス用の
基板材料,特に積層構造の三次元回路素子材料として注
目され、近年盛んに研究開発が進められている。In general, SOI films have characteristics such as easy isolation of elements, prevention of latch-up, and high mobility obtained by thinning, so that substrate materials for high-speed and highly integrated devices can be used. In particular, it has attracted attention as a three-dimensional circuit element material having a laminated structure, and has been actively researched and developed in recent years.
ところで、このようなSOI膜を形成する技術のひとつ
として、非晶質基板或いは非晶質膜上に多結晶シリコン
を堆積し、レーザビーム或いは電子ビームを用いて溶融
再結晶化する方法が知られているが、スループットが低
く、再結晶化層の結晶方位制御が難しいなどの問題があ
る。Incidentally, as one of the techniques for forming such an SOI film, there is known a method of depositing polycrystalline silicon on an amorphous substrate or an amorphous film and melting and recrystallizing the same using a laser beam or an electron beam. However, there are problems such as low throughput and difficulty in controlling the crystal orientation of the recrystallized layer.
また、他の手法として固相エピタキシャル成長法(以
下SPE法という)があり、これはSi基板上に非晶質絶縁
膜を形成し、この絶縁膜の一部を除去してSi基板に露出
面を形成し、この露出面及び絶縁膜上に非晶質Si(以下
a−Siという)膜を堆積形成したのち、N2雰囲気中で60
0℃,数10時間のアニールを行い、露出面をシードとし
た縦方向固相エピタキシャル成長(以下V−SPEとい
う),及び横方向固相エピタキシャル成長(以下L−SP
Eという)により、a−Si膜を単結晶化させるものであ
る。Another method is the solid phase epitaxial growth method (hereinafter referred to as the SPE method), in which an amorphous insulating film is formed on a Si substrate, and a part of the insulating film is removed to expose an exposed surface on the Si substrate. After forming an amorphous Si (hereinafter referred to as a-Si) film on the exposed surface and the insulating film, the film is formed in an N 2 atmosphere.
Annealing is performed at 0 ° C. for several tens of hours, and vertical solid phase epitaxial growth (hereinafter referred to as V-SPE) and lateral solid phase epitaxial growth (hereinafter referred to as L-SP) using the exposed surface as a seed.
(Referred to as E) to make the a-Si film single crystallize.
ところが、SPE法の場合、V−SPEがSi基板の露出面を
シードとして進行する際、絶縁膜と露出面との段差が大
きい場合に、この段差部分でストレスが発生し、絶縁膜
とSiとの界面に歪が発生してL−SPEの進行が妨げら
れ、十分なL−SPE距離が得られないという不都合が生
じる。However, in the case of the SPE method, when the V-SPE proceeds with the exposed surface of the Si substrate as a seed, if the step between the insulating film and the exposed surface is large, stress occurs at the step, and the insulating film and the Si Strain is generated at the interface, and the progress of the L-SPE is hindered, so that there is a disadvantage that a sufficient L-SPE distance cannot be obtained.
このような不都合を解消するために、絶縁膜とSi基板
の露出面との段差をできるだけ小さくしたリセス構造を
採用することが行われ、さらにL−SPE距離の拡大を図
るためにリン〔P〕イオンをa−Si膜に注入したのちア
ニールすることなどが行われており、例えばApplied Ph
ysics Letters48(12),24 March,1986,pp.778−775に
報告されているように、段差が約1000Åのリセス構造に
おいて、p+の注入によつて約45μmのL−SPE距離が得
られている。In order to solve such inconveniences, a recess structure in which the step between the insulating film and the exposed surface of the Si substrate is made as small as possible has been adopted. In order to further increase the L-SPE distance, phosphorus [P] has been used. Annealing is performed after ions are implanted into the a-Si film. For example, Applied Ph
As reported in ysics Letters 48 (12), 24 March, 1986, pp. 778-775, an L-SPE distance of about 45 μm can be obtained by implanting p + in a recess structure with a step of about 1000 °. ing.
ところで、三次元回路素子を作成する場合に、下層に
デバイスを作り込んだときに、シードとしてのSi基板の
露出面とパッシベーション膜としての絶縁膜との段差が
1μm以上になることがあり、この段差がL−SPEの進
行の妨げになるため、前記したリセス構造ではこれを解
消することは難しい。By the way, when creating a three-dimensional circuit element, when a device is built in a lower layer, a step between an exposed surface of a Si substrate as a seed and an insulating film as a passivation film may be 1 μm or more. Since the step hinders the progress of the L-SPE, it is difficult to eliminate this in the recess structure described above.
そこで、Si基板の露出面上に予め単結晶シリコンのシ
ード部を埋め込むことが考えられており、特に選択エピ
タキシャル成長法によるシード部の埋め込み技術は、L
−SPEでのa−Siの堆積とシード部の埋め込みを連続的
に行えるという利点を有し、今後の有望な技術として注
目されている。Therefore, it has been considered to embed a seed portion of single-crystal silicon in advance on the exposed surface of the Si substrate.
-It has the advantage that the deposition of a-Si and the embedding of the seed portion by -SPE can be performed continuously, and it is attracting attention as a promising technology in the future.
そして、この選択エピタキシャル成長法によるシード
部の埋め込み技術を使つたSPE法について、第3図を参
照して説明すると、同図(a)に示すように、(100)S
i基板(1)上に熱酸化法等により膜厚1μmのSiO2膜
(2)を形成し、このSiO2膜(2)の一部をエッチング
により除去して<100>方向にストライプ状に幅約2μ
mのSi基板(1)の露出面(3)を形成し、SiH4ガスの
熱分解法を利用しれ減圧CVD法により、基板温度940℃,
SiH4ガス流量4SCCMの条件でSiのエピタキシャル成長を
行うと、同図(b)に示すように、露出面(3)上にの
み選択的に単結晶Si(以下c−Siという)が成長し、露
出面(3)上にシード部(4)が形成される。The SPE method using the seed part filling technique by the selective epitaxial growth method will be described with reference to FIG. 3, as shown in FIG.
The i substrate (1) thermal oxidation method on such to form a SiO 2 film having a thickness of 1 [mu] m (2), a part of the SiO 2 film (2) is removed by etching <100> direction in a stripe pattern About 2μ in width
The exposed surface (3) of the m-Si substrate (1) is formed, and the substrate temperature is 940 ° C. by the reduced pressure CVD method using the thermal decomposition method of SiH 4 gas.
When Si is epitaxially grown under the condition of a SiH 4 gas flow rate of 4 SCCM, single crystal Si (hereinafter referred to as c-Si) is selectively grown only on the exposed surface (3) as shown in FIG. A seed part (4) is formed on the exposed surface (3).
このとき、c−Siのシード部(4)の側面に(111)
ファセット面(5)が形成される。At this time, (111) is formed on the side surface of the seed portion (4) of c-Si.
A facet surface (5) is formed.
また、前記した条件下での成長速度が約200Å/minで
あるため、SiO2膜(2)と露出面(3)との段差が1μ
mであるとき、これを埋めるには約1時間選択エピタキ
シャル成長を行えばよい。Further, since the growth rate under the above-mentioned conditions is about 200 ° / min, the step between the SiO 2 film (2) and the exposed surface (3) is 1 μm.
When it is m, selective epitaxial growth may be performed for about 1 hour to fill this.
つぎに、シード部(4)の形成を行つたのち、基板温
度を550℃まで下げ、SiH4ガスの熱分解法を利用した減
圧CVD法により、SiH4の分圧約10Torr,堆積速度200Å/mi
nの条件で15分間反応を行い、第3図(c)に示すよう
に、SiO2膜(2)上及びシード部(3)上に膜厚3000Å
のa−Si膜(6)を形成する。Next, after the formation of the seed portion (4), the substrate temperature was lowered to 550 ° C., and the partial pressure of SiH 4 was about 10 Torr and the deposition rate was 200 ° C./mi by the reduced pressure CVD method using the thermal decomposition method of SiH 4 gas.
The reaction was carried out for 15 minutes under the condition of n, and as shown in FIG. 3 (c), a film thickness of 3000 に was formed on the SiO 2 film (2) and the seed portion (3).
A-Si film (6) is formed.
その後、(180KeV,7×1015cm-2),(100KeV,3×1015
cm-2),(50KeV,2×1015cm-2)の注入条件で、第3図
(d)に示すように、a−Si膜(6)に3回にわたつて
P+の注入を行い、a−Si膜(6)にほぼ均一に3×1020
cm-3のイオン濃度にP+を注入したのち、a−Si膜(6)
をN2雰囲気中において590℃で15時間アニールし、同図
(e)に示すようにL−SPE層(7)を形成し、SOI膜を
形成する。Then, (180 KeV, 7 × 10 15 cm -2 ), (100 KeV, 3 × 10 15
cm −2 ) and (50 KeV, 2 × 10 15 cm −2 ), as shown in FIG. 3D, three times over the a-Si film (6).
P + is implanted, and 3 × 10 20 is almost uniformly formed on the a-Si film (6).
After implanting P + to an ion concentration of cm −3 , an a-Si film (6)
Is annealed at 590 ° C. for 15 hours in an N 2 atmosphere to form an L-SPE layer (7) as shown in FIG.
このとき、L−SPEの生じない領域のa−Si膜(6)
は多結晶化し、多結晶Si膜(8)が形成される。At this time, the a-Si film in a region where L-SPE does not occur (6)
Is polycrystallized to form a polycrystalline Si film (8).
ところで、このように形成したSOI膜の断面の走査型
電子顕微鏡(SEM)写真は第4図に示すようになり、同
図中SEGは選択エピタキシャル成長で,第3図のシード
部(4)に相当しSi SubstrateはSi基板(1)に相当
し,第4図からわかるように、SEGのシード部(4)と
L−SPE層(7)との境界部にくぼみが生じており、こ
のくぼみは、前記したようにSEGによるシード部(4)
の成長時に形成されたファセット面(5)により、L−
SPEの進行が阻害されたために生じたものと考えられ
る。By the way, a scanning electron microscope (SEM) photograph of the cross section of the SOI film thus formed is as shown in FIG. 4, in which SEG is selective epitaxial growth and corresponds to the seed portion (4) in FIG. The Si Substrate corresponds to the Si substrate (1). As can be seen from FIG. 4, a recess is formed at the boundary between the seed portion (4) of the SEG and the L-SPE layer (7). Seed section by SEG as described above (4)
The facet surface (5) formed during the growth of
It is considered that this occurred because the progression of SPE was inhibited.
従来の場合、SEGによりシード部(4)の埋め込み時
に形成されるファセット面によつてL−SPEの進行が阻
害されるため、L−SPE距離は10μm程度に留まり、L
−SPE距離の拡大を図ることができないという問題点が
ある。In the conventional case, since the progression of L-SPE is hindered by the facet surface formed when the seed portion (4) is buried by the SEG, the L-SPE distance is limited to about 10 μm.
-There is a problem that the SPE distance cannot be increased.
本発明は、前記の点に留意してなされ、L−SPE距離
の拡大を図り、大面積のSOI膜を形成できるようにする
ことを目的とする。The present invention has been made in consideration of the above points, and has as its object to increase the L-SPE distance so that a large-area SOI film can be formed.
前記目的を達成するために、本発明のSOI膜の形成方
法では、単結晶シリコン基板上に非晶質絶縁膜を形成
し、前記絶縁膜の一部を除去して前記基板に露出面を形
成し、選択エピタキシャル成長法により前記露出面上に
単結晶シリコンのシード部を形成したのち、前記シード
部上及び前記絶縁膜上に単結晶シリコン膜及び多結晶シ
リコン膜をそれぞれ形成し、前記単結晶シリコン膜及び
前記多結晶シリコン膜の表面にシリコンイオンを注入
し、前記単結晶シリコン膜の表層部及び前記多結晶シリ
コン膜の全部を非晶質化して非晶質シリコン層を形成
し、前記非晶質シリコン層にリンを注入したのち、前記
非晶質シリコン層を固相エピタキシャル成長法により単
結晶化することを特徴としている。In order to achieve the above object, in the method for forming an SOI film of the present invention, an amorphous insulating film is formed on a single crystal silicon substrate, and a part of the insulating film is removed to form an exposed surface on the substrate. Forming a seed portion of single crystal silicon on the exposed surface by selective epitaxial growth, forming a single crystal silicon film and a polycrystalline silicon film on the seed portion and the insulating film, respectively, Implanting silicon ions into the surface of the film and the polycrystalline silicon film, amorphizing the surface layer portion of the single crystal silicon film and the entire polycrystalline silicon film to form an amorphous silicon layer; After injecting phosphorus into the porous silicon layer, the amorphous silicon layer is monocrystallized by a solid phase epitaxial growth method.
以上のような構成において、選択エピタキシャル成長
法により形成したシード部上に単結晶シリコン膜を形成
すると共に、非晶質絶縁膜上に多結晶シリコン膜を形成
すると、シード部を形成した段階では、シード部の側面
にファセット面が形成されるが、その後の単結晶シリコ
ン膜及び多結晶シリコン膜の形成工程により、単結晶シ
リコン膜と多結晶シリコン膜との境界にはファセット面
の形成は見られなくなり、露出面と絶縁膜との段差が1
μm以上ある場合であつても、ファセット面の形成を防
止してL−SPE距離の拡大が図れる。In the above configuration, when a single crystal silicon film is formed on the seed portion formed by the selective epitaxial growth method and a polycrystalline silicon film is formed on the amorphous insulating film, the seed portion is formed at the stage where the seed portion is formed. A facet surface is formed on the side surface of the portion, but in the subsequent formation process of the single crystal silicon film and the polycrystalline silicon film, no facet surface is formed at the boundary between the single crystal silicon film and the polycrystalline silicon film. , The step between the exposed surface and the insulating film is 1
Even in the case where the length is not less than μm, the formation of the facet surface can be prevented and the L-SPE distance can be increased.
実施例について第1図及び第2図を参照して説明す
る。An embodiment will be described with reference to FIG. 1 and FIG.
まず、第1図(a)に示すように、第3図の場合と同
様に、(100)Si基板(9)上に熱酸化法等により膜厚
1μmの非晶質絶縁膜としてのSiO2膜(10)を形成し、
このSiO2膜(10)の一部をエッチングにより除去して<
100>方向にストライプ状に幅約2μmのSi基板(9)
の露出面(11)を形成する。First, as shown in FIG. 1 (a), similarly to the case of FIG. 3, SiO 2 as an amorphous insulating film having a thickness of 1 μm is formed on a (100) Si substrate (9) by a thermal oxidation method or the like. Forming a membrane (10),
A part of the SiO 2 film (10) is removed by etching.
Si substrate with a width of about 2 μm in stripes in the 100> direction (9)
The exposed surface (11) is formed.
つぎに、SiH4ガスの熱分解法を利用した減圧CVD法に
より、基板温度940℃,SiH4ガス流量4SCCMの条件で約1
時間、第1図(b)に示すように露出面(11)上にc−
Siのシード部(12)を選択エピタキシャル成長させる。Next, by a reduced pressure CVD method using a thermal decomposition method of SiH 4 gas, a substrate temperature of 940 ° C. and a SiH 4 gas flow rate of 4 SCCM were used for about 1 hour.
Time, c- on the exposed surface (11) as shown in FIG.
The Si seed portion (12) is selectively epitaxially grown.
なお、第3図の場合と同様、シード部(12)の側面に
は(111)ファセット面(13)が形成される。As in the case of FIG. 3, a (111) facet surface (13) is formed on the side surface of the seed portion (12).
その後、基板温度を800℃まで下げ、SiH4ガス流量20S
CCM,SiH4ガス分圧100mTorrの条件で約500Å/minの成長
速度でエピタキシャル成長を行い、シード部(12)上に
c−Si膜(14)を成長させると共に、SiO2膜(10)上に
多結晶Si膜(以下p−Si膜という)(15)を成長させ
る。After that, the substrate temperature was lowered to 800 ° C and the SiH 4 gas flow rate was 20S.
Epitaxial growth is performed at a growth rate of about 500Å / min under the conditions of CCM, SiH 4 gas partial pressure of 100 mTorr, and a c-Si film (14) is grown on the seed portion (12) and on the SiO 2 film (10). A polycrystalline Si film (hereinafter referred to as a p-Si film) (15) is grown.
このとき、p−Si膜(15)が約3000Åの膜厚になるよ
う、5〜6分間成長を行う。At this time, growth is performed for 5 to 6 minutes so that the p-Si film (15) has a thickness of about 3000 °.
さらに、(180KeV,2×1016cm-2),(100KeV,2×1016
cm-2),(50KeV,2×1016cm-2)の注入条件で、第1図
(d)に示すように、c−Si膜(14)及びp−Si膜(1
5)に3回にわたつてSi+を注入し、c−Si膜(14)の表
層部及びp−Si膜(14)の全部を非晶質化し、a−Si層
(16)を形成する。Furthermore, (180 KeV, 2 × 10 16 cm −2 ), (100 KeV, 2 × 10 16
cm −2 ) and (50 KeV, 2 × 10 16 cm −2 ), as shown in FIG. 1D, the c-Si film (14) and the p-Si film (1
5) Inject Si + three times to amorphize the entire surface layer of the c-Si film (14) and the p-Si film (14) to form an a-Si layer (16). .
そして、(180KeV,7×1015cm-2),(100KeV,3×1015
cm-2),(50KeV,2×1015cm-2)の注入条件で、3回に
わたつてa−Si層(16)にP+を注入したのち、N2雰囲気
中において600℃で10時間以上アニールし、第1図
(e)に示すように、a−Si層(16)をSPE法により単
結晶化してc−Si層(17)を形成し、SOI膜を形成す
る。And (180 KeV, 7 × 10 15 cm -2 ), (100 KeV, 3 × 10 15
cm −2 ) and (50 KeV, 2 × 10 15 cm −2 ), P + was implanted into the a-Si layer (16) three times, and then implanted at 600 ° C. in an N 2 atmosphere at 10 ° C. After annealing for more than an hour, as shown in FIG. 1 (e), the a-Si layer (16) is monocrystallized by the SPE method to form a c-Si layer (17), thereby forming an SOI film.
このとき、シード部(12)上のa−Si層(17)はV−
SPEにより単結晶化し、SiO2膜(10)上のa−Si層(1
7)はL−SPEにより単結晶化する。At this time, the a-Si layer (17) on the seed portion (12) is
Single crystallized by SPE, a-Si layer (1) on SiO 2 film (10)
7) is single-crystallized by L-SPE.
ところで、シード部(12)を形成した段階では、シー
ド部(12)の側面にファセット面(13)が形成される
が、その後c−Si膜(14)及びp−Si膜(15)をエピタ
キシャル成長させたときに、c−Si膜(14)とp−Si膜
(15)との境界にはファセット面の形成が見られなくな
り、その結果露出面(11)とSiO2膜(10)との段差が1
μm以上ある場合であつても、従来のようなファセット
面の形成を防止でき、L−SPE距離の大幅な拡大が可能
となる。By the way, at the stage where the seed portion (12) is formed, a facet surface (13) is formed on the side surface of the seed portion (12). Thereafter, the c-Si film (14) and the p-Si film (15) are epitaxially grown. When this is done, no facet is formed at the boundary between the c-Si film (14) and the p-Si film (15). As a result, the exposed surface (11) and the SiO 2 film (10) Step is 1
Even in the case where the thickness is not less than μm, the formation of the facet surface as in the related art can be prevented, and the L-SPE distance can be greatly increased.
そして、このようにして得られたSOI膜の表面を、酸
化クロム−フッ酸−硝酸銅−酢酸−水の組成のライトエ
ッチング溶液を用いて顕在化したときの電子顕微鏡写真
は第2図に示すようになり、同図中SEEDはシード部(1
2)に相当し、同図中のSEEDとL−SPEとの境界からのL
−SPEの幅は約20μmとなつており、前記した方法によ
つて約20μmのL−SPE距離が得られることがわかる。FIG. 2 shows an electron micrograph when the surface of the SOI film thus obtained was revealed using a light etching solution having a composition of chromium oxide-hydrofluoric acid-copper nitrate-acetic acid-water. SEED is the seed part (1
L) from the boundary between SEED and L-SPE in FIG.
It can be seen that the width of -SPE is about 20 [mu] m, and an L-SPE distance of about 20 [mu] m can be obtained by the method described above.
本発明は、以上説明したように構成されているので、
以下に記載する効果を奏する。Since the present invention is configured as described above,
The following effects are obtained.
選択エピタキシャル成長法により形成したシード部上
に単結晶シリコン膜を形成すると共に、非晶質絶縁膜上
に多結晶シリコン膜を形成したため、シード部を形成し
た段階では、シード部の側面にファセット面が形成され
るが、その後の工程により、単結晶シリコン膜と多結晶
シリコン膜との境界にはファセット面の形成が見られな
くなり、露出面と絶縁膜との段差が1μm以上ある場合
であつても、従来のようなファセット面の形成を防止す
ることができ、L−SPE距離の拡大を図ることができ、
大面積のSOI膜を得ることが可能となり、三次元回路素
子の作成技術として極めて有効である。Since a monocrystalline silicon film was formed on the seed portion formed by the selective epitaxial growth method and a polycrystalline silicon film was formed on the amorphous insulating film, a facet surface was formed on the side surface of the seed portion at the stage of forming the seed portion. However, due to the subsequent steps, no facet surface is formed at the boundary between the single crystal silicon film and the polycrystalline silicon film, and even if the step between the exposed surface and the insulating film is 1 μm or more. Therefore, it is possible to prevent the formation of the facet surface as in the prior art, and to increase the L-SPE distance,
This makes it possible to obtain a large-area SOI film, which is extremely effective as a technique for producing a three-dimensional circuit element.
第1図及び第2図は本発明のSOI膜の形成方法の1実施
例を示し、第1図(a)〜(e)は形成工程を示す断面
図、第2図はライトエッチングにより顕在化したSOI膜
表面の電子顕微鏡写真、第3図(a)〜(e)は従来例
の形成工程を示す断面図、第4図は第3図の工程により
形成したSOI膜の断面の電子顕微鏡写真である。 (9)……Si基板、(10)……SiO2膜、(11)……露出
面、(12)……シード部、(14)……c−Si膜、(15)
……p−Si膜、(16)……a−Si層、(17)……c−Si
層。1 and 2 show one embodiment of a method for forming an SOI film according to the present invention. FIGS. 1 (a) to 1 (e) are cross-sectional views showing a forming process, and FIG. 3 (a) to 3 (e) are cross-sectional views showing the forming steps of the conventional example, and FIG. 4 is an electron micrograph of the cross section of the SOI film formed by the steps of FIG. It is. (9) ... Si substrate, (10) .... SiO 2 film, (11) ... exposed surface (12) ... seed unit, (14) .... c-Si film, (15)
... p-Si film, (16) ... a-Si layer, (17) ... c-Si
layer.
Claims (1)
成し、前記絶縁膜の一部を除去して前記基板に露出面を
形成し、選択エピタキシャル成長法により前記露出面上
に単結晶シリコンのシード部を形成したのち、前記シー
ド部上及び前記絶縁膜上に単結晶シリコン膜及び多結晶
シリコン膜をそれぞれ形成し、前記単結晶シリコン膜及
び前記多結晶シリコン膜の表面にシリコンイオンを注入
し、前記単結晶シリコン膜の表層部及び前記多結晶シリ
コン膜の全部を非晶質化して非晶質シリコン層を形成
し、前記非晶質シリコン層にリンを注入したのち、前記
非晶質シリコン層を固相エピタキシャル成長法により単
結晶化することを特徴とするSOI膜の形成方法。An amorphous insulating film is formed on a single crystal silicon substrate, an exposed surface is formed on the substrate by removing a part of the insulating film, and a single crystal is formed on the exposed surface by a selective epitaxial growth method. After forming a silicon seed portion, a single-crystal silicon film and a polycrystalline silicon film are formed on the seed portion and the insulating film, respectively, and silicon ions are formed on the surfaces of the single-crystal silicon film and the polycrystalline silicon film. Implanting, amorphizing the surface layer portion of the single crystal silicon film and the entire polycrystalline silicon film to form an amorphous silicon layer, implanting phosphorus into the amorphous silicon layer, A method for forming an SOI film, comprising monocrystallizing a porous silicon layer by a solid phase epitaxial growth method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1067962A JP2762103B2 (en) | 1989-03-20 | 1989-03-20 | Method for forming SOI film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1067962A JP2762103B2 (en) | 1989-03-20 | 1989-03-20 | Method for forming SOI film |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02246210A JPH02246210A (en) | 1990-10-02 |
JP2762103B2 true JP2762103B2 (en) | 1998-06-04 |
Family
ID=13360100
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JP1067962A Expired - Fee Related JP2762103B2 (en) | 1989-03-20 | 1989-03-20 | Method for forming SOI film |
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JP (1) | JP2762103B2 (en) |
Families Citing this family (2)
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---|---|---|---|---|
KR100611061B1 (en) * | 2004-09-08 | 2006-08-10 | 삼성전자주식회사 | Method of manufacturing an epitaxial layer and method of manufacturing a thin layer and a semiconductor device using the same |
US10304723B1 (en) | 2017-11-22 | 2019-05-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process to form SOI substrate |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6158879A (en) * | 1984-08-29 | 1986-03-26 | Nec Corp | Preparation of silicon thin film crystal |
JPS6248015A (en) * | 1985-08-28 | 1987-03-02 | Sony Corp | Solid phase growth of semiconductor layer |
-
1989
- 1989-03-20 JP JP1067962A patent/JP2762103B2/en not_active Expired - Fee Related
Also Published As
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