JP2755619B2 - Insulated gate semiconductor device - Google Patents
Insulated gate semiconductor deviceInfo
- Publication number
- JP2755619B2 JP2755619B2 JP63263107A JP26310788A JP2755619B2 JP 2755619 B2 JP2755619 B2 JP 2755619B2 JP 63263107 A JP63263107 A JP 63263107A JP 26310788 A JP26310788 A JP 26310788A JP 2755619 B2 JP2755619 B2 JP 2755619B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- layer
- electrode
- protection
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
- H10D84/141—VDMOS having built-in components
- H10D84/148—VDMOS having built-in components the built-in components being breakdown diodes, e.g. Zener diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
- H10D84/141—VDMOS having built-in components
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は半導体装置、特に縦形MOSFET素子とそのゲー
ト保護素子とを有する絶縁ゲート形半導体装置に関す
る。The present invention relates to a semiconductor device, and more particularly, to an insulated gate semiconductor device having a vertical MOSFET element and its gate protection element.
（ロ）従来の技術 パワー用縦形MOSFETはN+N型Si基体をドレインとし、
このＮ基体表面の一部にＰ型領域を形成し、このＰ型領
域表面の一部にN+型領域を設けてソースとし、ソース・
ドレイン間のＰ型領域表面をチャンネル部としてこの上
にも絶縁膜（SiO2）を介して多結晶Siゲートを設けた構
造である。MOSFETを外部サージ電圧から保護するための
保護素子として従来は主としてMOSFETと同一基板中に設
けられたPNP接合ダイオードを用いていたが、基板がド
レイン領域として動作する縦形MOSFETの場合には寄生ト
ランジスタによるサイリスタ動作を生じて破壊するなど
の実用上の障害がある。このためこの種の保護素子をMO
SFET基板と分離された絶縁膜上に設ける構造が例えば特
開昭58−84461号公報に提案されている。その回路図
は、第５図に示す如くMOSFET素子（１）のゲートＧとソ
ースＳの間に保護ダイオード（２）を設けたものであ
る。(B) Conventional technology A vertical MOSFET for power uses an N + N-type Si substrate as a drain,
A P-type region is formed on a part of the surface of the N base, and an N + -type region is provided on a part of the surface of the P-type region to serve as a source.
In this structure, a polycrystalline Si gate is provided on the P-type region surface between the drains as a channel portion via an insulating film (SiO 2 ). Conventionally, a PNP junction diode provided on the same substrate as the MOSFET is mainly used as a protection element to protect the MOSFET from external surge voltage.However, in the case of a vertical MOSFET in which the substrate operates as a drain region, a parasitic transistor is used. There are practical obstacles such as the occurrence and destruction of the thyristor operation. For this reason, this type of protection element is
A structure provided on an insulating film separated from an SFET substrate has been proposed in, for example, Japanese Patent Application Laid-Open No. 58-84461. The circuit diagram is such that a protection diode ( 2 ) is provided between the gate G and the source S of the MOSFET element ( 1 ) as shown in FIG.
（ハ）発明が解決しようとする課題 しかしながら、素子の微細化が押し進められ、比例縮
小によりゲート酸化膜が一層薄くなると保護ダイオード
が保護動作を行う以前に破壊が発生することが明らかに
なった。これは、ゲートＧにサージ電圧が印加すると保
護素子（２）とゲートＧの酸化膜に同時に前記サージ電
圧が印加される為であり、ゲート酸化膜が破壊される前
に保護素子が動作するような構造が望まれていた。(C) Problems to be Solved by the Invention However, as the miniaturization of the element has been promoted and the gate oxide film has become thinner due to the proportional reduction, it has become clear that the protection diode will be destroyed before performing the protection operation. This is because when a surge voltage is applied to the gate G, the surge voltage is simultaneously applied to the protection element ( 2 ) and the oxide film of the gate G, so that the protection element operates before the gate oxide film is destroyed. A simple structure was desired.
（ニ）課題を解決するための手段 本発明は上記従来の課題に鑑み成されたもので、ゲー
ト取出し電極（22）からソース電極（20）までの保護ダ
イオード（17）の線路インピーダンスよりも前記ゲート
取出し電極（22）から前記ゲート電極（15）の動作部分
までの半導体層の線路インピーダンスを大にすることに
より、ゲート酸化膜（14）の破壊より先に保護動作をな
し得る絶縁ゲート型半導体装置を提供するものである。(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional problems, and is more effective than the line impedance of the protection diode ( 17 ) from the gate extraction electrode (22) to the source electrode (20). By increasing the line impedance of the semiconductor layer from the gate extraction electrode (22) to the operating portion of the gate electrode (15), an insulated gate semiconductor capable of performing a protection operation prior to the destruction of the gate oxide film (14). An apparatus is provided.
（ホ）作用 本発明によれば、ゲート電極（15）の動作部側に至る
半導体層を高インピーダンスにすることによって、サー
ジ電圧を制限する保護抵抗（23）をゲートに直列に挿入
できる。従って、サージ電圧からMOS素子を保護できる
と同時に、サージ電圧が制限されている間に保護ダイオ
ード（17）が導通してサージ電圧を吸収するので、より
効果的に素子の保護を行うことができる。(E) Function According to the present invention, the protection resistance ( 23 ) for limiting the surge voltage can be inserted in the gate in series by making the semiconductor layer reaching the operating portion side of the gate electrode (15) high impedance. Therefore, the MOS element can be protected from the surge voltage, and at the same time, the protection diode ( 17 ) conducts and absorbs the surge voltage while the surge voltage is limited, so that the element can be more effectively protected. .
（ヘ）実施例 以下に本発明の一実施例を図面を参照しながら詳細に
説明する。(F) Embodiment One embodiment of the present invention will be described below in detail with reference to the drawings.
第１図と第２図は夫々本発明のパワーMOSFETの断面構
造と平面構造を示す。1 and 2 show a cross-sectional structure and a planar structure of a power MOSFET of the present invention, respectively.
同図において、（11）はMOSFETのドレインとなるＮ型
Si基板、（12）はＰ型拡散層、（13）はN+型拡散ソー
ス、（14）はゲート絶縁膜となる薄いSiO2膜、（15）は
多結晶Siゲート、（16）はフィールド絶縁膜となる厚い
SiO2膜、であり、これらにより縦形MOSFETが構成され
る。この絶縁膜（16）上にMOSFET保護ダイオード（17）
となる多結晶Si層が形成される。この多結晶Si層は多結
晶Siゲートと同じ工程で絶縁膜上に形成されるものであ
り第２図に示すように、ループ状に多重に形成されたＰ
型拡散Si層（18a），（18b）とこれと内側及び外側でPN
接合を介して隣接するN+型拡散Si層（19a），（19b），
（19c）とから成る。このうち外側のN+型拡散Si層（19
c）にはAl配線（20）がコンタクトし、このAl配線（2
0）は層間絶縁膜（21）、例えばPSG（リン・シリケート
・ガラス）上を延在してソース電極Ｓと一体的に接続す
る。一方、内側のN+型拡散Si層（19a）は、外部接続用A
l電極パッドとなるゲート取出し電極（22）がコンタク
トし、層間絶縁膜（21）上を延在してMOSFETのゲート保
護抵抗（23）を形成する多結晶Si層とコンタクトする。In the same figure, (11) is an N-type that becomes the drain of the MOSFET.
Si substrate, (12) P-type diffusion layer, (13) N + type diffusion source, (14) thin SiO 2 film as gate insulating film, (15) polycrystalline Si gate, (16) field Thick insulating film
SiO 2 films, which constitute a vertical MOSFET. MOSFET protection diode ( 17 ) on this insulating film (16)
Is formed. This polycrystalline Si layer is formed on the insulating film in the same step as the polycrystalline Si gate, and as shown in FIG.
-Type diffusion Si layers (18a) and (18b) and PN
Adjacent N + -type diffused Si layers via junctions (19a), (19b),
(19c). Of these, the outer N + -type diffused Si layer (19
c) is contacted with the Al wiring (20), and this Al wiring (2
0) extends over an interlayer insulating film (21), for example, PSG (phosphorus silicate glass) and is integrally connected to the source electrode S. On the other hand, the inner N + type diffusion Si layer (19a)
A gate extraction electrode (22) serving as an electrode pad contacts, and contacts with a polycrystalline Si layer extending on the interlayer insulating film (21) and forming a gate protection resistor ( 23 ) of the MOSFET.
この多結晶Si層もまた、保護ダイオード（17）と同じ
くゲート電極（15）と同じ工程で形成されたものであ
り、ゲート電極（15）と同じ導電型と不純物濃度を有す
るN+型拡散Si層（24a），（24b）とそれよりも高い層抵
抗を有するN-型拡散Si層（25）とから成る。このN-型拡
散Si層（25）は、N+型拡散Si層（24a），（24b）の間に
ストライプ状に形成されてゲート取出し電極（22）とゲ
ート電極（15）の動作部分の間に保護抵抗（23）として
挿入される。The polycrystalline Si layer also has been formed in the same step protection diode (17) like the gate electrode (15), N + -type diffused Si having the same conductivity type and the impurity concentration and a gate electrode (15) It comprises layers (24a) and (24b) and an N - type diffused Si layer (25) having a higher layer resistance. The N - type diffusion Si layer (25), N + -type diffusion Si layer (24a), the operating portion of the gate electrode (15) and the gate extraction electrode (22) is formed in a stripe shape between (24b) It is inserted between them as a protective resistor ( 23 ).
上記保護ダイオード（17）と保護抵抗（23）は、絶縁
膜（16）とゲート絶縁膜（14）を形成しその上にノンド
ープの多結晶Si層をデポジットし、全面をリン（Ｐ）ド
ープしてN-型拡散Si層（25）に対応する不純物濃度と
し、この多結晶Si層をホトエッチング処理することによ
りゲートセル（26）を開孔してゲート電極（15）を形成
し、N-型拡散Si層（25）に対応する部分をホトレジスト
膜で覆ってボロン（Ｂ）のチャンネルイオン注入を行う
ことによりＰ型拡散層（12）のチャンネル部分を形成し
且つN-型拡散Si層（25）を除く多結晶Si層をＰ型Si層と
し、再びホトレジスト膜でＰ型拡散層（12）の真中と保
護ダイオード（17）のＰ型拡散Si層（18a），（18b）及
び保護抵抗（23）のN-型拡散Si層（25）に対応する部分
を覆ってリン（Ｐ）のイオン注入を行うことによりN+型
拡散ソース（13）を形成し且つゲート電極（15）と保護
ダイオード（17）部分の多結晶Si層の一部をN+型とする
ことで製造される。その後、CVDパッシベーション膜とA
l層を堆積し、Al層をパターニングすることでソース電
極（20）とゲート取出し電極（22）を形成する。The protection diode ( 17 ) and the protection resistor ( 23 ) are formed by forming an insulating film (16) and a gate insulating film (14), depositing a non-doped polycrystalline Si layer thereon, and doping the entire surface with phosphorus (P). Te N - the impurity concentration corresponding to the type diffusion Si layer (25), forming a gate electrode (15) by opening a gate cells (26) by photoetching process this polycrystalline Si layer, N - -type By covering the portion corresponding to the diffusion Si layer (25) with a photoresist film and performing channel ion implantation of boron (B), the channel portion of the P-type diffusion layer (12) is formed and the N - type diffusion Si layer (25) is formed. ) Is used as the P-type Si layer, and the middle of the P-type diffusion layer (12) and the P-type diffusion Si layers (18a) and (18b) of the protection diode ( 17 ) and the protection resistance ( N 23) - type diffusion Si layer ion implantation of phosphorus over the portions corresponding (P) to (25) Some of the N + -type diffusion source (13) formed and the gate electrode (15) and the protection diode (17) portion of the polycrystalline Si layer is produced by the N + -type by Ukoto. After that, the CVD passivation film and A
By depositing an l layer and patterning the Al layer, a source electrode (20) and a gate extraction electrode (22) are formed.
このような本発明構造の概略図と回路図を夫々第３図
と第４図に示す。同図から明らかな様に、ゲートＧとソ
ースＳの間にNPNPN構造の保護ダイオード（17）が形成
され、さらにゲートＧとMOS素子の動作部との間にN-型
層（25）による保護抵抗（23）が直列に挿入される。従
って、ゲート取出し電極（22）からソース電極（20）ま
での保護ダイオード（17）による線路インピーダンスに
対し、ゲート取出し電極（22）からゲート電極（15）動
作部までの多結晶Si層による線インピーダンスを大にで
きる。A schematic diagram and a circuit diagram of such a structure of the present invention are shown in FIGS. 3 and 4, respectively. As is apparent from the figure, a protection diode ( 17 ) having an NNPPN structure is formed between the gate G and the source S, and furthermore, protection between the gate G and the operating part of the MOS element by an N - type layer (25). A resistor ( 23 ) is inserted in series. Accordingly, the line impedance of the polycrystalline Si layer from the gate extraction electrode (22) to the operation part of the gate electrode (15) is different from the line impedance of the protection diode ( 17 ) from the gate extraction electrode (22) to the source electrode (20). Can be large.
このように本発明によれば、ゲートＧに直列に保護抵
抗（23）を挿入できるので、ゲートＧにサージ電圧が印
加された際保護抵抗（23）がサージ電圧を制限すること
によりゲート酸化膜（14）を保護し、その間に保護ダイ
オード（17）が導通してサージ電圧を吸収するので、MO
SFET素子をより効果的に保護できる。As described above, according to the present invention, the protection resistor ( 23 ) can be inserted in series with the gate G, so that when a surge voltage is applied to the gate G, the protection resistor ( 23 ) limits the surge voltage, thereby reducing the gate oxide film. (14) is protected while the protection diode ( 17 ) conducts and absorbs surge voltage.
The SFET element can be protected more effectively.
また、保護ダイオード（17）はゲート取出し電極（2
2）の領域を利用し且つ保護ダイオード（17）と保護抵
抗（23）の接続もゲート取出し電極（22）を利用するの
でチップサイズの増大を招かずに済む。The protection diode ( 17 ) is connected to the gate extraction electrode (2
Since the area of 2) is used and the connection between the protection diode ( 17 ) and the protection resistor ( 23 ) also uses the gate extraction electrode (22), the chip size does not increase.
（ト）発明の効果 以上説明した様に、本発明によればゲートＧに直列に
保護抵抗（23）を挿入できるので、保護抵抗（23）の電
流制限作用と保護ダイオード（17）の電流吸収作用との
組み合わせにより、サージ電圧がゲート酸化膜（14）を
破壊する以前に保護ダイオード（17）を導通させること
が可能な半導体装置を提供できる利点を有する。(G) Effect of the Invention As described above, according to the present invention, the protection resistor ( 23 ) can be inserted in series with the gate G, so that the current limiting action of the protection resistor ( 23 ) and the current absorption of the protection diode ( 17 ) are achieved. In combination with the operation, there is an advantage that a semiconductor device capable of conducting the protection diode ( 17 ) before the surge voltage destroys the gate oxide film (14) can be provided.
また、保護ダイオード（17）はゲート取出し電極（2
2）下部の多結晶Si層を、保護抵抗（23）は動作部周囲
の多結晶Si層を夫々用い、保護ダイオード（17）と保護
抵抗（22）との接続もまた、ゲート取出し電極（22）を
利用するので、チップサイズを増大させることの無い半
導体装置を提供できる利点を有する。The protection diode ( 17 ) is connected to the gate extraction electrode (2
2) The lower polycrystalline Si layer and the protective resistor ( 23 ) use the polycrystalline Si layer around the active part, respectively. The connection between the protective diode ( 17 ) and the protective resistor (22) is also made by the gate extraction electrode (22). ) Is used, so that there is an advantage that a semiconductor device without increasing the chip size can be provided.
第１図と第２図は夫々本発明を説明する為の断面図と平
面図、第３図と第４図は夫々本発明を説明する為の概略
図と回路図、第５図は従来例を説明する為の回路図であ
る。1 and 2 are a cross-sectional view and a plan view, respectively, for explaining the present invention, FIGS. 3 and 4 are schematic diagrams and circuit diagrams, respectively, for explaining the present invention, and FIG. 5 is a conventional example. FIG. 3 is a circuit diagram for explaining the operation of the embodiment.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭58−25264（ＪＰ，Ａ) 特開 昭59−198762（ＪＰ，Ａ) 特公 昭49−32474（ＪＰ，Ｂ２) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-58-25264 (JP, A) JP-A-59-198762 (JP, A) JP-B-49-32474 (JP, B2)
Claims (1)
半導体基体表面の一部に第２導電型領域を形成し、この
第２導電型領域表面の一部に第１導電型領域を設けてソ
ースとし、ソース・ドレイン間の第２導電型領域上に絶
縁膜を介して設けた多結晶半導体層をゲート電極とし、
このゲートへの電圧印加によって上記第２導電型領域表
面のソース・ドレイン領域電流を制御する電界効果型半
導体素子を多数個並列接続した大電力型の絶縁ゲート型
半導体装置において、 前記基体上に絶縁膜を介して設けられた多結晶半導体層
中の一部に設けられた第１導電型不純物導入層および前
記第１導電型不純物導入層とPN接合を介して隣接する第
２導電型不純物導入層とを有し前記半導体素子のゲート
・ソース間に挿入される保護素子を形成し、 多結晶シリコン層からなり前記ゲート電極層と同導電型
で且つ前記ゲート電極層より不純物濃度が低く、ストラ
イプ状に延在する低不純物濃度領域からなるゲート保護
抵抗を形成し、 前記ゲート保護抵抗を形成する多結晶シリコン層と前記
ゲート電極層とを一体化することで前記保護抵抗の一端
と前記ゲート電極層とを接続し、 前記ゲート保護抵抗の他端をゲート取り出し電極に接続
し、 且つ前記ストライプ状の低不純物濃度領域は前記ゲート
電極層と前記ゲート取り出し電極との間に、前記ゲート
電極層の複数のゲートセルに跨りその抵抗長が短く抵抗
幅が長くなるような形状で延在し、 前記保護素子の一端をソース取り出し電極に、前記保護
素子の他端を前記ゲート取り出し電極に接続して、 前記ゲート取り出し電極から前記ソース取り出し電極ま
での前記保護素子のインピーダンスよりも前記ゲート取
り出し電極から前記ゲート電極の動作部分までのインピ
ーダンスを大としたことを特徴とする絶縁ゲート型半導
体装置。A first conductive type semiconductor substrate serving as a drain, a second conductive type region formed on a part of the surface of the semiconductor substrate, and a first conductive type region provided on a part of the second conductive type region; A polycrystalline semiconductor layer provided on the second conductivity type region between the source and the drain via an insulating film as a gate electrode;
In a high power type insulated gate type semiconductor device in which a plurality of field effect type semiconductor elements for controlling source / drain region current on the surface of the second conductivity type region by applying a voltage to the gate are connected in parallel, A first conductivity type impurity introduction layer provided in a part of the polycrystalline semiconductor layer provided via a film, and a second conductivity type impurity introduction layer adjacent to the first conductivity type impurity introduction layer via a PN junction Forming a protection element inserted between the gate and the source of the semiconductor element, comprising a polycrystalline silicon layer having the same conductivity type as the gate electrode layer and having a lower impurity concentration than the gate electrode layer, Forming a gate protection resistor comprising a low impurity concentration region extending to the gate electrode layer, and integrating the polycrystalline silicon layer forming the gate protection resistor with the gate electrode layer to form the gate protection resistor. One end of a resistor is connected to the gate electrode layer; the other end of the gate protection resistor is connected to a gate extraction electrode; and the striped low impurity concentration region is between the gate electrode layer and the gate extraction electrode. A plurality of gate cells of the gate electrode layer extending in a shape such that the resistance length is short and the resistance width is long; one end of the protection element as a source extraction electrode; and the other end of the protection element as the gate. An insulated gate connected to a take-out electrode, wherein the impedance from the gate take-out electrode to the operating portion of the gate electrode is larger than the impedance of the protection element from the gate take-out electrode to the source take-out electrode. Type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63263107A JP2755619B2 (en) | 1988-10-19 | 1988-10-19 | Insulated gate semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63263107A JP2755619B2 (en) | 1988-10-19 | 1988-10-19 | Insulated gate semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02110976A JPH02110976A (en) | 1990-04-24 |
| JP2755619B2 true JP2755619B2 (en) | 1998-05-20 |
Family
ID=17384926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63263107A Expired - Lifetime JP2755619B2 (en) | 1988-10-19 | 1988-10-19 | Insulated gate semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2755619B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9207860D0 (en) * | 1992-04-09 | 1992-05-27 | Philips Electronics Uk Ltd | A semiconductor component |
| JP2956434B2 (en) * | 1992-10-30 | 1999-10-04 | 株式会社デンソー | Insulated semiconductor device |
| JP3255147B2 (en) | 1998-06-19 | 2002-02-12 | 株式会社デンソー | Surge protection circuit for insulated gate transistor |
| JP5391261B2 (en) * | 2000-03-06 | 2014-01-15 | ローム株式会社 | Semiconductor device |
| JP5309497B2 (en) * | 2007-08-09 | 2013-10-09 | 富士電機株式会社 | Semiconductor device |
| JP2015018950A (en) * | 2013-07-11 | 2015-01-29 | 株式会社東芝 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5029585B2 (en) * | 1972-07-24 | 1975-09-25 | ||
| JPS5825264A (en) * | 1981-08-07 | 1983-02-15 | Hitachi Ltd | Insulated gate semiconductor device |
-
1988
- 1988-10-19 JP JP63263107A patent/JP2755619B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02110976A (en) | 1990-04-24 |
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