JP2753011B2 - High breakdown voltage planar semiconductor device and method of manufacturing the same - Google Patents

Description

The present invention relates to a high breakdown voltage planar semiconductor device having a pn junction structure and a method for manufacturing the same.

(Prior art) Conventionally, as a high breakdown voltage planar type pn junction diode,
The structure shown in the figure is known. This, n ^- -type layer 21 p ⁺ -type layer 22 which is selectively formed by diffusion on the surface of the anode electrode 23, and the n contact to the p ⁺ -type layer ^- the low-resistance on the back surface of the mold layer 21 n ⁺ The cathode electrode 25 disposed via the mold layer 24 has a basic structure. Around the p ⁺ type layer 22 of such a diode, as a first low impurity concentration layer so as to be continuous therewith,
A p ⁻ -type layer 26 is formed by diffusion, and a p ⁻ -type layer 27 is formed as a second low-impurity-concentration layer around the diffusion so as to be continuous therewith. An n ⁺ -type layer 29 for fixing the surface potential of the n ⁻ -type layer 21 and an electrode 30 contacting the n ⁻ -type layer 21 are formed at a position further away from the p ⁻ -type layer 27 by a predetermined distance. p ^- type layer
The electric field concentrated on the edge of the p ⁺ -type layer 22 is reduced by the 26 and p ⁻ -type layers 27, and a high reverse breakdown voltage is obtained.

Although the structure shown in FIG. 7 can obtain a high withstand voltage, as a process for achieving a high withstand voltage, a p ^- type layer 26 having a low impurity concentration is formed using a first mask, and further a second mask is used. Therefore, two mask steps of forming the p ⁻ -type layer 27 having a lower impurity concentration are required. Therefore, there is a problem that the manufacturing process is complicated.

A similar problem also exists in other devices including a similar pn junction diode structure, for example, a MOS transistor, a conductive modulation type MOS transistor, a thyristor, and the like.

(Problems to be Solved by the Invention) As described above, in the conventional high breakdown voltage planar type semiconductor element, a plurality of mask processes for forming a plurality of low impurity concentration layers having different impurity concentrations are required to increase the breakdown voltage. There was a problem that.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a high breakdown voltage planar type semiconductor element capable of obtaining a breakdown voltage of the same level as a conventional semiconductor device through a simple process, and a method of manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) The present invention has a pn junction structure in which a second conductive type high impurity concentration layer is selectively formed on the surface of a first conductive type high resistance semiconductor layer. A high withstand voltage planar type semiconductor device, comprising a first low impurity concentration layer of a second conductivity type formed by diffusion around the high impurity concentration layer so as to be continuous with the high impurity concentration layer; And a plurality of second low impurity concentration layers having the same depth as the first low impurity diffusion layers formed so as to be continuous with and overlap with each other at the same impurity concentration. It is characterized by the following.

The invention also relates to the manufacture of such a semiconductor device,
The first low-impurity-concentration layer and the plurality of second low-impurity-concentration layers are formed by a single impurity introduction step using one mask having openings having different widths.

(Function) According to the present invention, the second low impurity concentration layers formed by multiple diffusion have the same impurity concentration as the first low impurity concentration layers, but have the same per unit area when viewed as a whole. Is lower than that of the first low impurity concentration layer. Therefore, unlike the conventional case, the impurity concentration is different.
1. This is equivalent to the case where the second low impurity concentration layer is continuously formed around the pn junction, and a high reverse breakdown voltage can be obtained. Moreover, according to the present invention, the first and second low impurity concentration layers can be formed by one impurity introduction step using one mask, and the manufacturing process is simplified.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 shows a main structure of a p ⁺ n junction diode according to one embodiment. A high impurity concentration p ⁺ type layer 2 serving as an anode is selectively formed on the surface of the n ⁻ type silicon layer 1. The diffusion depth of the p ⁺ type layer 2 is about 10 μm. p ⁺ -type layer 2 of p as the first low-impurity concentration layer continuously with this around ^- -type layer 6 is formed, the p ^- -type layer 6 and the second further continuous with this around the fourfold as low impurity concentration layer p ^- type layer 7 (7 ₁ to 7 ₄₎ is formed. These p ⁻ -type layers 6 and 7 are formed by one-time impurity diffusion using one mask. The p ^- type layers 7 partially overlap each other due to the lateral diffusion of impurities.

p ⁺ -type layer 2 and the p ^- wafer surface -type layer 6 is formed is covered with an oxide film 8, to which are opened the contact hole p ⁺
An anode electrode 3 that contacts the mold layer 2 is formed. On the wafer surface further away from the p ^- type layer 7 by a predetermined distance,
In order to fix the surface potential, an n ⁺ -type layer 9 and an electrode 10 in contact therewith are formed. On the back surface of the n ⁻ type silicon layer 1, a cathode electrode 5 is formed via an n ⁺ type layer 4.

FIG. 2 is an enlarged view showing a state where adjacent ones of the four p ^- type layers 7 in FIG. 1 partially overlap each other. W in the figure is the mask width when forming the p ⁻ -type layer 7. A p-type impurity is introduced from a mask opening formed at a distance of width W, and diffusion layers in a lateral direction are diffused in a subsequent thermal diffusion step so that diffusion layers partially overlap each other within the range of width W. Can be In some cases, the overlapping range of the diffusion layers may be larger than the mask width W.

FIG. 3 shows the steps of forming the p ^- type layers 6 and 7 of the diode according to this embodiment. As shown in FIG. 3A, an oxide film mask 11 is formed on the wafer surface on which the p ⁺ -type layer 2 is formed.
To form The openings 12 in the oxide film mask 11 are for obtaining the p ⁻ -type layer 6 which is the first low impurity concentration layer, and the plurality of openings 13 provided outside thereof are for the second low impurity concentration layer. This is for obtaining a certain p ^- type layer 7. Using the oxide film mask 11 thus patterned, p-type impurity ions are implanted. Thereafter, by performing thermal diffusion, the p ⁻ -type layers 6 and 7 partially overlapping each other as shown in FIG.
Get. The diffusion of the p ⁺ -type layer 2 after the ion implantation can be performed simultaneously with the diffusion of the p ^-- type layers 6 and 7. By setting conditions such that the diffusion width of the mask width in the region sandwiched by the openings 12 and 13 of the oxide film mask 11 by thermal diffusion is substantially the same, the p ^- type layer 7 formed by multiple diffusion is formed.
The region as a whole has an impurity concentration per unit area lower than that of the p ^- type layer 6, and is in a continuous state as a diffusion layer.

FIG. 4 shows the result of numerical analysis of the relationship between the total amount of impurities per unit area and the breakdown voltage of the p ⁺ n junction diode according to this embodiment as viewed from the surfaces of the p ⁻ -type layers 6 and 7. This data is obtained when the mask width for separating the p ⁻ type 6 and the plurality of p ⁻ type layers 7 is set to 5 μm. When the total amount of impurities is 1.87 × 10 ¹² / cm ² or more, the breakdown voltage sharply decreases. This total impurity amount is equal to that of the n ⁺ -type layer 2. Above this point, the effect of reducing the electric field concentration by providing a low impurity concentration layer for the p ⁺ -type layer 2 is lost. The total amount of impurities in p ^- type layers 6 and 7 is
At the point of 1.87 × 10 ¹² / cm ² , about 85% of the breakdown voltage of the flat junction except the edge of the junction between the p ⁺ type layer 2 and the n ⁻ type layer 1
Withstand pressure is obtained.

FIG. 5 shows the results of the relationship between the mask width separating the p ⁻ -type layers 6 and 7 from the breakdown voltage and the breakdown voltage of the diode of this embodiment also obtained by numerical analysis. A peak in the breakdown voltage is observed at a point where the mask width / diffusion depth is slightly smaller than 1 (point of 0.8 to 1.0). If the mask width is smaller than this, the overlap of the p ^- type layers 7 formed in a multiplex manner becomes too large and the impurity concentration per unit area does not change from that of the p ^- type layer 6, and the impurity concentration decreases gradually. Since the effect of forming the concentration layer in the high impurity concentration layer range is lost, the withstand voltage rapidly decreases. 0.92 mask width / diffusion depth
In this respect, a withstand voltage of about 85% with respect to the withstand voltage of the flat junction is obtained. When the mask width / diffusion depth is about 1.6 or more, the p ^- type layers 7 formed in a multiplexed manner are separated from each other without overlapping each other. For example, if the mask width / diffusion depth is 1.9,
The breakdown voltage drops to about 72% of the flat joint.

FIG. 6 shows a main structure of a p ⁺ n junction diode according to another embodiment of the present invention. Parts corresponding to those in FIG. 1 are denoted by the same reference numerals as in FIG. 1, and detailed description is omitted. The difference from the embodiment of FIG. 1 is that the semi-insulating layer is formed on the oxide film 8 on the wafer surface, extending from the p ⁺ -type layer 2 to the p ⁻ -type layers 6 and 7 and the outer n ⁻ -type layer 1. That is, the high resistance film 14 made of crystalline silicon or the like is provided. One end of the high resistance film 14 is connected to the anode electrode 3, and the other end is connected to the electrode 10. p ^-
The mold layers 6 and 7 are formed by a single impurity introduction step using a single mask, as in the previous embodiment.

According to this embodiment, when a reverse bias is applied to the pn junction, a uniform potential gradient is formed in the high resistance film 14, thereby preventing local concentration of the electric field. Higher reverse breakdown voltage can be obtained.

In the above embodiment, the p ^- type layer 7 as the second low-impurity-concentration layer is formed in four layers. However, the number of layers may be two or three, or five or more. In the embodiment, p ⁺ n
Although the junction diode has been described, the present invention can be applied to various high breakdown voltage planar semiconductor devices such as MOS transistors, thyristors, and conduction modulation type MOS transistors having the same diode structure.

[Effects of the Invention] As described above, according to the present invention, the impurity introduction step of forming a plurality of low impurity concentration layers for alleviating the electric field concentration can be performed with one mask, and at the same time as the conventional one. It is possible to obtain a high breakdown voltage planar type semiconductor element capable of obtaining a reverse breakdown voltage.

[Brief description of the drawings]

FIG. 1 is a view showing the structure of a principal part of a p ⁺ n junction diode according to an embodiment of the present invention, FIG. 2 is an enlarged view showing an overlapping state of the p ⁻ type layer 7, and FIG. FIG. 4B is a view for explaining the steps of forming the p ⁻ -type layers 6 and 7, and FIG. 4 is a numerical analysis of the relationship between the total amount of impurities in the p ⁻ -type layers 6 and 7 and the breakdown voltage in the structure of the above embodiment. FIG. 5 is a view showing the obtained results, FIG. 5 is a view showing the results obtained by numerical analysis of the relationship between the mask width separating the p ⁻ -type layer 7 and the breakdown voltage, and FIG. 6 is a view showing p of another embodiment of the present invention. FIG. 7 is a diagram showing a main structure of a ⁺ n junction diode, and FIG. 7 is a diagram showing a structure of a conventional high voltage p ⁺ n junction diode. 1 ...... n ^- -type silicon layer, 2 ...... p ⁺ -type layer, 3 ...... anode electrode, 4 ...... n ⁺ -type layer, 5 ...... cathode electrode, 6 ...... p ^- -type layer (a first low impurity concentration _{layer), 7 (7 1 ~7 4} ) ...... p - -type layer (a second low impurity concentration layer), 8 ...... oxide film, 9 ...... n ⁺ -type layer, 10 ...... electrodes, 11 ...... Oxide film mask, 12, 13 ... Opening, 14 ... High resistance film.

Claims (3)

(57) [Claims] 1. A high breakdown voltage planar type semiconductor device having a pn junction structure in which a second conductive type high impurity concentration layer is selectively formed on a surface of a first conductive type high resistance semiconductor layer. A first low-impurity-concentration layer of the second conductivity type diffused and formed so as to be continuous therewith, around the first low-impurity-concentration layer so as to be continuous therewith, and A plurality of second low-impurity-concentration layers formed so as to partially overlap each other with the same impurity concentration as that of the first low-impurity-concentration layer and to have substantially the same maximum depth. High breakdown voltage planar semiconductor device. 2. The high breakdown voltage planar according to claim 1, wherein the total amount of impurities per unit area of said first and second low impurity concentration layers is set to less than 1.87 × 10 ¹² / cm ^2. Type semiconductor element. 3. The method according to claim 1, wherein the first low impurity concentration layer and the second low impurity concentration layer have openings having different widths. A method for manufacturing a high breakdown voltage planar type semiconductor element, wherein the method is formed by a single impurity introduction step using one mask.