JP2749945B2 - Solid phase crystal growth method - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a solid phase crystal growth method, and more particularly, to an amorphous material applied to a three-dimensional integrated circuit or a constituent electronic element of a large-area electronic device. The present invention relates to a method for forming a semiconductor thin film on an insulator substrate.

[Problems to be solved by the prior art and the invention] In the field of growing a crystalline thin film on an amorphous substrate,
A method has been proposed in which an amorphous Si layer (thin film) is solid-phase grown on an amorphous insulating substrate (SiO ₂ ) by heat treatment at a low temperature. (T. Noguchi, H. Hayashi & H. Ohshima, 1987, Mat.
Res. Soc. Symp. Proc., 106, “Polysilicon and Interface
s, "P293, (Elsevier Science Publishing, New York 198
8)).

In this method, polycrystalline Si is deposited on SiO ₂ by LPCVD, and Si ⁺ ions are implanted into the polycrystalline Si to make it amorphous. Then 6
The crystal is grown by performing a heat treatment at a temperature of about 00 ° C.

However, in this method, but dendritic large crystal grains exceeding the maximum 10μm is obtained, is the other hand, the following particle size 1 [mu] m, per square centimeter ¹⁰⁶
Because the number of nuclei is not controlled, the particle size distribution is extremely wide. As a result, the transistors formed on the continuous film affect the distribution of the threshold value and the mobility, which is a very serious bottleneck in forming an integrated circuit. The present inventor has concluded from the results of many years of research that the origin of the grain size distribution of the polycrystalline film lies in the disordered existence of nucleation sites (origins) in the very early stage of thin film formation. However, as a result of intensive research focusing on the control of nucleation sites, we succeeded in controlling the position of nucleation sites in CVD (chemical vapor deposition) or in a solid phase.

(T.Yonehara, Y.Nishigaki, H.Mizutani, S.Kondoh, K.Tam
agata, T.Noma and T.Ichikawa, Applied Physics Letter
s, 52, 1231, 1988. (H, Kumomi and T. Yonera., Applied Physics Letters, 5
4,2648,1989. (Takao Yonehara, Hideya Kumomi, Nobuhiko Sato, Japanese Patent Application No. 1-110386)
No. 1) The crystal growth method disclosed in Japanese Patent Application No.
In a crystal growth method in which an amorphous thin film is crystallized by solid phase growth to form a thin film crystal, in the amorphous thin film, a small region having a smaller degree of implantation damage than other regions is formed by the amorphous thin film and the underlying film. Ions of the constituent material of the amorphous thin film are implanted so as to be formed near the interface with the substrate, and then heat treatment is performed at a temperature equal to or lower than the melting point of the amorphous thin film. One of the features is to form.

In this method, particularly in controlling nucleation sites in solid-phase growth, the non-nucleus formed region was formed by damaging the interface between the amorphous Si phase and the underlying substrate by ion implantation of the constituent material Si. Because of the heat treatment, dendritic crystals grow, and the rough grain boundaries are formed by the contact of the crystal end faces between the crystal grains, although the grain boundaries are controlled mainly in the small area where the degree of ion implantation damage is small. In some cases, the grain boundaries cannot be linear as shown in FIG. 2, and accurate grain boundary position control may not be achieved. The dendritic crystal mentioned here refers to a crystal having twin grain boundaries therein and growing by extending side branches in all directions. In the figure, reference numeral 8 denotes a grain boundary, and a region having a small degree of ion implantation damage is formed at the center of each crystal grain.

The variation in transistor characteristics made on the crystal thin film with the uniform grain size can be remarkably narrowed compared to that of the conventional solid phase growth film grown at random, but a higher performance device is obtained. Therefore, further improvement is desirable.

[Means and Actions for Solving the Problems] The present invention has been made to solve the above problems, and it is essential to precisely control and arrange the position, shape, and area of a crystal region. It was invented by the recognition that it was important.

That is, the present invention is based on the idea that a crystal should be formed so as to have a good crystal structure without forming a grain boundary which is a main cause of the device characteristic distribution in a specific pre-designed thin film region.

 FIG. 1 illustrates the gist of the present invention.

In FIG. 1A, an amorphous semiconductor layer is formed on an amorphous substrate so as to be separated to an optimum size for forming an element. The semiconductor layer is a photolithography usually used in the IC process,
This is performed using reactive ion etching. In the present invention, the size of the amorphous film to be separated is 5 to 10 μm on one side in the case of a corner.
m, and a circle having a diameter of about 5 to 10 μm is preferable.

As described in detail in Japanese Patent Application No. 01-110386, a nucleation site is formed at the center of each of the amorphous semiconductor islands separated by ion implantation, and a heat treatment is performed to form a single nucleus of a dendritic crystal. Is selectively solid-phase grown on the site (FIG. 1 (b)).

In other words, in the amorphous thin film, a minute region having a smaller degree of damage due to ion implantation than other regions is formed near the interface between the amorphous thin film and the base substrate.
Ions of the constituent material of the amorphous thin film are implanted, and then heat treatment is performed at a temperature lower than the melting point.

When the growth is continued as it is, the crystal in which a single nucleus is formed at each site is taken in the crystal phase by atoms crossing the amorphous / crystal phase boundary from the surrounding amorphous phase, and the crystal region expands. Eventually, the entire island is transformed into a crystal phase having a single domain, and no grain boundary is formed in the island region. This is because there is no separate crystal region grown from other nuclei in the island (FIG. 1 (c)). In the present invention, ion implantation is performed so that a single nucleus grows in each region of the amorphous thin film separately arranged.

However, there are no grain boundaries in the island, but due to dendritic crystals, twin planes remain as shown in FIG. 1 (c) and many crystal defects also exist. When crystal defects such as twins and dislocations are used for low-grade ones such as so-called thin-film transistors, twin planes and internal defects do not have as bad an effect as grain boundaries, but are as high as bulk. In the case of producing a performance element, it is fatal and removal of defects is indispensable.

For that purpose, heat treatment using incoherent light, which can heat-treat only a large-area batch thin film at a high temperature,
Optimal for this purpose. This is because the processing time (scanning time), controllability, and economical efficiency may become a problem because the beam diameter of coherent light, for example, laser light, is limited. For example, when incoherent light such as a lamp is used, batch large-area irradiation can be performed. Further, in the present invention, ion implantation is performed so that a single nucleus grows in each region of the amorphous thin film which is separately arranged, and thereafter, a crystal is grown by performing a heat treatment. After completion, it is preferable that no grain boundary exists in each region.

As described above, according to the present invention, a semiconductor island having a thin film-like flat single domain and having few crystal defects is formed on an amorphous substrate, and as a result, an electronic device having high performance and less variation is manufactured.

In the Example] (Example 1) A glass substrate like composed mainly of SiO _2, it was deposited an amorphous Si layer to a thickness of 100nm by vacuum CVD method.

The source gas was formed at 550 ° C. and a pressure of 0.3 Torr using SiH ₄ . This amorphous Si layer is implanted with 1 × 10 ¹⁵ ions / cm ² of Si ⁺ ions at the front surface at 40 KeV, and then a resist is applied.
15μm resist with 1μm diameter by normal lithography
The lattice points were left at m intervals.

Using this resist as a mask, Si ⁺ ions were implanted into the entire surface at 70 keV. The injection amount was 3 × 10 ¹⁵ ions / cm ² . 70keV
Due to the implantation energy, the projection range comes near the interface between 100 nm of Si and the SiO ₂ glass as the base material. As a result, the interface (Si / SiO ₂ ) was damaged in all regions except the resist having a diameter of 1 μm. After the resist was peeled off, the resist was re-applied, and a linear lattice-like groove having a width of 3 μm was formed in the amorphous Si layer in the middle of the lattice points by using reactive ion etching. That is, a plurality of 12 μm × 12 μm amorphous Si islands centered on the nucleation sites arranged in the lattice points were formed. Thereafter, heat treatment was performed at 630 ° C. for 80 hours in an N ₂ atmosphere. Then, as a result of observation with a transmission electron microscope, 12
All the regions of μm × 12 μm were transformed into crystals containing twin planes of a single domain, and there were no grain boundaries inside.

Furthermore, at 1300 ° C, 3
As a result of the heat treatment for minutes, residual defects inside the island are drastically reduced,
Bend-extion contours
Was observed over a wide area, and good crystallinity was shown.

Each of these crystal islands shows a carrier mobility equivalent to 90% of a device fabricated on bulk Si when a MOSFET (field effect transistor) is prototyped, and the variation in threshold value is comparable to that of a device fabricated on bulk. Was confirmed.

Example 2 SiH ₄ was thermally decomposed by a low pressure chemical vapor deposition method on a base material made of a plate-like glass, and a polycrystalline Si thin film was deposited to a thickness of 100 nm. The formation temperature was 620 ° C., the pressure was 0.3 Torr, and the particle size was fine, about 50 nm. Si implantation was performed twice. First, 40 keV implantation is performed on the entire surface without a resist mask, and Si ions are implanted into the polycrystalline Si layer with an energy of 3 × 10 ¹⁵ ions / cm ² , and the damage becomes continuous and becomes amorphous. Was. However, the projection range of 40 keV is located near the center of the film thickness of 100 nm, and as a result, there is almost no damage near the Si / SiO ₂ underlayer interface.

Thereafter, as in Example 1, a resist mask having a diameter of 1 μm was provided at lattice points at intervals of 15 μm, and a second Si ⁺ ion implantation was performed at 70 keV to introduce damage near the interface.
The injection amount was the same as the first injection. After the resist is peeled off, the resist is re-applied, and a linear lattice-like groove having a width of 3 μm is formed in the amorphous Si layer in the middle of the lattice points by using reactive ion etching. That is, a plurality of 12 μm × 12 μm amorphous Si islands centered on the nucleation sites arranged in the lattice points were formed. Thereafter, heat treatment was performed at 620 ° C. for 100 hours in N ₂ . As a result, similarly to the first embodiment, a 12 μm × 12 μm
A single domain crystal without a grain boundary is formed on the Si island.

Thick (Example 3) 50 nm amorphous Ge thin film, vacuum deposition by the electron beam on the underlying material formed of SiO _2. The degree of vacuum is 1 × 10
Deposited at ^-6 Torr, room temperature. 1.5μm depending on resist
Mask the area with a diameter and spacing of 15 μm, and use Ge ⁺
Inject at 30 keV. The injection amount was 2 × 10 ¹⁵ ions / cm ² . Ge ⁺ ions are implanted at a depth of about 50 nm from the surface, are mainly implanted intensively near the interface of the underlying substrate, and damage the interface. After removing the mask, a resist is applied again, and a linear lattice-shaped groove having a width of 3 μm is formed in the amorphous Ge layer by reactive ion etching between the lattice points. In other words, a plurality of 12 μm × 12 μm amorphous Ge islands were formed, centered on the nucleation sites arranged in the lattice points. Thereafter, when heat treatment was performed at 380 ° C. for 50 hours in N ₂ or in an H ₂ atmosphere, a single crystal was grown only from a small region covered with a mask and Ge ⁺ ions were not implanted and the interface was not damaged. Amorphous G with damage introduced at the interface by ⁺ ions
The crystal extended to the e region. As a result of examining the crystal structure with a transmission electron microscope, a single-domain crystal grows on each 12 μm × 12 μm island, and there is no grain boundary inside the island.

[Effect of the Invention] According to the present invention, a crystal region consisting of a single domain without a grain boundary at a low temperature can be formed at a desired position as a flat thin film.

Therefore, it is possible to manufacture an electronic element having small variations in characteristics over a large area.

[Brief description of the drawings]

FIG. 1 is a process chart showing the method of the present invention. FIG. 1A shows a state in which isolated amorphous semiconductor islands are arranged separately on an amorphous insulator substrate, and a nucleation site is artificially provided at the center of each island. . FIG. 1 (b) shows how a single nucleus is formed at an artificially formed nucleation site at the center of each island when the heat treatment is started. FIG. 1 (c) shows a state in which the entire island is finally crystallized, and a single-domain crystal without grain boundaries grows. FIG. 2 shows a conventional example, in which a thin film is not separated before growth, and shows a state in which a crystal grain boundary has a complicated shape as a result of solid phase growth while being connected. (Explanation of symbols) 1,6 ... Amorphous insulator substrate, 2 ... Amorphous semiconductor island, 3
... an artificial nucleation site, 4 ... a single nucleus (formed in a solid state at 3 places), 5 ... a crystal semiconductor island consisting of a single domain, 7 ... a crystal region consisting of a single domain, 8 ...
Grain boundaries.

Claims (1)

(57) [Claims] In a solid phase crystal growth method for controlling a crystal nucleus generation origin in a solid phase of an amorphous thin film, a plurality of amorphous thin films are separated from each other before growth, Disposing the plurality of amorphous thin films on the amorphous insulator substrate, forming a crystal nucleus origin such that a crystal grows from only a single nucleus in each of the amorphous thin films, A step of subjecting the crystal to solid phase growth by heat treatment at a temperature equal to or lower than the melting point of the amorphous thin film, and a step of irradiating the crystal grown after completion of the solid phase growth with incoherent light to remove defects inside the crystal. A solid phase crystal growth method characterized by comprising: